Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2015 Google, Inc |
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* |
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* (C) Copyright 2008-2014 Rockchip Electronics |
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* Peter, Software Engineering, <superpeter.cai@gmail.com>. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_CRU_RK3288_H |
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#define _ASM_ARCH_CRU_RK3288_H |
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#define OSC_HZ (24 * 1000 * 1000) |
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#define APLL_HZ (1800 * 1000000) |
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#define GPLL_HZ (594 * 1000000) |
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#define CPLL_HZ (384 * 1000000) |
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#define NPLL_HZ (384 * 1000000) |
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/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ |
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#define PD_BUS_ACLK_HZ 297000000 |
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#define PD_BUS_HCLK_HZ 148500000 |
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#define PD_BUS_PCLK_HZ 74250000 |
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#define PERI_ACLK_HZ 148500000 |
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#define PERI_HCLK_HZ 148500000 |
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#define PERI_PCLK_HZ 74250000 |
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struct rk3288_cru { |
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struct rk3288_pll { |
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u32 con0; |
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u32 con1; |
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u32 con2; |
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u32 con3; |
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} pll[5]; |
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u32 cru_mode_con; |
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u32 reserved0[3]; |
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u32 cru_clksel_con[43]; |
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u32 reserved1[21]; |
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u32 cru_clkgate_con[19]; |
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u32 reserved2; |
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u32 cru_glb_srst_fst_value; |
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u32 cru_glb_srst_snd_value; |
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u32 cru_softrst_con[12]; |
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u32 cru_misc_con; |
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u32 cru_glb_cnt_th; |
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u32 cru_glb_rst_con; |
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u32 reserved3; |
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u32 cru_glb_rst_st; |
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u32 reserved4; |
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u32 cru_sdmmc_con[2]; |
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u32 cru_sdio0_con[2]; |
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u32 cru_sdio1_con[2]; |
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u32 cru_emmc_con[2]; |
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}; |
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check_member(rk3288_cru, cru_emmc_con[1], 0x021c); |
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/* CRU_CLKSEL11_CON */ |
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enum { |
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HSICPHY_DIV_SHIFT = 8, |
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HSICPHY_DIV_MASK = 0x3f, |
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MMC0_PLL_SHIFT = 6, |
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MMC0_PLL_MASK = 3, |
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MMC0_PLL_SELECT_CODEC = 0, |
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MMC0_PLL_SELECT_GENERAL, |
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MMC0_PLL_SELECT_24MHZ, |
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MMC0_DIV_SHIFT = 0, |
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MMC0_DIV_MASK = 0x3f, |
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}; |
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/* CRU_CLKSEL12_CON */ |
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enum { |
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EMMC_PLL_SHIFT = 0xe, |
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EMMC_PLL_MASK = 3, |
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EMMC_PLL_SELECT_CODEC = 0, |
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EMMC_PLL_SELECT_GENERAL, |
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EMMC_PLL_SELECT_24MHZ, |
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EMMC_DIV_SHIFT = 8, |
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EMMC_DIV_MASK = 0x3f, |
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SDIO0_PLL_SHIFT = 6, |
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SDIO0_PLL_MASK = 3, |
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SDIO0_PLL_SELECT_CODEC = 0, |
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SDIO0_PLL_SELECT_GENERAL, |
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SDIO0_PLL_SELECT_24MHZ, |
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SDIO0_DIV_SHIFT = 0, |
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SDIO0_DIV_MASK = 0x3f, |
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}; |
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/* CRU_CLKSEL25_CON */ |
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enum { |
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SPI1_PLL_SHIFT = 0xf, |
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SPI1_PLL_MASK = 1, |
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SPI1_PLL_SELECT_CODEC = 0, |
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SPI1_PLL_SELECT_GENERAL, |
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SPI1_DIV_SHIFT = 8, |
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SPI1_DIV_MASK = 0x7f, |
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SPI0_PLL_SHIFT = 7, |
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SPI0_PLL_MASK = 1, |
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SPI0_PLL_SELECT_CODEC = 0, |
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SPI0_PLL_SELECT_GENERAL, |
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SPI0_DIV_SHIFT = 0, |
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SPI0_DIV_MASK = 0x7f, |
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}; |
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/* CRU_CLKSEL39_CON */ |
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enum { |
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ACLK_HEVC_PLL_SHIFT = 0xe, |
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ACLK_HEVC_PLL_MASK = 3, |
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ACLK_HEVC_PLL_SELECT_CODEC = 0, |
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ACLK_HEVC_PLL_SELECT_GENERAL, |
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ACLK_HEVC_PLL_SELECT_NEW, |
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ACLK_HEVC_DIV_SHIFT = 8, |
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ACLK_HEVC_DIV_MASK = 0x1f, |
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SPI2_PLL_SHIFT = 7, |
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SPI2_PLL_MASK = 1, |
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SPI2_PLL_SELECT_CODEC = 0, |
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SPI2_PLL_SELECT_GENERAL, |
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SPI2_DIV_SHIFT = 0, |
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SPI2_DIV_MASK = 0x7f, |
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}; |
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/* CRU_MODE_CON */ |
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enum { |
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NPLL_WORK_SHIFT = 0xe, |
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NPLL_WORK_MASK = 3, |
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NPLL_WORK_SLOW = 0, |
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NPLL_WORK_NORMAL, |
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NPLL_WORK_DEEP, |
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GPLL_WORK_SHIFT = 0xc, |
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GPLL_WORK_MASK = 3, |
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GPLL_WORK_SLOW = 0, |
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GPLL_WORK_NORMAL, |
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GPLL_WORK_DEEP, |
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CPLL_WORK_SHIFT = 8, |
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CPLL_WORK_MASK = 3, |
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CPLL_WORK_SLOW = 0, |
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CPLL_WORK_NORMAL, |
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CPLL_WORK_DEEP, |
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DPLL_WORK_SHIFT = 4, |
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DPLL_WORK_MASK = 3, |
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DPLL_WORK_SLOW = 0, |
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DPLL_WORK_NORMAL, |
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DPLL_WORK_DEEP, |
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APLL_WORK_SHIFT = 0, |
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APLL_WORK_MASK = 3, |
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APLL_WORK_SLOW = 0, |
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APLL_WORK_NORMAL, |
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APLL_WORK_DEEP, |
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}; |
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/* CRU_APLL_CON0 */ |
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enum { |
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CLKR_SHIFT = 8, |
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CLKR_MASK = 0x3f, |
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CLKOD_SHIFT = 0, |
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CLKOD_MASK = 0xf, |
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}; |
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/* CRU_APLL_CON1 */ |
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enum { |
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LOCK_SHIFT = 0x1f, |
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LOCK_MASK = 1, |
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LOCK_UNLOCK = 0, |
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LOCK_LOCK, |
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CLKF_SHIFT = 0, |
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CLKF_MASK = 0x1fff, |
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}; |
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#endif |
@ -0,0 +1,618 @@ |
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/*
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* (C) Copyright 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3288.h> |
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#include <asm/arch/grf_rk3288.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/periph.h> |
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#include <dm/lists.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct rk3288_clk_plat { |
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enum rk_clk_id clk_id; |
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}; |
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struct rk3288_clk_priv { |
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struct rk3288_grf *grf; |
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struct rk3288_cru *cru; |
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ulong rate; |
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}; |
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struct pll_div { |
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u32 nr; |
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u32 nf; |
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u32 no; |
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}; |
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enum { |
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VCO_MAX_HZ = 2200U * 1000000, |
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VCO_MIN_HZ = 440 * 1000000, |
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OUTPUT_MAX_HZ = 2200U * 1000000, |
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OUTPUT_MIN_HZ = 27500000, |
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FREF_MAX_HZ = 2200U * 1000000, |
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FREF_MIN_HZ = 269 * 1000000, |
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}; |
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enum { |
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/* PLL CON0 */ |
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PLL_OD_MASK = 0x0f, |
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/* PLL CON1 */ |
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PLL_NF_MASK = 0x1fff, |
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/* PLL CON2 */ |
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PLL_BWADJ_MASK = 0x0fff, |
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/* PLL CON3 */ |
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PLL_RESET_SHIFT = 5, |
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/* CLKSEL1: pd bus clk pll sel: codec or general */ |
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PD_BUS_SEL_PLL_MASK = 15, |
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PD_BUS_SEL_CPLL = 0, |
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PD_BUS_SEL_GPLL, |
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/* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ |
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PD_BUS_PCLK_DIV_SHIFT = 12, |
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PD_BUS_PCLK_DIV_MASK = 7, |
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/* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ |
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PD_BUS_HCLK_DIV_SHIFT = 8, |
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PD_BUS_HCLK_DIV_MASK = 3, |
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/* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ |
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PD_BUS_ACLK_DIV0_SHIFT = 3, |
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PD_BUS_ACLK_DIV0_MASK = 0x1f, |
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PD_BUS_ACLK_DIV1_SHIFT = 0, |
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PD_BUS_ACLK_DIV1_MASK = 0x7, |
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/*
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* CLKSEL10 |
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* peripheral bus pclk div: |
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* aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 |
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*/ |
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PERI_PCLK_DIV_SHIFT = 12, |
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PERI_PCLK_DIV_MASK = 7, |
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/* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ |
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PERI_HCLK_DIV_SHIFT = 8, |
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PERI_HCLK_DIV_MASK = 3, |
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/*
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* peripheral bus aclk div: |
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* aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) |
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*/ |
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PERI_ACLK_DIV_SHIFT = 0, |
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PERI_ACLK_DIV_MASK = 0x1f, |
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/* CLKSEL37 */ |
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DPLL_MODE_MASK = 0x3, |
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DPLL_MODE_SHIFT = 4, |
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DPLL_MODE_SLOW = 0, |
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DPLL_MODE_NORM, |
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CPLL_MODE_MASK = 3, |
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CPLL_MODE_SHIFT = 8, |
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CPLL_MODE_SLOW = 0, |
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CPLL_MODE_NORM, |
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GPLL_MODE_MASK = 3, |
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GPLL_MODE_SHIFT = 12, |
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GPLL_MODE_SLOW = 0, |
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GPLL_MODE_NORM, |
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NPLL_MODE_MASK = 3, |
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NPLL_MODE_SHIFT = 14, |
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NPLL_MODE_SLOW = 0, |
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NPLL_MODE_NORM, |
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SOCSTS_DPLL_LOCK = 1 << 5, |
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SOCSTS_APLL_LOCK = 1 << 6, |
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SOCSTS_CPLL_LOCK = 1 << 7, |
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SOCSTS_GPLL_LOCK = 1 << 8, |
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SOCSTS_NPLL_LOCK = 1 << 9, |
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}; |
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#define RATE_TO_DIV(input_rate, output_rate) \ |
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((input_rate) / (output_rate) - 1); |
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
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#define PLL_DIVISORS(hz, _nr, _no) {\ |
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.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
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_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__)); |
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/* Keep divisors as low as possible to reduce jitter and power usage */ |
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); |
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); |
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); |
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static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, |
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const struct pll_div *div) |
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{ |
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int pll_id = rk_pll_id(clk_id); |
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struct rk3288_pll *pll = &cru->pll[pll_id]; |
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/* All PLLs have same VCO and output frequency range restrictions. */ |
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uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; |
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uint output_hz = vco_hz / div->no; |
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debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
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pll, div->nf, div->nr, div->no, vco_hz, output_hz); |
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && |
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && |
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(div->no == 1 || !(div->no % 2))); |
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/* enter rest */ |
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rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
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rk_clrsetreg(&pll->con0, |
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CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, |
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((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); |
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rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); |
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rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); |
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udelay(10); |
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/* return form rest */ |
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rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
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return 0; |
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} |
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static inline unsigned int log2(unsigned int value) |
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{ |
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return fls(value) - 1; |
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} |
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static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, |
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unsigned int hz) |
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{ |
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static const struct pll_div dpll_cfg[] = { |
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{.nf = 25, .nr = 2, .no = 1}, |
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{.nf = 400, .nr = 9, .no = 2}, |
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{.nf = 500, .nr = 9, .no = 2}, |
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{.nf = 100, .nr = 3, .no = 1}, |
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}; |
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int cfg; |
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debug("%s: cru=%p, grf=%p, hz=%u\n", __func__, cru, grf, hz); |
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switch (hz) { |
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case 300000000: |
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cfg = 0; |
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break; |
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case 533000000: /* actually 533.3P MHz */ |
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cfg = 1; |
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break; |
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case 666000000: /* actually 666.6P MHz */ |
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cfg = 2; |
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break; |
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case 800000000: |
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cfg = 3; |
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break; |
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default: |
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debug("Unsupported SDRAM frequency, add to clock.c!"); |
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return -EINVAL; |
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} |
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/* pll enter slow-mode */ |
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, |
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DPLL_MODE_SLOW << DPLL_MODE_SHIFT); |
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rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); |
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/* wait for pll lock */ |
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while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) |
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udelay(1); |
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/* PLL enter normal-mode */ |
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, |
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DPLL_MODE_NORM << DPLL_MODE_SHIFT); |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) |
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{ |
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u32 aclk_div; |
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u32 hclk_div; |
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u32 pclk_div; |
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/* pll enter slow-mode */ |
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rk_clrsetreg(&cru->cru_mode_con, |
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GPLL_MODE_MASK << GPLL_MODE_SHIFT | |
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CPLL_MODE_MASK << CPLL_MODE_SHIFT, |
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT | |
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CPLL_MODE_SLOW << CPLL_MODE_SHIFT); |
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/* init pll */ |
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); |
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rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); |
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/* waiting for pll lock */ |
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while ((readl(&grf->soc_status[1]) & |
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != |
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) |
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udelay(1); |
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/*
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* pd_bus clock pll source selection and |
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* set up dependent divisors for PCLK/HCLK and ACLK clocks. |
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*/ |
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aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; |
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assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
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hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; |
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assert((hclk_div + 1) * PD_BUS_HCLK_HZ == |
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PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); |
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pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; |
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assert((pclk_div + 1) * PD_BUS_PCLK_HZ == |
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PD_BUS_ACLK_HZ && pclk_div < 0x7); |
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rk_clrsetreg(&cru->cru_clksel_con[1], |
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PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT | |
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PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT | |
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PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT | |
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PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT, |
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pclk_div << PD_BUS_PCLK_DIV_SHIFT | |
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hclk_div << PD_BUS_HCLK_DIV_SHIFT | |
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aclk_div << PD_BUS_ACLK_DIV0_SHIFT | |
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0 << 0); |
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/*
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* peri clock pll source selection and |
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* set up dependent divisors for PCLK/HCLK and ACLK clocks. |
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*/ |
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; |
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
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hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
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assert((1 << hclk_div) * PERI_HCLK_HZ == |
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PERI_ACLK_HZ && (hclk_div < 0x4)); |
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pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
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assert((1 << pclk_div) * PERI_PCLK_HZ == |
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PERI_ACLK_HZ && (pclk_div < 0x4)); |
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rk_clrsetreg(&cru->cru_clksel_con[10], |
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PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | |
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PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | |
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PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, |
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pclk_div << PERI_PCLK_DIV_SHIFT | |
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hclk_div << PERI_HCLK_DIV_SHIFT | |
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aclk_div << PERI_ACLK_DIV_SHIFT); |
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/* PLL enter normal-mode */ |
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rk_clrsetreg(&cru->cru_mode_con, |
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GPLL_MODE_MASK << GPLL_MODE_SHIFT | |
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CPLL_MODE_MASK << CPLL_MODE_SHIFT, |
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GPLL_MODE_NORM << GPLL_MODE_SHIFT | |
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GPLL_MODE_NORM << CPLL_MODE_SHIFT); |
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} |
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#endif |
||||
|
||||
/* Get pll rate by id */ |
||||
static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, |
||||
enum rk_clk_id clk_id) |
||||
{ |
||||
uint32_t nr, no, nf; |
||||
uint32_t con; |
||||
int pll_id = rk_pll_id(clk_id); |
||||
struct rk3288_pll *pll = &cru->pll[pll_id]; |
||||
static u8 clk_shift[CLK_COUNT] = { |
||||
0xff, APLL_WORK_SHIFT, DPLL_WORK_SHIFT, CPLL_WORK_SHIFT, |
||||
GPLL_WORK_SHIFT, NPLL_WORK_SHIFT |
||||
}; |
||||
uint shift; |
||||
|
||||
con = readl(&cru->cru_mode_con); |
||||
shift = clk_shift[clk_id]; |
||||
switch ((con >> shift) & APLL_WORK_MASK) { |
||||
case APLL_WORK_SLOW: |
||||
return OSC_HZ; |
||||
case APLL_WORK_NORMAL: |
||||
/* normal mode */ |
||||
con = readl(&pll->con0); |
||||
no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; |
||||
nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; |
||||
con = readl(&pll->con1); |
||||
nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; |
||||
|
||||
return (24 * nf / (nr * no)) * 1000000; |
||||
case APLL_WORK_DEEP: |
||||
default: |
||||
return 32768; |
||||
} |
||||
} |
||||
|
||||
static ulong rk3288_clk_get_rate(struct udevice *dev) |
||||
{ |
||||
struct rk3288_clk_plat *plat = dev_get_platdata(dev); |
||||
struct rk3288_clk_priv *priv = dev_get_priv(dev); |
||||
|
||||
debug("%s\n", dev->name); |
||||
return rkclk_pll_get_rate(priv->cru, plat->clk_id); |
||||
} |
||||
|
||||
static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate) |
||||
{ |
||||
struct rk3288_clk_plat *plat = dev_get_platdata(dev); |
||||
struct rk3288_clk_priv *priv = dev_get_priv(dev); |
||||
|
||||
debug("%s\n", dev->name); |
||||
switch (plat->clk_id) { |
||||
case CLK_DDR: |
||||
rkclk_configure_ddr(priv->cru, priv->grf, rate); |
||||
break; |
||||
default: |
||||
return -ENOENT; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint clk_general_rate, |
||||
enum periph_id periph) |
||||
{ |
||||
uint src_rate; |
||||
uint div, mux; |
||||
u32 con; |
||||
|
||||
switch (periph) { |
||||
case PERIPH_ID_EMMC: |
||||
con = readl(&cru->cru_clksel_con[12]); |
||||
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; |
||||
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; |
||||
break; |
||||
case PERIPH_ID_SDCARD: |
||||
con = readl(&cru->cru_clksel_con[12]); |
||||
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; |
||||
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; |
||||
break; |
||||
case PERIPH_ID_SDMMC2: |
||||
con = readl(&cru->cru_clksel_con[12]); |
||||
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; |
||||
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : clk_general_rate; |
||||
return DIV_TO_RATE(src_rate, div); |
||||
} |
||||
|
||||
static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint clk_general_rate, |
||||
enum periph_id periph, uint freq) |
||||
{ |
||||
int src_clk_div; |
||||
int mux; |
||||
|
||||
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); |
||||
src_clk_div = RATE_TO_DIV(clk_general_rate, freq); |
||||
|
||||
if (src_clk_div > 0x3f) { |
||||
src_clk_div = RATE_TO_DIV(OSC_HZ, freq); |
||||
mux = EMMC_PLL_SELECT_24MHZ; |
||||
assert((int)EMMC_PLL_SELECT_24MHZ == |
||||
(int)MMC0_PLL_SELECT_24MHZ); |
||||
} else { |
||||
mux = EMMC_PLL_SELECT_GENERAL; |
||||
assert((int)EMMC_PLL_SELECT_GENERAL == |
||||
(int)MMC0_PLL_SELECT_GENERAL); |
||||
} |
||||
switch (periph) { |
||||
case PERIPH_ID_EMMC: |
||||
rk_clrsetreg(&cru->cru_clksel_con[12], |
||||
EMMC_PLL_MASK << EMMC_PLL_SHIFT | |
||||
EMMC_DIV_MASK << EMMC_DIV_SHIFT, |
||||
mux << EMMC_PLL_SHIFT | |
||||
(src_clk_div - 1) << EMMC_DIV_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SDCARD: |
||||
rk_clrsetreg(&cru->cru_clksel_con[11], |
||||
MMC0_PLL_MASK << MMC0_PLL_SHIFT | |
||||
MMC0_DIV_MASK << MMC0_DIV_SHIFT, |
||||
mux << MMC0_PLL_SHIFT | |
||||
(src_clk_div - 1) << MMC0_DIV_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SDMMC2: |
||||
rk_clrsetreg(&cru->cru_clksel_con[12], |
||||
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | |
||||
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, |
||||
mux << SDIO0_PLL_SHIFT | |
||||
(src_clk_div - 1) << SDIO0_DIV_SHIFT); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return rockchip_mmc_get_clk(cru, clk_general_rate, periph); |
||||
} |
||||
|
||||
static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint clk_general_rate, |
||||
enum periph_id periph) |
||||
{ |
||||
uint div, mux; |
||||
u32 con; |
||||
|
||||
switch (periph) { |
||||
case PERIPH_ID_SPI0: |
||||
con = readl(&cru->cru_clksel_con[25]); |
||||
mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK; |
||||
div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; |
||||
break; |
||||
case PERIPH_ID_SPI1: |
||||
con = readl(&cru->cru_clksel_con[25]); |
||||
mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK; |
||||
div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; |
||||
break; |
||||
case PERIPH_ID_SPI2: |
||||
con = readl(&cru->cru_clksel_con[39]); |
||||
mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK; |
||||
div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK; |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
assert(mux == SPI0_PLL_SELECT_GENERAL); |
||||
|
||||
return DIV_TO_RATE(clk_general_rate, div); |
||||
} |
||||
|
||||
static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint clk_general_rate, |
||||
enum periph_id periph, uint freq) |
||||
{ |
||||
int src_clk_div; |
||||
|
||||
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); |
||||
src_clk_div = RATE_TO_DIV(clk_general_rate, freq); |
||||
switch (periph) { |
||||
case PERIPH_ID_SPI0: |
||||
rk_clrsetreg(&cru->cru_clksel_con[25], |
||||
SPI0_PLL_MASK << SPI0_PLL_SHIFT | |
||||
SPI0_DIV_MASK << SPI0_DIV_SHIFT, |
||||
SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | |
||||
src_clk_div << SPI0_DIV_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SPI1: |
||||
rk_clrsetreg(&cru->cru_clksel_con[25], |
||||
SPI1_PLL_MASK << SPI1_PLL_SHIFT | |
||||
SPI1_DIV_MASK << SPI1_DIV_SHIFT, |
||||
SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | |
||||
src_clk_div << SPI1_DIV_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SPI2: |
||||
rk_clrsetreg(&cru->cru_clksel_con[39], |
||||
SPI2_PLL_MASK << SPI2_PLL_SHIFT | |
||||
SPI2_DIV_MASK << SPI2_DIV_SHIFT, |
||||
SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | |
||||
src_clk_div << SPI2_DIV_SHIFT); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return rockchip_spi_get_clk(cru, clk_general_rate, periph); |
||||
} |
||||
|
||||
ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate) |
||||
{ |
||||
struct rk3288_clk_priv *priv = dev_get_priv(dev); |
||||
ulong new_rate; |
||||
|
||||
switch (periph) { |
||||
case PERIPH_ID_EMMC: |
||||
case PERIPH_ID_SDCARD: |
||||
new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev), |
||||
periph, rate); |
||||
break; |
||||
case PERIPH_ID_SPI0: |
||||
case PERIPH_ID_SPI1: |
||||
case PERIPH_ID_SPI2: |
||||
new_rate = rockchip_spi_set_clk(priv->cru, clk_get_rate(dev), |
||||
periph, rate); |
||||
break; |
||||
default: |
||||
return -ENOENT; |
||||
} |
||||
|
||||
return new_rate; |
||||
} |
||||
|
||||
static struct clk_ops rk3288_clk_ops = { |
||||
.get_rate = rk3288_clk_get_rate, |
||||
.set_rate = rk3288_clk_set_rate, |
||||
.set_periph_rate = rk3288_set_periph_rate, |
||||
}; |
||||
|
||||
static int rk3288_clk_probe(struct udevice *dev) |
||||
{ |
||||
struct rk3288_clk_plat *plat = dev_get_platdata(dev); |
||||
struct rk3288_clk_priv *priv = dev_get_priv(dev); |
||||
|
||||
if (plat->clk_id != CLK_OSC) { |
||||
struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent); |
||||
|
||||
priv->cru = parent_priv->cru; |
||||
priv->grf = parent_priv->grf; |
||||
return 0; |
||||
} |
||||
priv->cru = (struct rk3288_cru *)dev_get_addr(dev); |
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
||||
#ifdef CONFIG_SPL_BUILD |
||||
rkclk_init(priv->cru, priv->grf); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const char *const clk_name[CLK_COUNT] = { |
||||
"osc", |
||||
"apll", |
||||
"dpll", |
||||
"cpll", |
||||
"gpll", |
||||
"mpll", |
||||
}; |
||||
|
||||
static int rk3288_clk_bind(struct udevice *dev) |
||||
{ |
||||
struct rk3288_clk_plat *plat = dev_get_platdata(dev); |
||||
int pll, ret; |
||||
|
||||
/* We only need to set up the root clock */ |
||||
if (dev->of_offset == -1) { |
||||
plat->clk_id = CLK_OSC; |
||||
return 0; |
||||
} |
||||
|
||||
/* Create devices for P main clocks */ |
||||
for (pll = 1; pll < CLK_COUNT; pll++) { |
||||
struct udevice *child; |
||||
struct rk3288_clk_plat *cplat; |
||||
|
||||
debug("%s %s\n", __func__, clk_name[pll]); |
||||
ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll], |
||||
&child); |
||||
if (ret) |
||||
return ret; |
||||
cplat = dev_get_platdata(child); |
||||
cplat->clk_id = pll; |
||||
} |
||||
|
||||
/* The reset driver does not have a device node, so bind it here */ |
||||
ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev); |
||||
if (ret) |
||||
debug("Warning: No RK3288 reset driver: ret=%d\n", ret); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id rk3288_clk_ids[] = { |
||||
{ .compatible = "rockchip,rk3288-cru" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(clk_rk3288) = { |
||||
.name = "clk_rk3288", |
||||
.id = UCLASS_CLK, |
||||
.of_match = rk3288_clk_ids, |
||||
.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), |
||||
.platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), |
||||
.ops = &rk3288_clk_ops, |
||||
.bind = rk3288_clk_bind, |
||||
.probe = rk3288_clk_probe, |
||||
}; |
Loading…
Reference in new issue