This patch adds support for the Calimain board from OMICRON electronics GmbH. The board features a Texas Instruments AM1808 SoC, 128 MB DDR2 memory, and 64 MB NOR flash memory connected to CS2 and CS3. Signed-off-by: Christian Riesch <christian.riesch@omicron.at>master
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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/*
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* Copyright (C) 2011 OMICRON electronics GmbH |
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* |
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* Based on da850evm.c. Original Copyrights follow: |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <watchdog.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/emif_defs.h> |
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#include <asm/arch/emac_defs.h> |
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#include <asm/arch/pinmux_defs.h> |
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#include <asm/arch/davinci_misc.h> |
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#include <asm/arch/timer_defs.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CALIMAIN_HWVERSION_MASK 0x7f000000 |
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#define CALIMAIN_HWVERSION_SHIFT 24 |
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/* Hardware version pinmux settings */ |
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const struct pinmux_config hwversion_pins[] = { |
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{ pinmux(16), 8, 2 }, /* GP7[15] */ |
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{ pinmux(16), 8, 3 }, /* GP7[14] */ |
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{ pinmux(16), 8, 4 }, /* GP7[13] */ |
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{ pinmux(16), 8, 5 }, /* GP7[12] */ |
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{ pinmux(16), 8, 6 }, /* GP7[11] */ |
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{ pinmux(16), 8, 7 }, /* GP7[10] */ |
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{ pinmux(17), 8, 0 }, /* GP7[9] */ |
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{ pinmux(17), 8, 1 } /* GP7[8] */ |
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}; |
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const struct pinmux_resource pinmuxes[] = { |
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PINMUX_ITEM(uart2_pins_txrx), |
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PINMUX_ITEM(emac_pins_mii), |
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PINMUX_ITEM(emac_pins_mdio), |
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PINMUX_ITEM(emifa_pins_nor), |
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PINMUX_ITEM(emifa_pins_cs2), |
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PINMUX_ITEM(emifa_pins_cs3), |
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}; |
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes); |
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const struct lpsc_resource lpsc[] = { |
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ |
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{ DAVINCI_LPSC_EMAC }, /* image download */ |
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{ DAVINCI_LPSC_UART2 }, /* console */ |
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{ DAVINCI_LPSC_GPIO }, |
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}; |
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const int lpsc_size = ARRAY_SIZE(lpsc); |
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/* read board revision from GPIO7[8..14] */ |
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u32 get_board_rev(void) |
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{ |
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lpsc_on(DAVINCI_LPSC_GPIO); |
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if (davinci_configure_pin_mux(hwversion_pins, |
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ARRAY_SIZE(hwversion_pins)) != 0) |
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return 0xffffffff; |
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return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK) |
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>> CALIMAIN_HWVERSION_SHIFT; |
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} |
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/*
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* determine the oscillator frequency depending on the board revision |
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* |
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* rev 0x00 ... 25 MHz oscillator |
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* rev 0x01 ... 24 MHz oscillator |
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*/ |
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int calimain_get_osc_freq(void) |
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{ |
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u32 rev; |
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int freq; |
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rev = get_board_rev(); |
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switch (rev) { |
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case 0x00: |
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freq = 25000000; |
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break; |
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default: |
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freq = 24000000; |
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break; |
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} |
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return freq; |
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} |
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int board_init(void) |
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{ |
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int val; |
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#ifndef CONFIG_USE_IRQ |
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irq_init(); |
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#endif |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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/* select emac MII mode */ |
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val = readl(&davinci_syscfg_regs->cfgchip3); |
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val &= ~(1 << 8); |
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writel(val, &davinci_syscfg_regs->cfgchip3); |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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#ifdef CONFIG_HW_WATCHDOG |
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davinci_hw_watchdog_enable(); |
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#endif |
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printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq()); |
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printf("Board revision: %d\n", get_board_rev()); |
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return 0; |
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} |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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/*
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* Initializes on-board ethernet controllers. |
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*/ |
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int board_eth_init(bd_t *bis) |
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{ |
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if (!davinci_emac_initialize()) { |
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printf("Error: Ethernet init failed!\n"); |
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return -1; |
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} |
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return 0; |
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} |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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#ifdef CONFIG_HW_WATCHDOG |
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void hw_watchdog_reset(void) |
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{ |
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davinci_hw_watchdog_reset(); |
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} |
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#endif |
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#if defined(CONFIG_BOOTCOUNT_LIMIT) |
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void bootcount_store(ulong a) |
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{ |
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struct davinci_rtc *reg = |
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(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; |
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/*
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* write RTC kick register to enable write |
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* for RTC Scratch registers. Cratch0 and 1 are |
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* used for bootcount values. |
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*/ |
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writel(RTC_KICK0R_WE, ®->kick0r); |
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writel(RTC_KICK1R_WE, ®->kick1r); |
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writel(a, ®->scratch0); |
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writel(BOOTCOUNT_MAGIC, ®->scratch1); |
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} |
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ulong bootcount_load(void) |
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{ |
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struct davinci_rtc *reg = |
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(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; |
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if (readl(®->scratch1) != BOOTCOUNT_MAGIC) |
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return 0; |
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else |
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return readl(®->scratch0); |
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} |
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#endif |
@ -0,0 +1,363 @@ |
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/*
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* Copyright (C) 2011 OMICRON electronics GmbH |
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* |
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* Based on da850evm.h. Original Copyrights follow: |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* Board |
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*/ |
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#define CONFIG_DRIVER_TI_EMAC |
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#define MACH_TYPE_CALIMAIN 3528 |
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#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN |
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/*
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* SoC Configuration |
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*/ |
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#define CONFIG_MACH_DAVINCI_CALIMAIN |
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
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#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() |
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_SYS_TEXT_BASE 0x60000000 |
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#define CONFIG_DA850_LOWLEVEL |
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#define CONFIG_SYS_DA850_PLL_INIT |
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#define CONFIG_SYS_DA850_DDR_INIT |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_DA8XX_GPIO |
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#define CONFIG_HW_WATCHDOG |
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#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE |
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#define CONFIG_SYS_WDT_PERIOD_LOW \ |
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(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ |
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#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 |
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#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) |
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/*
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* PLL configuration |
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*/ |
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#define CONFIG_SYS_DV_CLKMODE 0 |
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 |
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 |
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 |
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 |
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 |
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#define CONFIG_SYS_DA850_PLL0_PLLM \ |
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((calimain_get_osc_freq() == 25000000) ? 23 : 24) |
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#define CONFIG_SYS_DA850_PLL1_PLLM \ |
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((calimain_get_osc_freq() == 25000000) ? 20 : 21) |
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/*
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* DDR2 memory configuration |
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*/ |
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ |
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) |
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ |
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) |
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ |
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 |
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ |
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(16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(7 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WTR_SHIFT)) |
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ |
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT)) |
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF |
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 |
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/*
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* Flash memory timing |
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*/ |
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#define CONFIG_SYS_DA850_CS2CFG ( \ |
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DAVINCI_ABCR_WSETUP(2) | \
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DAVINCI_ABCR_WSTROBE(5) | \
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DAVINCI_ABCR_WHOLD(3) | \
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DAVINCI_ABCR_RSETUP(1) | \
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DAVINCI_ABCR_RSTROBE(14) | \
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DAVINCI_ABCR_RHOLD(0) | \
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DAVINCI_ABCR_TA(3) | \
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DAVINCI_ABCR_ASIZE_16BIT) |
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/* single 64 MB NOR flash device connected to CS2 and CS3 */ |
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#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG |
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/*
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* Memory Info |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ |
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C) |
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/* memtest start addr */ |
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) |
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/* memtest will be run on 16MB */ |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) |
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
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/*
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* Serial Driver info |
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*/ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ |
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ |
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ |
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#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ |
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#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE |
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ |
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#define CONFIG_ENV_ADDR \ |
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(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) |
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#define CONFIG_ENV_SIZE (128 << 10) |
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
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#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ |
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#define CONFIG_SYS_MAX_FLASH_SECT \ |
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((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) |
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/*
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* Network & Ethernet Configuration |
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*/ |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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#define CONFIG_EMAC_MDIO_PHY_NUM 1 |
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#define CONFIG_MII |
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#define CONFIG_BOOTP_DEFAULT |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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#define CONFIG_NET_RETRY_COUNT 10 |
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#endif |
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/*
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* U-Boot general configuration |
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*/ |
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
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#define CONFIG_SYS_PROMPT "Calimain > " /* Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) |
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#define CONFIG_LOADADDR 0xc0700000 |
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#define CONFIG_VERSION_VARIABLE |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
|
||||
/*
|
||||
* Linux Information |
||||
*/ |
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "" |
||||
#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" |
||||
#define CONFIG_BOOTDELAY 0 |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ |
||||
#define CONFIG_AUTOBOOT_KEYED |
||||
#define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */ |
||||
#define CONFIG_RESET_TO_RETRY |
||||
|
||||
/*
|
||||
* Default environment settings |
||||
* gpio0 = button, gpio1 = led green, gpio2 = led red |
||||
* verify = n ... disable kernel checksum verification for faster booting |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"tftpdir=calimero\0" \
|
||||
"flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
|
||||
"erase 0x60800000 +0x400000; " \
|
||||
"cp.b $loadaddr 0x60800000 $filesize\0" \
|
||||
"flashrootfs=" \
|
||||
"tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
|
||||
"erase 0x60c00000 +0x2e00000; " \
|
||||
"cp.b $loadaddr 0x60c00000 $filesize\0" \
|
||||
"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
|
||||
"protect off all; " \
|
||||
"erase 0x60000000 +0x80000; " \
|
||||
"cp.b $loadaddr 0x60000000 $filesize\0" \
|
||||
"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
|
||||
"erase 0x60080000 +0x780000; " \
|
||||
"cp.b $loadaddr 0x60080000 $filesize\0" \
|
||||
"erase_persistent=erase 0x63a00000 +0x600000;\0" \
|
||||
"bootnor=setenv bootargs console=ttyS2,115200n8 " \
|
||||
"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
|
||||
"rootwait ethaddr=$ethaddr; " \
|
||||
"gpio c 1; gpio s 2; bootm 0x60800000\0" \
|
||||
"bootrlk=gpio s 1; gpio s 2;" \
|
||||
"setenv bootargs console=ttyS2,115200n8 " \
|
||||
"ethaddr=$ethaddr; bootm 0x60080000\0" \
|
||||
"boottftp=setenv bootargs console=ttyS2,115200n8 " \
|
||||
"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
|
||||
"rootwait ethaddr=$ethaddr; " \
|
||||
"tftpboot $loadaddr $tftpdir/uImage;" \
|
||||
"gpio c 1; gpio s 2; bootm $loadaddr\0" \
|
||||
"checkupdate=if test -n $update_flag; then " \
|
||||
"echo Previous update failed - starting RLK; " \
|
||||
"run bootrlk; fi; " \
|
||||
"if test -n $initial_setup; then " \
|
||||
"echo Running initial setup procedure; " \
|
||||
"sleep 1; run flashall; fi\0" \
|
||||
"product=accessory\0" \
|
||||
"serial=XX12345\0" \
|
||||
"checknor=" \
|
||||
"if gpio i 0; then run bootnor; fi;\0" \
|
||||
"checkrlk=" \
|
||||
"if gpio i 0; then run bootrlk; fi;\0" \
|
||||
"checkbutton=" \
|
||||
"run checknor; sleep 1;" \
|
||||
"run checknor; sleep 1;" \
|
||||
"run checknor; sleep 1;" \
|
||||
"run checknor; sleep 1;" \
|
||||
"run checknor;" \
|
||||
"gpio s 1; gpio s 2;" \
|
||||
"echo ---- Release button to boot RLK ----;" \
|
||||
"run checkrlk; sleep 1;" \
|
||||
"run checkrlk; sleep 1;" \
|
||||
"run checkrlk; sleep 1;" \
|
||||
"run checkrlk; sleep 1;" \
|
||||
"run checkrlk; sleep 1;" \
|
||||
"run checkrlk;" \
|
||||
"echo ---- Factory reset requested ----;" \
|
||||
"gpio c 1;" \
|
||||
"setenv factory_reset true;" \
|
||||
"saveenv;" \
|
||||
"run bootnor;\0" \
|
||||
"flashall=run flashrlk;" \
|
||||
"run flashkernel;" \
|
||||
"run flashrootfs;" \
|
||||
"setenv erase_datafs true;" \
|
||||
"setenv initial_setup;" \
|
||||
"saveenv;" \
|
||||
"run bootnor;\0" \
|
||||
"verify=n\0" \
|
||||
"clearenv=protect off all;" \
|
||||
"erase 0x60040000 +0x40000;\0" \
|
||||
"bootlimit=3\0" \
|
||||
"altbootcmd=run bootrlk\0" |
||||
|
||||
#define CONFIG_PREBOOT \ |
||||
"echo Version: $ver; " \
|
||||
"echo Serial: $serial; " \
|
||||
"echo MAC: $ethaddr; " \
|
||||
"echo Product: $product; " \
|
||||
"gpio c 1; gpio c 2;" |
||||
|
||||
/*
|
||||
* U-Boot commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_GPIO |
||||
|
||||
#ifndef CONFIG_DRIVER_TI_EMAC |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_DHCP |
||||
#undef CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_PING |
||||
#endif |
||||
|
||||
/* additions for new relocation code, must added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
||||
/* initial stack pointer in internal SRAM */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
int calimain_get_osc_freq(void); |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue