Matthias Fuchs
9 years ago
committed by
Tom Rini
parent
3705726010
commit
9a4018e09a
@ -1,12 +0,0 @@ |
||||
if TARGET_DP405 |
||||
|
||||
config SYS_BOARD |
||||
default "dp405" |
||||
|
||||
config SYS_VENDOR |
||||
default "esd" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "DP405" |
||||
|
||||
endif |
||||
@ -1,6 +0,0 @@ |
||||
DP405 BOARD |
||||
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
||||
S: Maintained |
||||
F: board/esd/dp405/ |
||||
F: include/configs/DP405.h |
||||
F: configs/DP405_defconfig |
||||
@ -1,13 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# Objects for Xilinx JTAG programming (CPLD)
|
||||
CPLD = ../common/xilinx_jtag/lenval.o \
|
||||
../common/xilinx_jtag/micro.o \
|
||||
../common/xilinx_jtag/ports.o
|
||||
|
||||
obj-y = dp405.o flash.o ../common/misc.o $(CPLD)
|
||||
@ -1,112 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <command.h> |
||||
#include <malloc.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
/*
|
||||
* IRQ 0-15 405GP internally generated; active high; level sensitive |
||||
* IRQ 16 405GP internally generated; active low; level sensitive |
||||
* IRQ 17-24 RESERVED |
||||
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
||||
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
||||
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
||||
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
||||
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
||||
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
||||
*/ |
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
||||
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ |
||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
||||
*/ |
||||
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
||||
|
||||
/*
|
||||
* Reset CPLD via GPIO13 (CS4) pin |
||||
*/ |
||||
out_be32((void *)GPIO0_OR, |
||||
in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13)); |
||||
udelay(1000); /* wait 1ms */ |
||||
out_be32((void *)GPIO0_OR, |
||||
in_be32((void *)GPIO0_OR) | (0x80000000 >> 13)); |
||||
udelay(1000); /* wait 1ms */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
/* adjust flash start and offset */ |
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
||||
gd->bd->bi_flashoffset = 0; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char str[64]; |
||||
int i = getenv_f("serial#", str, sizeof(str)); |
||||
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, |
||||
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; |
||||
unsigned char id1, id2, rev; |
||||
|
||||
puts ("Board: "); |
||||
|
||||
if (i == -1) |
||||
puts ("### No HW ID - assuming DP405"); |
||||
else |
||||
puts(str); |
||||
|
||||
id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f]; |
||||
id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f]; |
||||
|
||||
rev = in_8((void *)0xf0001000); |
||||
if (rev & 0x10) /* old DP405 compatibility */ |
||||
rev = in_8((void *)0xf0000800); |
||||
|
||||
switch (rev & 0xc0) { |
||||
case 0x00: |
||||
puts(" (HW=DP405"); |
||||
break; |
||||
case 0x80: |
||||
puts(" (HW=DP405/CO"); |
||||
break; |
||||
case 0xc0: |
||||
puts(" (HW=DN405"); |
||||
break; |
||||
} |
||||
printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f); |
||||
|
||||
if ((rev & 0xc0) == 0xc0) { |
||||
printf(", C5V=%s", |
||||
in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on"); |
||||
} |
||||
puts(")\n"); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,85 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
/*
|
||||
* include common flash code (for esd boards) |
||||
*/ |
||||
#include "../common/flash.c" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size_b0; |
||||
int i; |
||||
uint pbcr; |
||||
unsigned long base_b0; |
||||
int size_val = 0; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0<<20); |
||||
} |
||||
|
||||
/* Setup offsets */ |
||||
flash_get_offsets (-size_b0, &flash_info[0]); |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
mtdcr(EBC0_CFGADDR, PB0CR); |
||||
pbcr = mfdcr(EBC0_CFGDATA); |
||||
mtdcr(EBC0_CFGADDR, PB0CR); |
||||
base_b0 = -size_b0; |
||||
switch (size_b0) { |
||||
case 1 << 20: |
||||
size_val = 0; |
||||
break; |
||||
case 2 << 20: |
||||
size_val = 1; |
||||
break; |
||||
case 4 << 20: |
||||
size_val = 2; |
||||
break; |
||||
case 8 << 20: |
||||
size_val = 3; |
||||
break; |
||||
case 16 << 20: |
||||
size_val = 4; |
||||
break; |
||||
} |
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); |
||||
mtdcr(EBC0_CFGDATA, pbcr); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
-CONFIG_SYS_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
|
||||
flash_info[0].size = size_b0; |
||||
|
||||
return (size_b0); |
||||
} |
||||
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_4xx=y |
||||
CONFIG_TARGET_DP405=y |
||||
@ -1,246 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_DP405 1 /* ...on a DP405 board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#undef CONFIG_BOOTCOMMAND |
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_BSP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_EEPROM |
||||
|
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_NFS |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
|
||||
#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock() |
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
||||
#define CONFIG_SYS_BASE_BAUD 691200 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 } |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) |
||||
# define CONFIG_SYS_RAMBOOT 1 |
||||
#else |
||||
# undef CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
||||
#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
||||
/* total size of a CAT24WC16 is 2048 bytes */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_PPC4XX |
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
#define CAN_BA 0xF0000000 /* CAN Base Address */ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
||||
#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
||||
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff |
||||
*/ |
||||
/* FPGA program pin configuration */ |
||||
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
||||
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific) |
||||
* |
||||
* GPIO0[0] - External Bus Controller BLAST output |
||||
* GPIO0[1-9] - Instruction trace outputs -> GPIO |
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||
* GPIO0[28-29] - UART1 data signal input/output |
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
||||
*/ |
||||
/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
||||
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ |
||||
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ |
||||
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
||||
#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ |
||||
|
||||
/*
|
||||
* Default speed selection (cpu_plb_opb_ebc) in mhz. |
||||
* This value will be set if iic boot eprom is disabled. |
||||
*/ |
||||
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue