From 9b219d4dfb1f358fa0dfa03f6e529c82f9299dd2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 27 Mar 2015 01:31:44 +0100 Subject: [PATCH] tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach Signed-off-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra20/funcmux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a07..44a85c5 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE);