This patch adds the core support for Freescale mx31 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>master
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).a
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COBJS = interrupts.o serial.o generic.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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/*
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* (C) Copyright 2007 |
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* Sascha Hauer, Pengutronix |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/mx31-regs.h> |
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static u32 mx31_decode_pll(u32 reg, u32 infreq) |
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{ |
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u32 mfi = (reg >> 10) & 0xf; |
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u32 mfn = reg & 0x3f; |
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u32 mfd = (reg >> 16) & 0x3f; |
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u32 pd = (reg >> 26) & 0xf; |
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mfi = mfi <= 5 ? 5 : mfi; |
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mfd += 1; |
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pd += 1; |
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return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / |
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(mfd * pd)) << 10; |
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} |
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u32 mx31_get_mpl_dpdgck_clk(void) |
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{ |
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u32 infreq; |
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if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) |
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infreq = CONFIG_MX31_CLK32 * 1024; |
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else |
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infreq = CONFIG_MX31_HCLK_FREQ; |
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return mx31_decode_pll(__REG(CCM_MPCTL), infreq); |
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} |
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u32 mx31_get_mcu_main_clk(void) |
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{ |
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/* For now we assume mpl_dpdgck_clk == mcu_main_clk
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* which should be correct for most boards |
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*/ |
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return mx31_get_mpl_dpdgck_clk(); |
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} |
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u32 mx31_get_ipg_clk(void) |
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{ |
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u32 freq = mx31_get_mcu_main_clk(); |
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u32 pdr0 = __REG(CCM_PDR0); |
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freq /= ((pdr0 >> 3) & 0x7) + 1; |
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freq /= ((pdr0 >> 6) & 0x3) + 1; |
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return freq; |
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} |
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void mx31_dump_clocks(void) |
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{ |
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u32 cpufreq = mx31_get_mcu_main_clk(); |
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printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); |
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printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); |
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} |
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void mx31_gpio_mux(unsigned long mode) |
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{ |
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unsigned long reg, shift, tmp; |
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reg = IOMUXC_BASE + (mode & 0xfc); |
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shift = (~mode & 0x3) * 8; |
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tmp = __REG(reg); |
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tmp &= ~(0xff << shift); |
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tmp |= ((mode >> 8) & 0xff) << shift; |
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__REG(reg) = tmp; |
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} |
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#if defined(CONFIG_DISPLAY_CPUINFO) |
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int print_cpuinfo (void) |
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{ |
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printf("CPU: Freescale i.MX31 at %d MHz\n", |
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mx31_get_mcu_main_clk() / 1000000); |
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return 0; |
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} |
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#endif |
@ -0,0 +1,102 @@ |
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/*
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* (C) Copyright 2007 |
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* Sascha Hauer, Pengutronix |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/mx31-regs.h> |
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#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ |
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/* General purpose timers registers */ |
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#define GPTCR __REG(TIMER_BASE) /* Control register */ |
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#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ |
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#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ |
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#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ |
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/* General purpose timers bitfields */ |
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#define GPTCR_SWR (1<<15) /* Software reset */ |
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#define GPTCR_FRR (1<<9) /* Freerun / restart */ |
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#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ |
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#define GPTCR_TEN (1) /* Timer enable */ |
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/* nothing really to do with interrupts, just starts up a counter. */ |
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int interrupt_init (void) |
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{ |
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int i; |
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/* setup GP Timer 1 */ |
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GPTCR = GPTCR_SWR; |
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for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ |
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GPTPR = 0; /* 32Khz */ |
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GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ |
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return 0; |
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} |
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void reset_timer_masked (void) |
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{ |
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GPTCR = 0; |
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GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ |
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} |
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ulong get_timer_masked (void) |
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{ |
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ulong val = GPTCNT; |
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return val; |
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} |
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ulong get_timer (ulong base) |
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{ |
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return get_timer_masked () - base; |
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} |
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void set_timer (ulong t) |
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{ |
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} |
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/* delay x useconds AND perserve advance timstamp value */ |
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void udelay (unsigned long usec) |
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{ |
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ulong tmo, tmp; |
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if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ |
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tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ |
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tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ |
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tmo /= 1000; /* finish normalize. */ |
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} else { /* else small number, don't kill it prior to HZ multiply */ |
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tmo = usec * CFG_HZ; |
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tmo /= (1000*1000); |
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} |
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tmp = get_timer (0); /* get current timestamp */ |
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if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ |
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reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ |
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else |
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tmo += tmp; /* else, set advancing stamp wake up time */ |
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while (get_timer_masked () < tmo)/* loop till event */ |
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/*NOP*/; |
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} |
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void reset_cpu (ulong addr) |
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{ |
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__REG16(WDOG_BASE) = 4; |
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} |
@ -0,0 +1,231 @@ |
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/*
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* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#if defined CONFIG_MX31_UART |
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#include <asm/arch/mx31.h> |
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#define __REG(x) (*((volatile u32 *)(x))) |
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#ifdef CFG_MX31_UART1 |
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#define UART_PHYS 0x43f90000 |
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#elif defined(CFG_MX31_UART2) |
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#define UART_PHYS 0x43f94000 |
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#elif defined(CFG_MX31_UART3) |
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#define UART_PHYS 0x5000c000 |
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#elif defined(CFG_MX31_UART4) |
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#define UART_PHYS 0x43fb0000 |
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#elif defined(CFG_MX31_UART5) |
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#define UART_PHYS 0x43fb4000 |
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#else |
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#error "define CFG_MX31_UARTx to use the mx31 UART driver" |
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#endif |
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/* Register definitions */ |
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#define URXD 0x0 /* Receiver Register */ |
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#define UTXD 0x40 /* Transmitter Register */ |
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#define UCR1 0x80 /* Control Register 1 */ |
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#define UCR2 0x84 /* Control Register 2 */ |
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#define UCR3 0x88 /* Control Register 3 */ |
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#define UCR4 0x8c /* Control Register 4 */ |
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#define UFCR 0x90 /* FIFO Control Register */ |
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#define USR1 0x94 /* Status Register 1 */ |
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#define USR2 0x98 /* Status Register 2 */ |
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#define UESC 0x9c /* Escape Character Register */ |
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#define UTIM 0xa0 /* Escape Timer Register */ |
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#define UBIR 0xa4 /* BRM Incremental Register */ |
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#define UBMR 0xa8 /* BRM Modulator Register */ |
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#define UBRC 0xac /* Baud Rate Count Register */ |
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#define UTS 0xb4 /* UART Test Register (mx31) */ |
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/* UART Control Register Bit Fields.*/ |
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#define URXD_CHARRDY (1<<15) |
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#define URXD_ERR (1<<14) |
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#define URXD_OVRRUN (1<<13) |
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#define URXD_FRMERR (1<<12) |
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#define URXD_BRK (1<<11) |
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#define URXD_PRERR (1<<10) |
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#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ |
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ |
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ |
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ |
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ |
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ |
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#define UCR1_IREN (1<<7) /* Infrared interface enable */ |
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ |
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
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#define UCR1_SNDBRK (1<<4) /* Send break */ |
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
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#define UCR1_DOZE (1<<1) /* Doze */ |
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#define UCR1_UARTEN (1<<0) /* UART enabled */ |
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ |
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#define UCR2_CTSC (1<<13) /* CTS pin control */ |
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#define UCR2_CTS (1<<12) /* Clear to send */ |
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#define UCR2_ESCEN (1<<11) /* Escape enable */ |
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#define UCR2_PREN (1<<8) /* Parity enable */ |
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#define UCR2_PROE (1<<7) /* Parity odd/even */ |
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#define UCR2_STPB (1<<6) /* Stop */ |
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#define UCR2_WS (1<<5) /* Word size */ |
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ |
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */ |
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#define UCR2_RXEN (1<<1) /* Receiver enabled */ |
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#define UCR2_SRST (1<<0) /* SW reset */ |
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ |
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#define UCR3_PARERREN (1<<12) /* Parity enable */ |
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ |
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#define UCR3_DSR (1<<10) /* Data set ready */ |
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#define UCR3_DCD (1<<9) /* Data carrier detect */ |
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#define UCR3_RI (1<<8) /* Ring indicator */ |
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ |
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ |
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ |
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
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#define UCR3_BPEN (1<<0) /* Preset registers enable */ |
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ |
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ |
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ |
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#define UCR4_IRSC (1<<5) /* IR special case */ |
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ |
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ |
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ |
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ |
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ |
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ |
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#define USR1_RTSS (1<<14) /* RTS pin status */ |
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ |
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#define USR1_RTSD (1<<12) /* RTS delta */ |
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ |
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ |
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ |
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ |
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ |
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ |
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#define USR2_IDLE (1<<12) /* Idle condition */ |
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ |
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#define USR2_WAKE (1<<7) /* Wake */ |
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ |
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#define USR2_TXDC (1<<3) /* Transmitter complete */ |
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#define USR2_BRCD (1<<2) /* Break condition */ |
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#define USR2_ORE (1<<1) /* Overrun error */ |
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#define USR2_RDR (1<<0) /* Recv data ready */ |
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#define UTS_FRCPERR (1<<13) /* Force parity error */ |
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#define UTS_LOOP (1<<12) /* Loop tx and rx */ |
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ |
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ |
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#define UTS_TXFULL (1<<4) /* TxFIFO full */ |
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#define UTS_RXFULL (1<<3) /* RxFIFO full */ |
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#define UTS_SOFTRST (1<<0) /* Software reset */ |
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DECLARE_GLOBAL_DATA_PTR; |
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void serial_setbrg (void) |
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{ |
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u32 clk = mx31_get_ipg_clk(); |
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if (!gd->baudrate) |
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gd->baudrate = CONFIG_BAUDRATE; |
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__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ |
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__REG(UART_PHYS + UBIR) = 0xf; |
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__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); |
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} |
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int serial_getc (void) |
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{ |
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while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); |
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return __REG(UART_PHYS + URXD); |
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} |
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void serial_putc (const char c) |
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{ |
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__REG(UART_PHYS + UTXD) = c; |
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/* wait for transmitter to be ready */ |
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while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); |
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/* If \n, also do \r */ |
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if (c == '\n') |
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serial_putc ('\r'); |
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} |
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/*
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* Test whether a character is in the RX buffer |
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*/ |
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int serial_tstc (void) |
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{ |
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/* If receive fifo is empty, return false */ |
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if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) |
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return 0; |
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return 1; |
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} |
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void |
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serial_puts (const char *s) |
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{ |
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while (*s) { |
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serial_putc (*s++); |
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} |
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} |
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/*
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* Initialise the serial port with the given baudrate. The settings |
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* are always 8 data bits, no parity, 1 stop bit, no start bits. |
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* |
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*/ |
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int serial_init (void) |
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{ |
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__REG(UART_PHYS + UCR1) = 0x0; |
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__REG(UART_PHYS + UCR2) = 0x0; |
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while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); |
||||
|
||||
__REG(UART_PHYS + UCR3) = 0x0704; |
||||
__REG(UART_PHYS + UCR4) = 0x8000; |
||||
__REG(UART_PHYS + UESC) = 0x002b; |
||||
__REG(UART_PHYS + UTIM) = 0x0; |
||||
|
||||
__REG(UART_PHYS + UTS) = 0x0; |
||||
|
||||
serial_setbrg(); |
||||
|
||||
__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; |
||||
|
||||
__REG(UART_PHYS + UCR1) = UCR1_UARTEN; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
#endif /* CONFIG_MX31 */ |
@ -0,0 +1,137 @@ |
||||
/*
|
||||
* |
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MX31_REGS_H |
||||
#define __ASM_ARCH_MX31_REGS_H |
||||
|
||||
#define __REG(x) (*((volatile u32 *)(x))) |
||||
#define __REG16(x) (*((volatile u16 *)(x))) |
||||
#define __REG8(x) (*((volatile u8 *)(x))) |
||||
|
||||
#define CCM_BASE 0x53f80000 |
||||
#define CCM_CCMR (CCM_BASE + 0x00) |
||||
#define CCM_PDR0 (CCM_BASE + 0x04) |
||||
#define CCM_PDR1 (CCM_BASE + 0x08) |
||||
#define CCM_RCSR (CCM_BASE + 0x0c) |
||||
#define CCM_MPCTL (CCM_BASE + 0x10) |
||||
#define CCM_UPCTL (CCM_BASE + 0x10) |
||||
#define CCM_SPCTL (CCM_BASE + 0x18) |
||||
#define CCM_COSR (CCM_BASE + 0x1C) |
||||
|
||||
#define CCMR_MDS (1 << 7) |
||||
#define CCMR_SBYCS (1 << 4) |
||||
#define CCMR_MPE (1 << 3) |
||||
#define CCMR_PRCS_MASK (3 << 1) |
||||
#define CCMR_FPM (1 << 1) |
||||
#define CCMR_CKIH (2 << 1) |
||||
|
||||
#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) |
||||
#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) |
||||
#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) |
||||
#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) |
||||
#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) |
||||
#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) |
||||
#define PDR0_MCU_PODF(x) ((x) & 0x7) |
||||
|
||||
#define PLL_PD(x) (((x) & 0xf) << 26) |
||||
#define PLL_MFD(x) (((x) & 0x3ff) << 16) |
||||
#define PLL_MFI(x) (((x) & 0xf) << 10) |
||||
#define PLL_MFN(x) (((x) & 0x3ff) << 0) |
||||
|
||||
#define WEIM_BASE 0xb8002000 |
||||
#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) |
||||
#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) |
||||
#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) |
||||
|
||||
#define IOMUXC_BASE 0x43FAC000 |
||||
#define IOMUXC_GPR (IOMUXC_BASE + 0x8) |
||||
#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) |
||||
#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) |
||||
|
||||
#define IPU_BASE 0x53fc0000 |
||||
#define IPU_CONF IPU_BASE |
||||
|
||||
#define IPU_CONF_PXL_ENDIAN (1<<8) |
||||
#define IPU_CONF_DU_EN (1<<7) |
||||
#define IPU_CONF_DI_EN (1<<6) |
||||
#define IPU_CONF_ADC_EN (1<<5) |
||||
#define IPU_CONF_SDC_EN (1<<4) |
||||
#define IPU_CONF_PF_EN (1<<3) |
||||
#define IPU_CONF_ROT_EN (1<<2) |
||||
#define IPU_CONF_IC_EN (1<<1) |
||||
#define IPU_CONF_SCI_EN (1<<0) |
||||
|
||||
#define WDOG_BASE 0x53FDC000 |
||||
|
||||
/*
|
||||
* Signal Multiplexing (IOMUX) |
||||
*/ |
||||
|
||||
/* bits in the SW_MUX_CTL registers */ |
||||
#define MUX_CTL_OUT_GPIO_DR (0 << 4) |
||||
#define MUX_CTL_OUT_FUNC (1 << 4) |
||||
#define MUX_CTL_OUT_ALT1 (2 << 4) |
||||
#define MUX_CTL_OUT_ALT2 (3 << 4) |
||||
#define MUX_CTL_OUT_ALT3 (4 << 4) |
||||
#define MUX_CTL_OUT_ALT4 (5 << 4) |
||||
#define MUX_CTL_OUT_ALT5 (6 << 4) |
||||
#define MUX_CTL_OUT_ALT6 (7 << 4) |
||||
#define MUX_CTL_IN_NONE (0 << 0) |
||||
#define MUX_CTL_IN_GPIO (1 << 0) |
||||
#define MUX_CTL_IN_FUNC (2 << 0) |
||||
#define MUX_CTL_IN_ALT1 (4 << 0) |
||||
#define MUX_CTL_IN_ALT2 (8 << 0) |
||||
|
||||
#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) |
||||
#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) |
||||
#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) |
||||
#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) |
||||
|
||||
/* Register offsets based on IOMUXC_BASE */ |
||||
/* 0x00 .. 0x7b */ |
||||
#define MUX_CTL_RTS1 0x7c |
||||
#define MUX_CTL_CTS1 0x7d |
||||
#define MUX_CTL_DTR_DCE1 0x7e |
||||
#define MUX_CTL_DSR_DCE1 0x7f |
||||
#define MUX_CTL_CSPI2_SCLK 0x80 |
||||
#define MUX_CTL_CSPI2_SPI_RDY 0x81 |
||||
#define MUX_CTL_RXD1 0x82 |
||||
#define MUX_CTL_TXD1 0x83 |
||||
#define MUX_CTL_CSPI2_MISO 0x84 |
||||
/* 0x85 .. 0x8a */ |
||||
#define MUX_CTL_CSPI2_MOSI 0x8b |
||||
|
||||
/* The modes a specific pin can be in
|
||||
* these macros can be used in mx31_gpio_mux() and have the form |
||||
* MUX_[contact name]__[pin function] |
||||
*/ |
||||
#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) |
||||
#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) |
||||
#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) |
||||
#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) |
||||
|
||||
#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) |
||||
#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) |
||||
|
||||
|
||||
#endif /* __ASM_ARCH_MX31_REGS_H */ |
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* |
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MX31_H |
||||
#define __ASM_ARCH_MX31_H |
||||
|
||||
u32 mx31_get_mpl_dpdgck_clk(void); |
||||
u32 mx31_get_mcu_main_clk(void); |
||||
u32 mx31_get_ipg_clk(void); |
||||
void mx31_gpio_mux(unsigned long mode); |
||||
|
||||
#endif /* __ASM_ARCH_MX31_H */ |
Loading…
Reference in new issue