Stefano Babic
10 years ago
commit
9b5b60a05c
@ -0,0 +1,128 @@ |
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/* |
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* Copyright (C) 2013 Samsung Electronics |
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* Akshay Saraswat <akshay.s@samsung.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <asm/arch/cpu.h> |
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.globl relocate_wait_code
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relocate_wait_code: |
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adr r0, code_base @ r0: source address (start)
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adr r1, code_end @ r1: source address (end)
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ldr r2, =0x02073000 @ r2: target address
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1: |
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ldmia r0!, {r3-r6} |
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stmia r2!, {r3-r6} |
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cmp r0, r1 |
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blt 1b |
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b code_end |
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.ltorg |
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/* |
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* Secondary core waits here until Primary wake it up. |
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* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. |
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* This is a workaround code which is supposed to act as a |
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* substitute/supplement to the iROM code. |
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* |
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* This workaround code is relocated to the address 0x02073000 |
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* because that comes out to be the last 4KB of the iRAM |
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* (Base Address - 0x02020000, Limit Address - 0x020740000). |
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* |
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* U-boot and kernel are aware of this code and flags by the simple |
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* fact that we are implementing a workaround in the last 4KB |
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* of the iRAM and we have already defined these flag and address |
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* values in both kernel and U-boot for our use. |
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*/ |
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code_base: |
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b 1f |
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/* |
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* These addresses are being used as flags in u-boot and kernel. |
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* |
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* Jump address for resume and flag to check for resume/reset: |
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* Resume address - 0x2073008 |
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* Resume flag - 0x207300C |
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* |
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* Jump address for cluster switching: |
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* Switch address - 0x2073018 |
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* |
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* Jump address for core hotplug: |
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* Hotplug address - 0x207301C |
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* |
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* Jump address for C2 state (Reserved for future not being used right now): |
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* C2 address - 0x2073024 |
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* |
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* Managed per core status for the active cluster: |
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* CPU0 state - 0x2073028 |
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* CPU1 state - 0x207302C |
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* CPU2 state - 0x2073030 |
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* CPU3 state - 0x2073034 |
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* |
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* Managed per core GIC status for the active cluster: |
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* CPU0 gic state - 0x2073038 |
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* CPU1 gic state - 0x207303C |
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* CPU2 gic state - 0x2073040 |
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* CPU3 gic state - 0x2073044 |
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* |
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* Logic of the code: |
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* Step-1: Read current CPU status. |
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* Step-2: If it's a resume then continue, else jump to step 4. |
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* Step-3: Clear inform1 PMU register and jump to inform0 value. |
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* Step-4: If it's a switch, C2 or reset, get the hotplug address. |
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* Step-5: If address is not available, enter WFE. |
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* Step-6: If address is available, jump to that address. |
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*/ |
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nop @ for backward compatibility
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.word 0x0 @ REG0: RESUME_ADDR
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.word 0x0 @ REG1: RESUME_FLAG
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.word 0x0 @ REG2
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.word 0x0 @ REG3
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_switch_addr: |
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.word 0x0 @ REG4: SWITCH_ADDR
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_hotplug_addr: |
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.word 0x0 @ REG5: CPU1_BOOT_REG
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.word 0x0 @ REG6
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_c2_addr: |
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.word 0x0 @ REG7: REG_C2_ADDR
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_cpu_state: |
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.word 0x1 @ CPU0_STATE : RESET
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.word 0x2 @ CPU1_STATE : SECONDARY RESET
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.word 0x2 @ CPU2_STATE : SECONDARY RESET
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.word 0x2 @ CPU3_STATE : SECONDARY RESET
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_gic_state: |
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.word 0x0 @ CPU0 - GICD_IGROUPR0
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.word 0x0 @ CPU1 - GICD_IGROUPR0
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.word 0x0 @ CPU2 - GICD_IGROUPR0
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.word 0x0 @ CPU3 - GICD_IGROUPR0
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1: |
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adr r0, _cpu_state |
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mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
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and r7, r7, #0xf @ r7 = cpu id
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/* Read the current cpu state */ |
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ldr r10, [r0, r7, lsl #2] |
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svc_entry: |
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tst r10, #(1 << 4) |
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adrne r0, _switch_addr |
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bne wait_for_addr |
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/* Clear INFORM1 */ |
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ldr r0, =(0x10040000 + 0x804) |
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ldr r1, [r0] |
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cmp r1, #0x0 |
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movne r1, #0x0 |
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strne r1, [r0] |
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/* Get INFORM0 */ |
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ldrne r1, =(0x10040000 + 0x800) |
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ldrne pc, [r1] |
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tst r10, #(1 << 0) |
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ldrne pc, =0x23e00000 |
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adr r0, _hotplug_addr |
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wait_for_addr: |
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ldr r1, [r0] |
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cmp r1, #0x0 |
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bxne r1 |
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wfe |
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b wait_for_addr |
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.ltorg |
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code_end: |
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mov pc, lr |
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File diff suppressed because it is too large
Load Diff
@ -1,28 +0,0 @@ |
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sg-regs.h> |
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void sg_init(void) |
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{ |
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u32 tmp; |
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/* Set DDR size */ |
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tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); |
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tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); |
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#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE |
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tmp |= SG_MEMCONF_SPARSEMEM; |
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#endif |
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writel(tmp, SG_MEMCONF); |
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/* Input ports must be enabled before deasserting reset of cores */ |
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tmp = readl(SG_IECTRL); |
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tmp |= 0x1; |
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writel(tmp, SG_IECTRL); |
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} |
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@ -1,29 +0,0 @@ |
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sc-regs.h> |
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void clkrst_init(void) |
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{ |
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u32 tmp; |
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/* deassert reset */ |
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tmp = readl(SC_RSTCTRL); |
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tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 |
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| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; |
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writel(tmp, SC_RSTCTRL); |
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readl(SC_RSTCTRL); /* dummy read */ |
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/* privide clocks */ |
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tmp = readl(SC_CLKCTRL); |
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tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC |
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| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; |
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writel(tmp, SC_CLKCTRL); |
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readl(SC_CLKCTRL); /* dummy read */ |
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} |
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@ -1,75 +0,0 @@ |
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sbc-regs.h> |
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#include <asm/arch/sg-regs.h> |
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void sbc_init(void) |
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{ |
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#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) |
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/*
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* Only CS1 is connected to support card. |
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* BKSZ[1:0] should be set to "01". |
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*/ |
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); |
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); |
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); |
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); |
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if (boot_is_swapped()) { |
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/*
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* Boot Swap On: boot from external NOR/SRAM |
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* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. |
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* |
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* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank |
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* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals |
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*/ |
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writel(0x0000bc01, SBBASE0); |
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} else { |
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/*
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* Boot Swap Off: boot from mask ROM |
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* 0x00000000-0x01ffffff: mask ROM |
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* 0x02000000-0x3effffff: memory bank (31MB) |
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* 0x03f00000-0x3fffffff: peripherals (1MB) |
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*/ |
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writel(0x0000be01, SBBASE0); /* dummy */ |
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writel(0x0200be01, SBBASE1); |
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} |
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#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) |
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#if !defined(CONFIG_SPL_BUILD) |
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/* XECS0: boot/sub memory (boot swap = off/on) */ |
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); |
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); |
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); |
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); |
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#endif |
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/* XECS1: sub/boot memory (boot swap = off/on) */ |
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
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/* XECS3: peripherals */ |
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); |
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); |
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); |
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); |
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writel(0x0000bc01, SBBASE0); /* boot memory */ |
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writel(0x0400bc01, SBBASE1); /* sub memory */ |
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writel(0x0800bf01, SBBASE3); /* peripherals */ |
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#if !defined(CONFIG_SPL_BUILD) |
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sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ |
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#endif |
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sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ |
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writel(0x00000001, SG_LOADPINCTRL); |
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#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ |
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} |
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@ -1,28 +0,0 @@ |
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sg-regs.h> |
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void sg_init(void) |
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{ |
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u32 tmp; |
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/* Set DDR size */ |
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tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); |
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tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); |
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#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE |
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tmp |= SG_MEMCONF_SPARSEMEM; |
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#endif |
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writel(tmp, SG_MEMCONF); |
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/* Input ports must be enabled before deasserting reset of cores */ |
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tmp = readl(SG_IECTRL); |
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tmp |= 1 << 6; |
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writel(tmp, SG_IECTRL); |
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} |
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@ -1,29 +0,0 @@ |
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sc-regs.h> |
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void clkrst_init(void) |
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{ |
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u32 tmp; |
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/* deassert reset */ |
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tmp = readl(SC_RSTCTRL); |
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tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 |
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| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; |
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writel(tmp, SC_RSTCTRL); |
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readl(SC_RSTCTRL); /* dummy read */ |
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/* privide clocks */ |
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tmp = readl(SC_CLKCTRL); |
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tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC |
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| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; |
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writel(tmp, SC_CLKCTRL); |
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readl(SC_CLKCTRL); /* dummy read */ |
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} |
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@ -0,0 +1,9 @@ |
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#
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# (C) Copyright 2014 - 2015 Xilinx, Inc.
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# Michal Simek <michal.simek@xilinx.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clk.o
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obj-y += cpu.o
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@ -0,0 +1,49 @@ |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned long get_uart_clk(int dev_id) |
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{ |
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u32 ver = zynqmp_get_silicon_version(); |
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switch (ver) { |
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case ZYNQMP_CSU_VERSION_EP108: |
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return 25000000; |
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} |
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return 133000000; |
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} |
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#ifdef CONFIG_CLOCKS |
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/**
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* set_cpu_clk_info() - Initialize clock framework |
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* Always returns zero. |
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* |
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* This function is called from common code after relocation and sets up the |
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* clock framework. The framework must not be used before this function had been |
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* called. |
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*/ |
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int set_cpu_clk_info(void) |
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{ |
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gd->cpu_clk = get_tbclk(); |
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/* Support Veloce to show at least 1MHz via bdi */ |
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if (gd->cpu_clk > 1000000) |
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; |
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else |
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gd->bd->bi_arm_freq = 1; |
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gd->bd->bi_dsp_freq = 0; |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,28 @@ |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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#define ZYNQ_SILICON_VER_MASK 0xF000 |
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#define ZYNQ_SILICON_VER_SHIFT 12 |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned int zynqmp_get_silicon_version(void) |
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{ |
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gd->cpu_clk = get_tbclk(); |
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switch (gd->cpu_clk) { |
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case 50000000: |
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return ZYNQMP_CSU_VERSION_QEMU; |
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} |
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return ZYNQMP_CSU_VERSION_EP108; |
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} |
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@ -1,33 +0,0 @@ |
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/*
|
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* Copyright (C) 2014 Panasonic Corporation |
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef __PLAT_UNIPHIER_EHCI_H |
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#define __PLAT_UNIPHIER_EHCI_H |
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#include <linux/types.h> |
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#include <asm/io.h> |
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#include "mio-regs.h" |
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|
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struct uniphier_ehci_platform_data { |
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unsigned long base; |
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}; |
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|
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extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[]; |
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|
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static inline void uniphier_ehci_reset(int index, int on) |
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{ |
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u32 tmp; |
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|
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tmp = readl(MIO_USB_RSTCTRL(index)); |
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if (on) |
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tmp &= ~MIO_USB_RSTCTRL_XRST; |
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else |
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tmp |= MIO_USB_RSTCTRL_XRST; |
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writel(tmp, MIO_USB_RSTCTRL(index)); |
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} |
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|
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#endif /* __PLAT_UNIPHIER_EHCI_H */ |
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@ -0,0 +1,13 @@ |
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/*
|
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _ASM_ARCH_CLK_H_ |
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#define _ASM_ARCH_CLK_H_ |
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|
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unsigned long get_uart_clk(int dev_id); |
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|
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#endif /* _ASM_ARCH_CLK_H_ */ |
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@ -0,0 +1,52 @@ |
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/*
|
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _ASM_ARCH_HARDWARE_H |
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#define _ASM_ARCH_HARDWARE_H |
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|
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#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 |
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#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 |
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|
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#define ZYNQ_SDHCI_BASEADDR0 0xFF160000 |
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#define ZYNQ_SDHCI_BASEADDR1 0xFF170000 |
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|
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#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 |
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#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 |
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|
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struct crlapb_regs { |
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u32 reserved0[74]; |
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u32 timestamp_ref_ctrl; /* 0x128 */ |
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u32 reserved0_1[53]; |
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u32 boot_mode; /* 0x200 */ |
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u32 reserved1[26]; |
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}; |
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|
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) |
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|
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#define ZYNQMP_IOU_SCNTR 0xFF250000 |
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 |
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 |
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|
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struct iou_scntr { |
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u32 counter_control_register; |
||||
u32 reserved0[7]; |
||||
u32 base_frequency_id_register; |
||||
}; |
||||
|
||||
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) |
||||
|
||||
/* Bootmode setting values */ |
||||
#define BOOT_MODES_MASK 0x0000000F |
||||
#define SD_MODE 0x00000005 |
||||
#define JTAG_MODE 0x00000000 |
||||
|
||||
/* Board version value */ |
||||
#define ZYNQMP_CSU_VERSION_SILICON 0x0 |
||||
#define ZYNQMP_CSU_VERSION_EP108 0x1 |
||||
#define ZYNQMP_CSU_VERSION_QEMU 0x3 |
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */ |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* (C) Copyright 2014 - 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_SYS_PROTO_H |
||||
#define _ASM_ARCH_SYS_PROTO_H |
||||
|
||||
int zynq_sdhci_init(unsigned long regbase); |
||||
|
||||
unsigned int zynqmp_get_silicon_version(void); |
||||
|
||||
#endif /* _ASM_ARCH_SYS_PROTO_H */ |
||||
@ -0,0 +1,104 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/sizes.h> |
||||
#include <asm/io.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
static inline u32 sg_memconf_val_ch0(unsigned long size, int num) |
||||
{ |
||||
int size_mb = size / num; |
||||
u32 ret; |
||||
|
||||
switch (size_mb) { |
||||
case SZ_64M: |
||||
ret = SG_MEMCONF_CH0_SZ_64M; |
||||
break; |
||||
case SZ_128M: |
||||
ret = SG_MEMCONF_CH0_SZ_128M; |
||||
break; |
||||
case SZ_256M: |
||||
ret = SG_MEMCONF_CH0_SZ_256M; |
||||
break; |
||||
case SZ_512M: |
||||
ret = SG_MEMCONF_CH0_SZ_512M; |
||||
break; |
||||
case SZ_1G: |
||||
ret = SG_MEMCONF_CH0_SZ_1G; |
||||
break; |
||||
default: |
||||
BUG(); |
||||
break; |
||||
} |
||||
|
||||
switch (num) { |
||||
case 1: |
||||
ret |= SG_MEMCONF_CH0_NUM_1; |
||||
break; |
||||
case 2: |
||||
ret |= SG_MEMCONF_CH0_NUM_2; |
||||
break; |
||||
default: |
||||
BUG(); |
||||
break; |
||||
} |
||||
return ret; |
||||
} |
||||
|
||||
static inline u32 sg_memconf_val_ch1(unsigned long size, int num) |
||||
{ |
||||
int size_mb = size / num; |
||||
u32 ret; |
||||
|
||||
switch (size_mb) { |
||||
case SZ_64M: |
||||
ret = SG_MEMCONF_CH1_SZ_64M; |
||||
break; |
||||
case SZ_128M: |
||||
ret = SG_MEMCONF_CH1_SZ_128M; |
||||
break; |
||||
case SZ_256M: |
||||
ret = SG_MEMCONF_CH1_SZ_256M; |
||||
break; |
||||
case SZ_512M: |
||||
ret = SG_MEMCONF_CH1_SZ_512M; |
||||
break; |
||||
case SZ_1G: |
||||
ret = SG_MEMCONF_CH1_SZ_1G; |
||||
break; |
||||
default: |
||||
BUG(); |
||||
break; |
||||
} |
||||
|
||||
switch (num) { |
||||
case 1: |
||||
ret |= SG_MEMCONF_CH1_NUM_1; |
||||
break; |
||||
case 2: |
||||
ret |= SG_MEMCONF_CH1_NUM_2; |
||||
break; |
||||
default: |
||||
BUG(); |
||||
break; |
||||
} |
||||
return ret; |
||||
} |
||||
|
||||
void memconf_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* Set DDR size */ |
||||
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); |
||||
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); |
||||
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE |
||||
tmp |= SG_MEMCONF_SPARSEMEM; |
||||
#endif |
||||
writel(tmp, SG_MEMCONF); |
||||
} |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <mach/sc-regs.h> |
||||
|
||||
void clkrst_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* deassert reset */ |
||||
tmp = readl(SC_RSTCTRL); |
||||
#ifdef CONFIG_UNIPHIER_ETH |
||||
tmp |= SC_RSTCTRL_NRST_ETHER; |
||||
#endif |
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER |
||||
tmp |= SC_RSTCTRL_NRST_STDMAC; |
||||
#endif |
||||
#ifdef CONFIG_NAND_DENALI |
||||
tmp |= SC_RSTCTRL_NRST_NAND; |
||||
#endif |
||||
writel(tmp, SC_RSTCTRL); |
||||
readl(SC_RSTCTRL); /* dummy read */ |
||||
|
||||
/* privide clocks */ |
||||
tmp = readl(SC_CLKCTRL); |
||||
#ifdef CONFIG_UNIPHIER_ETH |
||||
tmp |= SC_CLKCTRL_CEN_ETHER; |
||||
#endif |
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER |
||||
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; |
||||
#endif |
||||
#ifdef CONFIG_NAND_DENALI |
||||
tmp |= SC_CLKCTRL_CEN_NAND; |
||||
#endif |
||||
writel(tmp, SC_CLKCTRL); |
||||
readl(SC_CLKCTRL); /* dummy read */ |
||||
} |
||||
@ -0,0 +1 @@ |
||||
#include "../ph1-pro4/early_clkrst_init.c" |
||||
@ -0,0 +1,50 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <mach/sbc-regs.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sbc_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* system bus output enable */ |
||||
tmp = readl(PC0CTRL); |
||||
tmp &= 0xfffffcff; |
||||
writel(tmp, PC0CTRL); |
||||
|
||||
/*
|
||||
* Only CS1 is connected to support card. |
||||
* BKSZ[1:0] should be set to "01". |
||||
*/ |
||||
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); |
||||
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); |
||||
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); |
||||
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); |
||||
|
||||
if (boot_is_swapped()) { |
||||
/*
|
||||
* Boot Swap On: boot from external NOR/SRAM |
||||
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. |
||||
* |
||||
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank |
||||
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals |
||||
*/ |
||||
writel(0x0000bc01, SBBASE0); |
||||
} else { |
||||
/*
|
||||
* Boot Swap Off: boot from mask ROM |
||||
* 0x00000000-0x01ffffff: mask ROM |
||||
* 0x02000000-0x03efffff: memory bank (31MB) |
||||
* 0x03f00000-0x03ffffff: peripherals (1MB) |
||||
*/ |
||||
writel(0x0000be01, SBBASE0); /* dummy */ |
||||
writel(0x0200be01, SBBASE1); |
||||
} |
||||
} |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sg_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* Input ports must be enabled before deasserting reset of cores */ |
||||
tmp = readl(SG_IECTRL); |
||||
tmp |= 0x1; |
||||
writel(tmp, SG_IECTRL); |
||||
} |
||||
@ -0,0 +1,57 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <mach/sc-regs.h> |
||||
|
||||
void clkrst_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* deassert reset */ |
||||
tmp = readl(SC_RSTCTRL); |
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | |
||||
SC_RSTCTRL_NRST_GIO; |
||||
#endif |
||||
#ifdef CONFIG_UNIPHIER_ETH |
||||
tmp |= SC_RSTCTRL_NRST_ETHER; |
||||
#endif |
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER |
||||
tmp |= SC_RSTCTRL_NRST_STDMAC; |
||||
#endif |
||||
#ifdef CONFIG_NAND_DENALI |
||||
tmp |= SC_RSTCTRL_NRST_NAND; |
||||
#endif |
||||
writel(tmp, SC_RSTCTRL); |
||||
readl(SC_RSTCTRL); /* dummy read */ |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
tmp = readl(SC_RSTCTRL2); |
||||
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; |
||||
writel(tmp, SC_RSTCTRL2); |
||||
readl(SC_RSTCTRL2); /* dummy read */ |
||||
#endif |
||||
|
||||
/* privide clocks */ |
||||
tmp = readl(SC_CLKCTRL); |
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | |
||||
SC_CLKCTRL_CEN_GIO; |
||||
#endif |
||||
#ifdef CONFIG_UNIPHIER_ETH |
||||
tmp |= SC_CLKCTRL_CEN_ETHER; |
||||
#endif |
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER |
||||
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; |
||||
#endif |
||||
#ifdef CONFIG_NAND_DENALI |
||||
tmp |= SC_CLKCTRL_CEN_NAND; |
||||
#endif |
||||
writel(tmp, SC_CLKCTRL); |
||||
readl(SC_CLKCTRL); /* dummy read */ |
||||
} |
||||
@ -1,29 +1,31 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2014 Panasonic Corporation |
||||
* Copyright (C) 2011-2015 Panasonic Corporation |
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/sc-regs.h> |
||||
#include <mach/sc-regs.h> |
||||
|
||||
void clkrst_init(void) |
||||
void early_clkrst_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* deassert reset */ |
||||
tmp = readl(SC_RSTCTRL); |
||||
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 |
||||
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; |
||||
|
||||
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; |
||||
if (spl_boot_device() != BOOT_DEVICE_NAND) |
||||
tmp &= ~SC_RSTCTRL_NRST_NAND; |
||||
writel(tmp, SC_RSTCTRL); |
||||
readl(SC_RSTCTRL); /* dummy read */ |
||||
|
||||
/* privide clocks */ |
||||
tmp = readl(SC_CLKCTRL); |
||||
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC |
||||
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; |
||||
tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; |
||||
writel(tmp, SC_CLKCTRL); |
||||
readl(SC_CLKCTRL); /* dummy read */ |
||||
} |
||||
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Reference in new issue