This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>master
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de> |
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* |
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* FIXME: This file contains temporary stub functions and is here |
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* only until these functions are properly merged into |
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* mainline. |
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* Copyright Altera Corporation (C) 2014-2015 |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SDRAM_H_ |
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#define _SDRAM_H_ |
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#ifndef __ASSEMBLY__ |
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unsigned long sdram_calculate_size(void); |
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unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg); |
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int sdram_calibration_full(void); |
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extern int sdram_calibration(void); |
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#define SDR_CTRLGRP_ADDRESS 0x5000 |
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struct socfpga_sdr_ctrl { |
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u32 ctrl_cfg; |
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u32 dram_timing1; |
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u32 dram_timing2; |
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u32 dram_timing3; |
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u32 dram_timing4; /* 0x10 */ |
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u32 lowpwr_timing; |
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u32 dram_odt; |
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u32 __padding0[4]; |
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u32 dram_addrw; /* 0x2c */ |
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u32 dram_if_width; /* 0x30 */ |
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u32 dram_dev_width; |
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u32 dram_sts; |
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u32 dram_intr; |
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u32 sbe_count; /* 0x40 */ |
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u32 dbe_count; |
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u32 err_addr; |
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u32 drop_count; |
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u32 drop_addr; /* 0x50 */ |
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u32 lowpwr_eq; |
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u32 lowpwr_ack; |
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u32 static_cfg; |
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u32 ctrl_width; /* 0x60 */ |
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u32 cport_width; |
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u32 cport_wmap; |
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u32 cport_rmap; |
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u32 rfifo_cmap; /* 0x70 */ |
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u32 wfifo_cmap; |
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u32 cport_rdwr; |
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u32 port_cfg; |
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u32 fpgaport_rst; /* 0x80 */ |
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u32 __padding1; |
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u32 fifo_cfg; |
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u32 protport_default; |
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u32 prot_rule_addr; /* 0x90 */ |
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u32 prot_rule_id; |
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u32 prot_rule_data; |
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u32 prot_rule_rdwr; |
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u32 __padding2[3]; |
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u32 mp_priority; /* 0xac */ |
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u32 mp_weight0; /* 0xb0 */ |
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u32 mp_weight1; |
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u32 mp_weight2; |
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u32 mp_weight3; |
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u32 mp_pacing0; /* 0xc0 */ |
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u32 mp_pacing1; |
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u32 mp_pacing2; |
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u32 mp_pacing3; |
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u32 mp_threshold0; /* 0xd0 */ |
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u32 mp_threshold1; |
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u32 mp_threshold2; |
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u32 __padding3[29]; |
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u32 phy_ctrl0; /* 0x150 */ |
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u32 phy_ctrl1; |
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u32 phy_ctrl2; |
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}; |
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struct sdram_prot_rule { |
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uint64_t sdram_start; /* SDRAM start address */ |
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uint64_t sdram_end; /* SDRAM end address */ |
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uint32_t rule; /* SDRAM protection rule number: 0-19 */ |
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int valid; /* Rule valid or not? 1 - valid, 0 not*/ |
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uint32_t security; |
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uint32_t portmask; |
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uint32_t result; |
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uint32_t lo_prot_id; |
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uint32_t hi_prot_id; |
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}; |
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#ifndef __ARCH_SDRAM_H__ |
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#define __ARCH_SDRAM_H__ |
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 |
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 |
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 |
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 |
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 |
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 |
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 |
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 |
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 |
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 |
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 |
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 |
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 |
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 |
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 |
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 |
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 |
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 |
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/* Register template: sdr::ctrlgrp::dramtiming1 */ |
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 |
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 |
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 |
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 |
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 |
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 |
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 |
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 |
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 |
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 |
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 |
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f |
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/* Register template: sdr::ctrlgrp::dramtiming2 */ |
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 |
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 |
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 |
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 |
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 |
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 |
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 |
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 |
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 |
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff |
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/* Register template: sdr::ctrlgrp::dramtiming3 */ |
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 |
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 |
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 |
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 |
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f |
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/* Register template: sdr::ctrlgrp::dramtiming4 */ |
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 |
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 |
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 |
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 |
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 |
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff |
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/* Register template: sdr::ctrlgrp::lowpwrtiming */ |
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 |
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 |
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 |
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff |
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/* Register template: sdr::ctrlgrp::dramaddrw */ |
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 |
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 |
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 |
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 |
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 |
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 |
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 |
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f |
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/* Register template: sdr::ctrlgrp::dramifwidth */ |
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 |
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff |
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/* Register template: sdr::ctrlgrp::dramdevwidth */ |
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 |
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f |
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/* Register template: sdr::ctrlgrp::dramintr */ |
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#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 |
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#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 |
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#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 |
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#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 |
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/* Register template: sdr::ctrlgrp::staticcfg */ |
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 |
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 |
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 |
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 |
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#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 |
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#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 |
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/* Register template: sdr::ctrlgrp::ctrlwidth */ |
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 |
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 |
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/* Register template: sdr::ctrlgrp::cportwidth */ |
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 |
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff |
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/* Register template: sdr::ctrlgrp::cportwmap */ |
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 |
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff |
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/* Register template: sdr::ctrlgrp::cportrmap */ |
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 |
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff |
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/* Register template: sdr::ctrlgrp::rfifocmap */ |
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 |
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff |
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/* Register template: sdr::ctrlgrp::wfifocmap */ |
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 |
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff |
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/* Register template: sdr::ctrlgrp::cportrdwr */ |
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 |
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff |
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/* Register template: sdr::ctrlgrp::portcfg */ |
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 |
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 |
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 |
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff |
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/* Register template: sdr::ctrlgrp::fifocfg */ |
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 |
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 |
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 |
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff |
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/* Register template: sdr::ctrlgrp::mppriority */ |
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 |
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff |
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff |
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff |
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff |
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 |
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff |
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ |
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff |
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ |
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff |
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ |
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff |
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ |
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 |
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff |
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
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0xffffffff |
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
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0xffffffff |
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 |
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#define \ |
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
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0x0000ffff |
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/* Register template: sdr::ctrlgrp::remappriority */ |
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 |
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff |
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ |
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(((x) << 12) & 0xfffff000) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ |
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(((x) << 10) & 0x00000c00) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ |
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(((x) << 6) & 0x000000c0) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ |
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(((x) << 8) & 0x00000100) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ |
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(((x) << 9) & 0x00000200) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ |
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(((x) << 4) & 0x00000030) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ |
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(((x) << 2) & 0x0000000c) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ |
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(((x) << 0) & 0x00000003) |
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ |
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(((x) << 12) & 0xfffff000) |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ |
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(((x) << 0) & 0x00000fff) |
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ |
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ |
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(((x) << 0) & 0x00000fff) |
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/* Register template: sdr::ctrlgrp::dramodt */ |
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#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 |
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#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 |
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#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 |
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#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f |
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/* Field instance: sdr::ctrlgrp::dramsts */ |
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#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 |
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#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 |
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/* function declaration */ |
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inline unsigned long sdram_calculate_size(void) { return 0; } |
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inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } |
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inline int sdram_calibration_full(void) { return 0; } |
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/* SDRAM width macro for configuration with ECC */ |
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#define SDRAM_WIDTH_32BIT_WITH_ECC 40 |
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#define SDRAM_WIDTH_16BIT_WITH_ECC 24 |
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#endif /* __ARCH_SDRAM_H__ */ |
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#endif |
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#endif /* _SDRAM_H_ */ |
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@ -0,0 +1,100 @@ |
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/*
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* Copyright Altera Corporation (C) 2012-2015 |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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/* This file is autogenerated from tools provided by Altera.*/ |
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#ifndef __SDRAM_CONFIG_H |
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#define __SDRAM_CONFIG_H |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 |
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 |
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 |
||||
#ifdef CONFIG_SOCFPGA_ARRIA5 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 |
||||
#else |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 |
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */ |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 |
||||
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ |
||||
0x01010101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ |
||||
0x01010101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ |
||||
0x0101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 |
||||
|
||||
#endif /*#ifndef__SDRAM_CONFIG_H*/ |
@ -0,0 +1,799 @@ |
||||
/*
|
||||
* Copyright Altera Corporation (C) 2014-2015 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <div64.h> |
||||
#include <watchdog.h> |
||||
#include <asm/arch/fpga_manager.h> |
||||
#include <asm/arch/sdram.h> |
||||
#include <asm/arch/sdram_config.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <asm/io.h> |
||||
|
||||
/* define constant for 4G memory - used for SDRAM errata workaround */ |
||||
#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
static struct socfpga_sdr_ctrl *sdr_ctrl = |
||||
(struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS); |
||||
|
||||
static int compute_errata_rows(unsigned long long memsize, int cs, int width, |
||||
int rows, int banks, int cols) |
||||
{ |
||||
unsigned long long newrows; |
||||
int inewrowslog2; |
||||
int bits; |
||||
|
||||
debug("workaround rows - memsize %lld\n", memsize); |
||||
debug("workaround rows - cs %d\n", cs); |
||||
debug("workaround rows - width %d\n", width); |
||||
debug("workaround rows - rows %d\n", rows); |
||||
debug("workaround rows - banks %d\n", banks); |
||||
debug("workaround rows - cols %d\n", cols); |
||||
|
||||
newrows = lldiv(memsize, (cs * (width / 8))); |
||||
debug("rows workaround - term1 %lld\n", newrows); |
||||
|
||||
newrows = lldiv(newrows, ((1 << banks) * (1 << cols))); |
||||
debug("rows workaround - term2 %lld\n", newrows); |
||||
|
||||
/* Compute the hamming weight - same as number of bits set.
|
||||
* Need to see if result is ordinal power of 2 before |
||||
* attempting log2 of result. |
||||
*/ |
||||
bits = hweight32(newrows); |
||||
|
||||
debug("rows workaround - bits %d\n", bits); |
||||
|
||||
if (bits != 1) { |
||||
printf("SDRAM workaround failed, bits set %d\n", bits); |
||||
return rows; |
||||
} |
||||
|
||||
if (newrows > UINT_MAX) { |
||||
printf("SDRAM workaround rangecheck failed, %lld\n", newrows); |
||||
return rows; |
||||
} |
||||
|
||||
inewrowslog2 = __ilog2((unsigned int)newrows); |
||||
|
||||
debug("rows workaround - ilog2 %d, %d\n", inewrowslog2, |
||||
(int)newrows); |
||||
|
||||
if (inewrowslog2 == -1) { |
||||
printf("SDRAM workaround failed, newrows %d\n", (int)newrows); |
||||
return rows; |
||||
} |
||||
|
||||
return inewrowslog2; |
||||
} |
||||
|
||||
/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ |
||||
static void sdram_set_rule(struct sdram_prot_rule *prule) |
||||
{ |
||||
uint32_t lo_addr_bits; |
||||
uint32_t hi_addr_bits; |
||||
int ruleno = prule->rule; |
||||
|
||||
/* Select the rule */ |
||||
writel(ruleno, &sdr_ctrl->prot_rule_rdwr); |
||||
|
||||
/* Obtain the address bits */ |
||||
lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF); |
||||
hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF); |
||||
|
||||
debug("sdram set rule start %x, %lld\n", lo_addr_bits, |
||||
prule->sdram_start); |
||||
debug("sdram set rule end %x, %lld\n", hi_addr_bits, |
||||
prule->sdram_end); |
||||
|
||||
/* Set rule addresses */ |
||||
writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); |
||||
|
||||
/* Set rule protection ids */ |
||||
writel(prule->lo_prot_id | (prule->hi_prot_id << 12), |
||||
&sdr_ctrl->prot_rule_id); |
||||
|
||||
/* Set the rule data */ |
||||
writel(prule->security | (prule->valid << 2) | |
||||
(prule->portmask << 3) | (prule->result << 13), |
||||
&sdr_ctrl->prot_rule_data); |
||||
|
||||
/* write the rule */ |
||||
writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr); |
||||
|
||||
/* Set rule number to 0 by default */ |
||||
writel(0, &sdr_ctrl->prot_rule_rdwr); |
||||
} |
||||
|
||||
static void sdram_get_rule(struct sdram_prot_rule *prule) |
||||
{ |
||||
uint32_t addr; |
||||
uint32_t id; |
||||
uint32_t data; |
||||
int ruleno = prule->rule; |
||||
|
||||
/* Read the rule */ |
||||
writel(ruleno, &sdr_ctrl->prot_rule_rdwr); |
||||
writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr); |
||||
|
||||
/* Get the addresses */ |
||||
addr = readl(&sdr_ctrl->prot_rule_addr); |
||||
prule->sdram_start = (addr & 0xFFF) << 20; |
||||
prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; |
||||
|
||||
/* Get the configured protection IDs */ |
||||
id = readl(&sdr_ctrl->prot_rule_id); |
||||
prule->lo_prot_id = id & 0xFFF; |
||||
prule->hi_prot_id = (id >> 12) & 0xFFF; |
||||
|
||||
/* Get protection data */ |
||||
data = readl(&sdr_ctrl->prot_rule_data); |
||||
|
||||
prule->security = data & 0x3; |
||||
prule->valid = (data >> 2) & 0x1; |
||||
prule->portmask = (data >> 3) & 0x3FF; |
||||
prule->result = (data >> 13) & 0x1; |
||||
} |
||||
|
||||
static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end) |
||||
{ |
||||
struct sdram_prot_rule rule; |
||||
int rules; |
||||
|
||||
/* Start with accepting all SDRAM transaction */ |
||||
writel(0x0, &sdr_ctrl->protport_default); |
||||
|
||||
/* Clear all protection rules for warm boot case */ |
||||
memset(&rule, 0, sizeof(struct sdram_prot_rule)); |
||||
|
||||
for (rules = 0; rules < 20; rules++) { |
||||
rule.rule = rules; |
||||
sdram_set_rule(&rule); |
||||
} |
||||
|
||||
/* new rule: accept SDRAM */ |
||||
rule.sdram_start = sdram_start; |
||||
rule.sdram_end = sdram_end; |
||||
rule.lo_prot_id = 0x0; |
||||
rule.hi_prot_id = 0xFFF; |
||||
rule.portmask = 0x3FF; |
||||
rule.security = 0x3; |
||||
rule.result = 0; |
||||
rule.valid = 1; |
||||
rule.rule = 0; |
||||
|
||||
/* set new rule */ |
||||
sdram_set_rule(&rule); |
||||
|
||||
/* default rule: reject everything */ |
||||
writel(0x3ff, &sdr_ctrl->protport_default); |
||||
} |
||||
|
||||
static void sdram_dump_protection_config(void) |
||||
{ |
||||
struct sdram_prot_rule rule; |
||||
int rules; |
||||
|
||||
debug("SDRAM Prot rule, default %x\n", |
||||
readl(&sdr_ctrl->protport_default)); |
||||
|
||||
for (rules = 0; rules < 20; rules++) { |
||||
sdram_get_rule(&rule); |
||||
debug("Rule %d, rules ...\n", rules); |
||||
debug(" sdram start %llx\n", rule.sdram_start); |
||||
debug(" sdram end %llx\n", rule.sdram_end); |
||||
debug(" low prot id %d, hi prot id %d\n", |
||||
rule.lo_prot_id, |
||||
rule.hi_prot_id); |
||||
debug(" portmask %x\n", rule.portmask); |
||||
debug(" security %d\n", rule.security); |
||||
debug(" result %d\n", rule.result); |
||||
debug(" valid %d\n", rule.valid); |
||||
} |
||||
} |
||||
|
||||
/* Function to write to register and verify the write */ |
||||
static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) |
||||
{ |
||||
#ifndef SDRAM_MMR_SKIP_VERIFY |
||||
unsigned reg_value1; |
||||
#endif |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value); |
||||
/* Write to register */ |
||||
writel(reg_value, addr); |
||||
#ifndef SDRAM_MMR_SKIP_VERIFY |
||||
debug(" Read and verify..."); |
||||
/* Read back the wrote value */ |
||||
reg_value1 = readl(addr); |
||||
/* Indicate failure if value not matched */ |
||||
if (reg_value1 != reg_value) { |
||||
debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n", |
||||
(u32)addr, reg_value, reg_value1); |
||||
return 1; |
||||
} |
||||
debug("correct!\n"); |
||||
#endif /* SDRAM_MMR_SKIP_VERIFY */ |
||||
return 0; |
||||
} |
||||
|
||||
static void set_sdr_ctrlcfg(void) |
||||
{ |
||||
int addrorder; |
||||
|
||||
debug("\nConfiguring CTRLCFG\n"); |
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << |
||||
SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB); |
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << |
||||
SDR_CTRLGRP_CTRLCFG_MEMBL_LSB); |
||||
|
||||
|
||||
/* SDRAM Failure When Accessing Non-Existent Memory
|
||||
* Set the addrorder field of the SDRAM control register |
||||
* based on the CSBITs setting. |
||||
*/ |
||||
switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) { |
||||
case 1: |
||||
addrorder = 0; /* chip, row, bank, column */ |
||||
if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0) |
||||
debug("INFO: Changing address order to 0 (chip, row, \
|
||||
bank, column)\n"); |
||||
break; |
||||
case 2: |
||||
addrorder = 2; /* row, chip, bank, column */ |
||||
if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2) |
||||
debug("INFO: Changing address order to 2 (row, chip, \
|
||||
bank, column)\n"); |
||||
break; |
||||
default: |
||||
addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER; |
||||
break; |
||||
} |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK, |
||||
addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << |
||||
SDR_CTRLGRP_CTRLCFG_ECCEN_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << |
||||
SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << |
||||
SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << |
||||
SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << |
||||
SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << |
||||
SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB); |
||||
} |
||||
|
||||
static void set_sdr_dram_timing1(void) |
||||
{ |
||||
debug("Configuring DRAMTIMING1\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << |
||||
SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << |
||||
SDR_CTRLGRP_DRAMTIMING1_TAL_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << |
||||
SDR_CTRLGRP_DRAMTIMING1_TCL_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << |
||||
SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << |
||||
SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << |
||||
SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB); |
||||
} |
||||
|
||||
static void set_sdr_dram_timing2(void) |
||||
{ |
||||
debug("Configuring DRAMTIMING2\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << |
||||
SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << |
||||
SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << |
||||
SDR_CTRLGRP_DRAMTIMING2_TRP_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << |
||||
SDR_CTRLGRP_DRAMTIMING2_TWR_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << |
||||
SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB); |
||||
} |
||||
|
||||
static void set_sdr_dram_timing3(void) |
||||
{ |
||||
debug("Configuring DRAMTIMING3\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << |
||||
SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << |
||||
SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << |
||||
SDR_CTRLGRP_DRAMTIMING3_TRC_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << |
||||
SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << |
||||
SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB); |
||||
} |
||||
|
||||
static void set_sdr_dram_timing4(void) |
||||
{ |
||||
debug("Configuring DRAMTIMING4\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_timing4, |
||||
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << |
||||
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_timing4, |
||||
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << |
||||
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB); |
||||
} |
||||
|
||||
static void set_sdr_dram_lowpwr_timing(void) |
||||
{ |
||||
debug("Configuring LOWPWRTIMING\n"); |
||||
clrsetbits_le32(&sdr_ctrl->lowpwr_timing, |
||||
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << |
||||
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->lowpwr_timing, |
||||
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << |
||||
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB); |
||||
} |
||||
|
||||
static void set_sdr_addr_rw(void) |
||||
{ |
||||
int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; |
||||
int width = 8; |
||||
int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; |
||||
int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS; |
||||
int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS; |
||||
unsigned long long workaround_memsize = MEMSIZE_4G; |
||||
|
||||
debug("Configuring DRAMADDRW\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << |
||||
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB); |
||||
/*
|
||||
* SDRAM Failure When Accessing Non-Existent Memory |
||||
* Update Preloader to artificially increase the number of rows so |
||||
* that the memory thinks it has 4GB of RAM. |
||||
*/ |
||||
rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks, |
||||
cols); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK, |
||||
rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << |
||||
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB); |
||||
/* SDRAM Failure When Accessing Non-Existent Memory
|
||||
* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to |
||||
* log2(number of chip select bits). Since there's only |
||||
* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, |
||||
* which is the same as "chip selects" - 1. |
||||
*/ |
||||
clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK, |
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << |
||||
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB); |
||||
} |
||||
|
||||
static void set_sdr_static_cfg(void) |
||||
{ |
||||
debug("Configuring STATICCFG\n"); |
||||
clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << |
||||
SDR_CTRLGRP_STATICCFG_MEMBL_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->static_cfg, |
||||
SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << |
||||
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB); |
||||
} |
||||
|
||||
static void set_sdr_fifo_cfg(void) |
||||
{ |
||||
debug("Configuring FIFOCFG\n"); |
||||
clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << |
||||
SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << |
||||
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB); |
||||
} |
||||
|
||||
static void set_sdr_mp_weight(void) |
||||
{ |
||||
debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); |
||||
clrsetbits_le32(&sdr_ctrl->mp_weight0, |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_weight1, |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_weight1, |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_weight2, |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_weight3, |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << |
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB); |
||||
} |
||||
|
||||
static void set_sdr_mp_pacing(void) |
||||
{ |
||||
debug("Configuring MPPACING_MPPACING_0\n"); |
||||
clrsetbits_le32(&sdr_ctrl->mp_pacing0, |
||||
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << |
||||
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_pacing1, |
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << |
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_pacing1, |
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << |
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_pacing2, |
||||
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << |
||||
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_pacing3, |
||||
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << |
||||
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB); |
||||
} |
||||
|
||||
static void set_sdr_mp_threshold(void) |
||||
{ |
||||
debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); |
||||
clrsetbits_le32(&sdr_ctrl->mp_threshold0, |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_threshold1, |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK, |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK << |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->mp_threshold2, |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB); |
||||
} |
||||
|
||||
|
||||
/* Function to initialize SDRAM MMR */ |
||||
unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) |
||||
{ |
||||
unsigned long reg_value; |
||||
unsigned long status = 0; |
||||
|
||||
#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \ |
||||
defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
|
||||
defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
|
||||
defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
|
||||
defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) |
||||
|
||||
writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS, |
||||
&sysmgr_regs->iswgrp_handoff[4]); |
||||
#endif |
||||
set_sdr_ctrlcfg(); |
||||
set_sdr_dram_timing1(); |
||||
set_sdr_dram_timing2(); |
||||
set_sdr_dram_timing3(); |
||||
set_sdr_dram_timing4(); |
||||
set_sdr_dram_lowpwr_timing(); |
||||
set_sdr_addr_rw(); |
||||
|
||||
debug("Configuring DRAMIFWIDTH\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_if_width, |
||||
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << |
||||
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB); |
||||
|
||||
debug("Configuring DRAMDEVWIDTH\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_dev_width, |
||||
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << |
||||
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB); |
||||
|
||||
debug("Configuring LOWPWREQ\n"); |
||||
clrsetbits_le32(&sdr_ctrl->lowpwr_eq, |
||||
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << |
||||
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB); |
||||
|
||||
debug("Configuring DRAMINTR\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << |
||||
SDR_CTRLGRP_DRAMINTR_INTREN_LSB); |
||||
|
||||
set_sdr_static_cfg(); |
||||
|
||||
debug("Configuring CTRLWIDTH\n"); |
||||
clrsetbits_le32(&sdr_ctrl->ctrl_width, |
||||
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << |
||||
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB); |
||||
|
||||
debug("Configuring PORTCFG\n"); |
||||
clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << |
||||
SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB); |
||||
|
||||
set_sdr_fifo_cfg(); |
||||
|
||||
debug("Configuring MPPRIORITY\n"); |
||||
clrsetbits_le32(&sdr_ctrl->mp_priority, |
||||
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << |
||||
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB); |
||||
|
||||
set_sdr_mp_weight(); |
||||
set_sdr_mp_pacing(); |
||||
set_sdr_mp_threshold(); |
||||
|
||||
debug("Configuring PHYCTRL_PHYCTRL_0\n"); |
||||
setbits_le32(&sdr_ctrl->phy_ctrl0, |
||||
CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0); |
||||
|
||||
debug("Configuring CPORTWIDTH\n"); |
||||
clrsetbits_le32(&sdr_ctrl->cport_width, |
||||
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << |
||||
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->cport_width), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->cport_width); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring CPORTWMAP\n"); |
||||
clrsetbits_le32(&sdr_ctrl->cport_wmap, |
||||
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << |
||||
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->cport_wmap), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->cport_wmap); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring CPORTRMAP\n"); |
||||
clrsetbits_le32(&sdr_ctrl->cport_rmap, |
||||
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << |
||||
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->cport_rmap), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->cport_rmap); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring RFIFOCMAP\n"); |
||||
clrsetbits_le32(&sdr_ctrl->rfifo_cmap, |
||||
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << |
||||
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->rfifo_cmap), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->rfifo_cmap); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring WFIFOCMAP\n"); |
||||
reg_value = readl(&sdr_ctrl->wfifo_cmap); |
||||
clrsetbits_le32(&sdr_ctrl->wfifo_cmap, |
||||
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << |
||||
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->wfifo_cmap), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->wfifo_cmap); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring CPORTRDWR\n"); |
||||
clrsetbits_le32(&sdr_ctrl->cport_rdwr, |
||||
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << |
||||
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->cport_rdwr), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->cport_rdwr); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
debug("Configuring DRAMODT\n"); |
||||
clrsetbits_le32(&sdr_ctrl->dram_odt, |
||||
SDR_CTRLGRP_DRAMODT_READ_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << |
||||
SDR_CTRLGRP_DRAMODT_READ_LSB); |
||||
|
||||
clrsetbits_le32(&sdr_ctrl->dram_odt, |
||||
SDR_CTRLGRP_DRAMODT_WRITE_MASK, |
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << |
||||
SDR_CTRLGRP_DRAMODT_WRITE_LSB); |
||||
|
||||
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ |
||||
writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, |
||||
&sysmgr_regs->iswgrp_handoff[3]); |
||||
|
||||
/* only enable if the FPGA is programmed */ |
||||
if (fpgamgr_test_fpga_ready()) { |
||||
if (sdram_write_verify(&sdr_ctrl->fpgaport_rst, |
||||
CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) { |
||||
status = 1; |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
/* Restore the SDR PHY Register if valid */ |
||||
if (sdr_phy_reg != 0xffffffff) |
||||
writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); |
||||
|
||||
/***** Final step - apply configuration changes *****/ |
||||
debug("Configuring STATICCFG_\n"); |
||||
clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, |
||||
1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); |
||||
debug(" Write - Address "); |
||||
debug("0x%08x Data 0x%08x\n", |
||||
(unsigned)(&sdr_ctrl->static_cfg), |
||||
(unsigned)reg_value); |
||||
reg_value = readl(&sdr_ctrl->static_cfg); |
||||
debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); |
||||
|
||||
sdram_set_protection_config(0, sdram_calculate_size()); |
||||
|
||||
sdram_dump_protection_config(); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/*
|
||||
* To calculate SDRAM device size based on SDRAM controller parameters. |
||||
* Size is specified in bytes. |
||||
* |
||||
* NOTE: |
||||
* This function is compiled and linked into the preloader and |
||||
* Uboot (there may be others). So if this function changes, the Preloader |
||||
* and UBoot must be updated simultaneously. |
||||
*/ |
||||
unsigned long sdram_calculate_size(void) |
||||
{ |
||||
unsigned long temp; |
||||
unsigned long row, bank, col, cs, width; |
||||
|
||||
temp = readl(&sdr_ctrl->dram_addrw); |
||||
col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> |
||||
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; |
||||
|
||||
/* SDRAM Failure When Accessing Non-Existent Memory
|
||||
* Use ROWBITS from Quartus/QSys to calculate SDRAM size |
||||
* since the FB specifies we modify ROWBITs to work around SDRAM |
||||
* controller issue. |
||||
* |
||||
* If the stored handoff value for rows is 0, it probably means |
||||
* the preloader is older than UBoot. Use the |
||||
* #define from the SOCEDS Tools per Crucible review |
||||
* uboot-socfpga-204. Note that this is not a supported |
||||
* configuration and is not tested. The customer |
||||
* should be using preloader and uboot built from the |
||||
* same tag. |
||||
*/ |
||||
row = readl(&sysmgr_regs->iswgrp_handoff[4]); |
||||
if (row == 0) |
||||
row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; |
||||
/* If the stored handoff value for rows is greater than
|
||||
* the field width in the sdr.dramaddrw register then |
||||
* something is very wrong. Revert to using the the #define |
||||
* value handed off by the SOCEDS tool chain instead of |
||||
* using a broken value. |
||||
*/ |
||||
if (row > 31) |
||||
row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; |
||||
|
||||
bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> |
||||
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; |
||||
|
||||
/* SDRAM Failure When Accessing Non-Existent Memory
|
||||
* Use CSBITs from Quartus/QSys to calculate SDRAM size |
||||
* since the FB specifies we modify CSBITs to work around SDRAM |
||||
* controller issue. |
||||
*/ |
||||
cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> |
||||
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB; |
||||
cs += 1; |
||||
|
||||
cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; |
||||
|
||||
width = readl(&sdr_ctrl->dram_if_width); |
||||
/* ECC would not be calculated as its not addressible */ |
||||
if (width == SDRAM_WIDTH_32BIT_WITH_ECC) |
||||
width = 32; |
||||
if (width == SDRAM_WIDTH_16BIT_WITH_ECC) |
||||
width = 16; |
||||
|
||||
/* calculate the SDRAM size base on this info */ |
||||
temp = 1 << (row + bank + col); |
||||
temp = temp * cs * (width / 8); |
||||
|
||||
debug("sdram_calculate_memory returns %ld\n", temp); |
||||
|
||||
return temp; |
||||
} |
Loading…
Reference in new issue