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@ -92,17 +92,17 @@ void set_muxconf_regs(void) |
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static void setup_net_chip(void) |
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{ |
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gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; |
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gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; |
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gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; |
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ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; |
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/* Configure GPMC registers */ |
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writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); |
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writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); |
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writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); |
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writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); |
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writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); |
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writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); |
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writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); |
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writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); |
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writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); |
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writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); |
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writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); |
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writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); |
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writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); |
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writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7); |
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
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writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
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