This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>master
Masahiro Yamada
9 years ago
parent
881aa5a79a
commit
9d0c2ceb35
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-y += timer.o
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else |
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obj-y += mem_map.o smp.o smp_kick_cpus.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
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endif |
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/*
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* Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect |
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* |
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mapmem.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#define CCI500_BASE 0x5FD00000 |
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#define CCI500_SLAVE_OFFSET 0x1000 |
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#define CCI500_SNOOP_CTRL |
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#define CCI500_SNOOP_CTRL_EN_DVM BIT(1) |
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#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0) |
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void cci500_init(unsigned int nr_slaves) |
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{ |
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unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET; |
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int i; |
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for (i = 0; i < nr_slaves; i++) { |
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void __iomem *base; |
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u32 tmp; |
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base = map_sysmem(slave_base, SZ_4K); |
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tmp = readl(base); |
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tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP; |
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writel(tmp, base); |
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unmap_sysmem(base); |
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slave_base += CCI500_SLAVE_OFFSET; |
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} |
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} |
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/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/types.h> |
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#include <asm/armv8/mmu.h> |
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static struct mm_region uniphier_mem_map[] = { |
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{ |
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.base = 0x00000000, |
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.size = 0x80000000, |
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, |
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{ |
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.base = 0x80000000, |
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.size = 0xc0000000, |
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_INNER_SHARE |
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}, |
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{ /* sentinel */ } |
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}; |
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struct mm_region *mem_map = uniphier_mem_map; |
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/* |
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/linkage.h> |
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ENTRY(uniphier_smp_setup) |
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mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */ |
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orr x0, x0, #(1 << 6) /* SMPEN */ |
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msr s3_1_c15_c2_1, x0 |
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ret |
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ENDPROC(uniphier_smp_setup) |
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ENTRY(uniphier_secondary_startup) |
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bl uniphier_smp_setup |
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b _start |
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ENDPROC(uniphier_secondary_startup) |
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/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mapmem.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 |
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void uniphier_smp_setup(void); |
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void uniphier_secondary_startup(void); |
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void uniphier_smp_kick_all_cpus(void) |
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{ |
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void __iomem *rom_boot_rsv0; |
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rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); |
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writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); |
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readq(rom_boot_rsv0); /* relax */ |
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unmap_sysmem(rom_boot_rsv0); |
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uniphier_smp_setup(); |
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asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ |
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} |
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/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mapmem.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#define CNT_CONTROL_BASE 0x60E00000 |
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#define CNTCR 0x000 |
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#define CNTCR_EN BIT(0) |
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/* setup ARMv8 Generic Timer */ |
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int timer_init(void) |
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{ |
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void __iomem *base; |
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u32 tmp; |
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base = map_sysmem(CNT_CONTROL_BASE, SZ_4K); |
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/*
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* Note: |
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* In a system that implements both Secure and Non-secure states, |
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* this register is only writable in Secure state. |
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*/ |
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tmp = readl(base + CNTCR); |
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tmp |= CNTCR_EN; |
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writel(tmp, base + CNTCR); |
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unmap_sysmem(base); |
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return 0; |
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} |
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/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <linux/io.h> |
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#include "../sg-regs.h" |
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#include "boot-device.h" |
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static struct boot_device_info boot_device_table[] = { |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, |
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{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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}; |
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static int get_boot_mode_sel(void) |
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{ |
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return (readl(SG_PINMON0) >> 1) & 0x1f; |
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} |
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u32 uniphier_ld20_boot_device(void) |
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{ |
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int boot_mode; |
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if (~readl(SG_PINMON0) & 0x00000780) |
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return BOOT_DEVICE_USB; |
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boot_mode = get_boot_mode_sel(); |
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return boot_device_table[boot_mode].type; |
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} |
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void uniphier_ld20_boot_mode_show(void) |
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{ |
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int mode_sel, i; |
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mode_sel = get_boot_mode_sel(); |
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puts("Boot Mode Pin:\n"); |
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for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) |
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printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, |
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boot_device_table[i].info); |
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} |
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/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sc64-regs.h" |
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void uniphier_ld20_clk_init(void) |
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{ |
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} |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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*/ |
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#ifndef _DDRPHY_LD20_REGS_H |
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#define _DDRPHY_LD20_REGS_H |
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#define PHY_SCL_DATA_0 0x00000104 |
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#define PHY_SCL_DATA_1 0x00000108 |
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#define PHY_SCL_LATENCY 0x0000010C |
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#define PHY_SCL_START 0x00000100 |
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#define PHY_SCL_CONFIG_1 0x00000118 |
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#define PHY_SCL_CONFIG_2 0x0000011C |
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#define PHY_PAD_CTRL 0x00000120 |
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#define PHY_DLL_RECALIB 0x00000124 |
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#define PHY_DLL_ADRCTRL 0x00000128 |
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#define PHY_LANE_SEL 0x0000012C |
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#define PHY_DLL_TRIM_1 0x00000130 |
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#define PHY_DLL_TRIM_2 0x00000134 |
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#define PHY_DLL_TRIM_3 0x00000138 |
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#define PHY_SCL_MAIN_CLK_DELTA 0x00000140 |
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#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C |
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#define PHY_WRLVL_DYN_ODT 0x00000150 |
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#define PHY_WRLVL_ON_OFF 0x00000154 |
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#define PHY_UNQ_ANALOG_DLL_1 0x0000015C |
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#define PHY_DLL_INCR_TRIM_1 0x00000164 |
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#define PHY_DLL_INCR_TRIM_3 0x00000168 |
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#define PHY_SCL_CONFIG_3 0x0000016C |
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#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170 |
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#define PHY_SCL_START_ADDR 0x00000188 |
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#define PHY_DSCL_CNT 0x0000019C |
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#define PHY_DLL_TRIM_CLK 0x000001A4 |
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#define PHY_DYNAMIC_BIT_LVL 0x000001AC |
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#define PHY_SCL_WINDOW_TRIM 0x000001B4 |
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#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8 |
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#define PHY_SCL_CONFIG_4 0x000001BC |
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#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0 |
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#define PHY_VREF_TRAINING 0x000001C8 |
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#define PHY_SCL_GATE_TIMING 0x000001E0 |
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#endif /* _DDRPHY_LD20_REGS_H */ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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*/ |
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#ifndef UMC_LD20_REGS_H |
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#define UMC_LD20_REGS_H |
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#define UMC_CMDCTLA 0x00000000 |
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#define UMC_CMDCTLB 0x00000004 |
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#define UMC_CMDCTLC 0x00000008 |
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#define UMC_INITCTLA 0x00000020 |
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#define UMC_INITCTLB 0x00000024 |
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#define UMC_INITCTLC 0x00000028 |
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#define UMC_DRMMR0 0x00000030 |
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#define UMC_DRMMR1 0x00000034 |
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#define UMC_DRMMR2 0x00000038 |
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#define UMC_DRMMR3 0x0000003C |
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#define UMC_INITSET 0x00000040 |
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#define UMC_INITSTAT 0x00000044 |
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#define UMC_CMDCTLE 0x00000050 |
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#define UMC_SPCSETB 0x00000084 |
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#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ |
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#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ |
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#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ |
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#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ |
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#define UMC_ACSCTLA 0x000000C0 |
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#define UMC_ACSSETA 0x000000C4 |
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#define UMC_MEMCONF0A 0x00000200 |
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#define UMC_MEMCONF0B 0x00000204 |
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#define UMC_MEMCONFCH 0x00000240 |
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#define UMC_MEMMAPSET 0x00000250 |
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#define UMC_FLOWCTLA 0x00000400 |
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#define UMC_FLOWCTLB 0x00000404 |
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#define UMC_FLOWCTLC 0x00000408 |
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#define UMC_FLOWCTLG 0x00000508 |
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#define UMC_RDATACTL_D0 0x00000600 |
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#define UMC_WDATACTL_D0 0x00000604 |
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#define UMC_RDATACTL_D1 0x00000608 |
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#define UMC_WDATACTL_D1 0x0000060C |
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#define UMC_DATASET 0x00000610 |
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#define UMC_ODTCTL_D0 0x00000618 |
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#define UMC_ODTCTL_D1 0x0000061C |
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#define UMC_RESPCTL 0x00000624 |
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#define UMC_DIRECTBUSCTRLA 0x00000680 |
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#define UMC_DCCGCTL 0x00000720 |
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#define UMC_DICGCTLA 0x00000724 |
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#define UMC_DICGCTLB 0x00000728 |
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#define UMC_ERRMASKA 0x00000958 |
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#define UMC_ERRMASKB 0x0000095C |
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#define UMC_BSICMAPSET 0x00000988 |
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#define UMC_DIOCTLA 0x00000C00 |
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#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ |
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#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ |
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#define UMC_DFISTCTLC 0x00000C18 |
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#define UMC_DFICUPDCTLA 0x00000C20 |
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#define UMC_DFIPUPDCTLA 0x00000C30 |
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#define UMC_DFICSOVRRD 0x00000C84 |
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#define UMC_DFITURNOFF 0x00000C88 |
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/* UM registers */ |
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#define UMC_MBUS0 0x00080004 |
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#define UMC_MBUS1 0x00081004 |
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#define UMC_MBUS2 0x00082004 |
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#define UMC_MBUS3 0x00000C78 |
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#define UMC_MBUS4 0x00000CF8 |
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#define UMC_MBUS5 0x00000E78 |
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#define UMC_MBUS6 0x00000EF8 |
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#define UMC_MBUS7 0x00001278 |
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#define UMC_MBUS8 0x000012F8 |
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#define UMC_MBUS9 0x00002478 |
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#define UMC_MBUS10 0x000024F8 |
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#endif /* UMC_LD20_REGS_H */ |
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@ -0,0 +1,306 @@ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* |
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* based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/bitops.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include <asm/processor.h> |
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#include "../init.h" |
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#include "ddrphy-ld20-regs.h" |
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#include "umc-ld20-regs.h" |
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#define DRAM_CH_NR 3 |
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enum dram_freq { |
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DRAM_FREQ_1866M, |
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DRAM_FREQ_NR, |
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}; |
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enum dram_size { |
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DRAM_SZ_256M, |
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DRAM_SZ_512M, |
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DRAM_SZ_NR, |
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}; |
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/* umc */ |
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static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; |
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static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; |
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static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; |
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static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; |
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static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; |
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static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801}; |
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static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130}; |
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static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803}; |
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static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; |
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static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; |
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static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; |
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static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { |
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{0x0049071D, 0x0078071D}, |
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}; |
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static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; |
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static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610}; |
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static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204}; |
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static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204}; |
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static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; |
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static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; |
||||
static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; |
||||
|
||||
static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; |
||||
static u32 umc_directbusctrla[DRAM_CH_NR] = { |
||||
0x00000000, 0x00000001, 0x00000001 |
||||
}; |
||||
|
||||
/* DDR PHY */ |
||||
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) |
||||
{ |
||||
writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); |
||||
while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); |
||||
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); |
||||
writel(0x00000000, phy_base + PHY_LANE_SEL); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
writel(0x00000006, phy_base + PHY_LANE_SEL); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
writel(0x0000000c, phy_base + PHY_LANE_SEL); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
writel(0x00000012, phy_base + PHY_LANE_SEL); |
||||
writel(0x00000005, phy_base + PHY_DLL_TRIM_1); |
||||
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); |
||||
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); |
||||
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); |
||||
writel(0x50bb40b1, phy_base + PHY_PAD_CTRL); |
||||
writel(0x00000070, phy_base + PHY_VREF_TRAINING); |
||||
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); |
||||
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); |
||||
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); |
||||
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); |
||||
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); |
||||
writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING); |
||||
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); |
||||
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); |
||||
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); |
||||
writel(0x00000000, phy_base + PHY_LANE_SEL); |
||||
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); |
||||
writel(0xa800100d, phy_base + PHY_DLL_RECALIB); |
||||
writel(0x00005076, phy_base + PHY_SCL_LATENCY); |
||||
} |
||||
|
||||
static int ddrphy_training(void __iomem *phy_base) |
||||
{ |
||||
writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); |
||||
writel(0x00010000, phy_base + PHY_DLL_TRIM_2); |
||||
writel(0x50000000, phy_base + PHY_SCL_START); |
||||
|
||||
while ((readl(phy_base + PHY_SCL_START) & BIT(28))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); |
||||
writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); |
||||
writel(0x00080000, phy_base + PHY_SCL_START_ADDR); |
||||
writel(0x11000000, phy_base + PHY_SCL_START); |
||||
|
||||
while ((readl(phy_base + PHY_SCL_START) & BIT(28))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000000, phy_base + PHY_SCL_START_ADDR); |
||||
writel(0x30500000, phy_base + PHY_SCL_START); |
||||
|
||||
while ((readl(phy_base + PHY_SCL_START) & BIT(28))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA); |
||||
writel(0x789b3de0, phy_base + PHY_SCL_DATA_0); |
||||
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); |
||||
writel(0x11000000, phy_base + PHY_SCL_START); |
||||
|
||||
while ((readl(phy_base + PHY_SCL_START) & BIT(28))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x34000000, phy_base + PHY_SCL_START); |
||||
|
||||
while ((readl(phy_base + PHY_SCL_START) & BIT(28))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, |
||||
unsigned long size, int ch) |
||||
{ |
||||
enum dram_size size_e; |
||||
|
||||
switch (size) { |
||||
case 0: |
||||
return 0; |
||||
case SZ_256M: |
||||
size_e = DRAM_SZ_256M; |
||||
break; |
||||
case SZ_512M: |
||||
size_e = DRAM_SZ_512M; |
||||
break; |
||||
default: |
||||
pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", |
||||
size, ch); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* Wait for PHY Init Complete */ |
||||
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) |
||||
cpu_relax(); |
||||
|
||||
writel(0x00000001, dc_base + UMC_DFICSOVRRD); |
||||
writel(0x00000000, dc_base + UMC_DFITURNOFF); |
||||
|
||||
writel(umc_initctla[freq], dc_base + UMC_INITCTLA); |
||||
writel(umc_initctlb[freq], dc_base + UMC_INITCTLB); |
||||
writel(umc_initctlc[freq], dc_base + UMC_INITCTLC); |
||||
|
||||
writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0); |
||||
writel(0x00000004, dc_base + UMC_DRMMR1); |
||||
writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2); |
||||
writel(0x00000000, dc_base + UMC_DRMMR3); |
||||
|
||||
writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A); |
||||
writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B); |
||||
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); |
||||
writel(0x00000008, dc_base + UMC_MEMMAPSET); |
||||
|
||||
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); |
||||
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); |
||||
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); |
||||
writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE); |
||||
|
||||
writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); |
||||
writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); |
||||
|
||||
writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); |
||||
writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); |
||||
writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); |
||||
writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); |
||||
writel(umc_dataset[freq], dc_base + UMC_DATASET); |
||||
|
||||
writel(0x00400020, dc_base + UMC_DCCGCTL); |
||||
writel(0x00000003, dc_base + UMC_ACSCTLA); |
||||
writel(0x00000103, dc_base + UMC_FLOWCTLG); |
||||
writel(0x00010200, dc_base + UMC_ACSSETA); |
||||
|
||||
writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA); |
||||
writel(0x00004444, dc_base + UMC_FLOWCTLC); |
||||
writel(0x00000000, dc_base + UMC_DFICUPDCTLA); |
||||
|
||||
writel(0x00202000, dc_base + UMC_FLOWCTLB); |
||||
writel(0x00000000, dc_base + UMC_BSICMAPSET); |
||||
writel(0x00000000, dc_base + UMC_ERRMASKA); |
||||
writel(0x00000000, dc_base + UMC_ERRMASKB); |
||||
|
||||
writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA); |
||||
|
||||
writel(0x00000001, dc_base + UMC_INITSET); |
||||
/* Wait for PHY Init Complete */ |
||||
while (readl(dc_base + UMC_INITSTAT) & BIT(0)) |
||||
cpu_relax(); |
||||
|
||||
writel(0x2A0A0A00, dc_base + UMC_SPCSETB); |
||||
writel(0x00000000, dc_base + UMC_DFICSOVRRD); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, |
||||
enum dram_freq freq, unsigned long size, int ch) |
||||
{ |
||||
void __iomem *dc_base = umc_ch_base + 0x00011000; |
||||
void __iomem *phy_base = phy_ch_base; |
||||
int ret; |
||||
|
||||
/* PHY Update Mode (ON) */ |
||||
writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA); |
||||
|
||||
/* deassert PHY reset signals */ |
||||
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, |
||||
dc_base + UMC_DIOCTLA); |
||||
|
||||
ddrphy_init(phy_base, freq); |
||||
|
||||
ret = umc_dc_init(dc_base, freq, size, ch); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = ddrphy_training(phy_base); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void um_init(void __iomem *um_base) |
||||
{ |
||||
writel(0x000000ff, um_base + UMC_MBUS0); |
||||
writel(0x000000ff, um_base + UMC_MBUS1); |
||||
writel(0x000000ff, um_base + UMC_MBUS2); |
||||
writel(0x00000001, um_base + UMC_MBUS3); |
||||
writel(0x00000001, um_base + UMC_MBUS4); |
||||
writel(0x00000001, um_base + UMC_MBUS5); |
||||
writel(0x00000001, um_base + UMC_MBUS6); |
||||
writel(0x00000001, um_base + UMC_MBUS7); |
||||
writel(0x00000001, um_base + UMC_MBUS8); |
||||
writel(0x00000001, um_base + UMC_MBUS9); |
||||
writel(0x00000001, um_base + UMC_MBUS10); |
||||
} |
||||
|
||||
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
void __iomem *um_base = (void __iomem *)0x5b600000; |
||||
void __iomem *umc_ch_base = (void __iomem *)0x5b800000; |
||||
void __iomem *phy_ch_base = (void __iomem *)0x6e200000; |
||||
enum dram_freq freq; |
||||
int ch, ret; |
||||
|
||||
switch (bd->dram_freq) { |
||||
case 1866: |
||||
freq = DRAM_FREQ_1866M; |
||||
break; |
||||
default: |
||||
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
for (ch = 0; ch < bd->dram_nr_ch; ch++) { |
||||
unsigned long size = bd->dram_ch[ch].size; |
||||
unsigned int width = bd->dram_ch[ch].width; |
||||
|
||||
ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, |
||||
size / (width / 16), ch); |
||||
if (ret) { |
||||
pr_err("failed to initialize UMC ch%d\n", ch); |
||||
return ret; |
||||
} |
||||
|
||||
umc_ch_base += 0x00200000; |
||||
phy_ch_base += 0x00004000; |
||||
} |
||||
|
||||
um_init(um_base); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc64-regs.h" |
||||
|
||||
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* deassert reset */ |
||||
tmp = readl(SC_RSTCTRL7); |
||||
tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | |
||||
SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | |
||||
SC_RSTCTRL7_UMC30; |
||||
writel(tmp, SC_RSTCTRL7); |
||||
|
||||
/* provide clocks */ |
||||
tmp = readl(SC_CLKCTRL7); |
||||
tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | |
||||
SC_CLKCTRL7_UMC30; |
||||
writel(tmp, SC_CLKCTRL7); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,53 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../micro-support-card.h" |
||||
|
||||
int uniphier_ld20_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
uniphier_sbc_init_savepin(bd); |
||||
|
||||
support_card_reset(); |
||||
|
||||
support_card_init(); |
||||
|
||||
led_puts("L0"); |
||||
|
||||
memconf_init(bd); |
||||
uniphier_pxs2_memconf_init(bd); |
||||
|
||||
led_puts("L1"); |
||||
|
||||
uniphier_ld20_early_clk_init(bd); |
||||
|
||||
led_puts("L2"); |
||||
|
||||
led_puts("L3"); |
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT |
||||
preloader_console_init(); |
||||
#endif |
||||
|
||||
led_puts("L4"); |
||||
|
||||
{ |
||||
int res; |
||||
|
||||
res = uniphier_ld20_umc_init(bd); |
||||
if (res < 0) { |
||||
while (1) |
||||
; |
||||
} |
||||
} |
||||
|
||||
led_puts("L5"); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,46 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_ld20_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ |
||||
sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ |
||||
sg_set_iectrl_range(3, 17); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */ |
||||
sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ |
||||
sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */ |
||||
sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ |
||||
sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ |
||||
sg_set_iectrl_range(46, 53); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,28 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_UNIPHIER=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_ARCH_UNIPHIER_LD20=y |
||||
CONFIG_MICRO_SUPPORT_CARD=y |
||||
CONFIG_SYS_TEXT_BASE=0x84000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref" |
||||
CONFIG_HUSH_PARSER=y |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
# CONFIG_CMD_MISC is not set |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_OF_TRANSLATE=y |
||||
CONFIG_GPIO_UNIPHIER=y |
||||
CONFIG_MMC_UNIPHIER=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_SPL_PINCTRL=y |
||||
CONFIG_UNIPHIER_SERIAL=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_XHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
Loading…
Reference in new issue