* Add support for MPC8247 based "IDS8247" board.master
parent
d44e14b5fc
commit
9dd41a7b0c
@ -0,0 +1,40 @@ |
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o
|
||||
|
||||
$(LIB): .depend $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,34 @@ |
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# IDS 8247 Board
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
|
||||
# for the "final" configuration, with U-Boot in flash, or the address
|
||||
# in RAM where U-Boot is loaded at for debugging.
|
||||
#
|
||||
TEXT_BASE = 0xfff00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
@ -0,0 +1,484 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Heiko Schocher, DENX Software Engineering, <hs@denx.de> |
||||
* |
||||
* (C) Copyright 2001 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2001-2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#undef DEBUG |
||||
|
||||
#include <common.h> |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
# ifndef CFG_ENV_ADDR |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
||||
# endif |
||||
# ifndef CFG_ENV_SIZE |
||||
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
||||
# endif |
||||
# ifndef CFG_ENV_SECT_SIZE |
||||
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
||||
# endif |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Protection Flags: |
||||
*/ |
||||
#define FLAG_PROTECT_SET 0x01 |
||||
#define FLAG_PROTECT_CLEAR 0x02 |
||||
|
||||
/* Board support for 1 or 2 flash devices */ |
||||
#undef FLASH_PORT_WIDTH32 |
||||
#undef FLASH_PORT_WIDTH16 |
||||
#define FLASH_PORT_WIDTH8 |
||||
|
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
#define FLASH_PORT_WIDTH ushort |
||||
#define FLASH_PORT_WIDTHV vu_short |
||||
#elif FLASH_PORT_WIDTH32 |
||||
#define FLASH_PORT_WIDTH ulong |
||||
#define FLASH_PORT_WIDTHV vu_long |
||||
#else /* FLASH_PORT_WIDTH8 */ |
||||
#define FLASH_PORT_WIDTH uchar |
||||
#define FLASH_PORT_WIDTHV vu_char |
||||
#endif |
||||
|
||||
#define FPW FLASH_PORT_WIDTH |
||||
#define FPWV FLASH_PORT_WIDTHV |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (FPWV * addr, flash_info_t * info); |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size_b0; |
||||
int i; |
||||
volatile immap_t * immr = (immap_t *)CFG_IMMR; |
||||
volatile memctl8260_t *memctl = &immr->im_memctl; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0 << 20); |
||||
} |
||||
|
||||
memctl->memc_or0 = 0xff800060; |
||||
memctl->memc_br0 = 0xff800801; |
||||
|
||||
flash_get_offsets (0xff800000, &flash_info[0]); |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
(void) flash_protect (FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE + monitor_flash_len - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
flash_info[0].size = size_b0; |
||||
|
||||
return (size_b0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return; |
||||
} |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00020000); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_INTEL: |
||||
printf ("INTEL "); |
||||
break; |
||||
default: |
||||
printf ("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_28F320J3A: |
||||
printf ("28F320J3A\n"); |
||||
break; |
||||
case FLASH_28F640J3A: |
||||
printf ("28F640J3A\n"); |
||||
break; |
||||
case FLASH_28F128J3A: |
||||
printf ("28F128J3A\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
static ulong flash_get_size (FPWV * addr, flash_info_t * info) |
||||
{ |
||||
FPW value; |
||||
|
||||
addr[0] = (FPW) 0x00900090; |
||||
|
||||
value = addr[0]; |
||||
|
||||
debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); |
||||
|
||||
switch (value) { |
||||
case (FPW) INTEL_MANUFACT: |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
#ifdef FLASH_PORT_WIDTH8 |
||||
value = addr[2]; /* device ID */ |
||||
#else |
||||
value = addr[1]; /* device ID */ |
||||
#endif |
||||
|
||||
debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); |
||||
|
||||
switch (value) { |
||||
case (FPW) INTEL_ID_28F320J3A: |
||||
info->flash_id += FLASH_28F320J3A; |
||||
info->sector_count = 32; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
|
||||
case (FPW) INTEL_ID_28F640J3A: |
||||
info->flash_id += FLASH_28F640J3A; |
||||
info->sector_count = 64; |
||||
info->size = 0x00800000; |
||||
break; /* => 8 MB */ |
||||
|
||||
case (FPW) INTEL_ID_28F128J3A: |
||||
info->flash_id += FLASH_28F128J3A; |
||||
info->sector_count = 128; |
||||
info->size = 0x01000000; |
||||
break; /* => 16 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
break; |
||||
} |
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) { |
||||
printf ("** ERROR: sector count %d > max (%d) **\n", |
||||
info->sector_count, CFG_MAX_FLASH_SECT); |
||||
info->sector_count = CFG_MAX_FLASH_SECT; |
||||
} |
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
int flag, prot, sect; |
||||
ulong type, start, now, last; |
||||
int rcode = 0; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK); |
||||
if ((type != FLASH_MAN_INTEL)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
FPWV *addr = (FPWV *) (info->start[sect]); |
||||
FPW status; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */ |
||||
*addr = (FPW) 0x00200020; /* erase setup */ |
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
*addr = (FPW) 0x00B000B0; /* suspend erase */ |
||||
*addr = (FPW) 0x00FF00FF; /* reset to read mode */ |
||||
rcode = 1; |
||||
break; |
||||
} |
||||
|
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
*addr = (FPW) 0x00FF00FF; /* reset to read mode */ |
||||
} |
||||
} |
||||
printf (" done\n"); |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
* 4 - Flash not identified |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp; |
||||
FPW data; |
||||
|
||||
int i, l, rc, port_width; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return 4; |
||||
} |
||||
/* get lower word aligned address */ |
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
wp = (addr & ~1); |
||||
port_width = 2; |
||||
#elif defined(FLASH_PORT_WIDTH32) |
||||
wp = (addr & ~3); |
||||
port_width = 4; |
||||
#else |
||||
wp = addr; |
||||
port_width = 1; |
||||
#endif |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
for (; i < port_width && cnt > 0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
if ((rc = write_data (info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= port_width) { |
||||
data = 0; |
||||
for (i = 0; i < port_width; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_data (info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
cnt -= port_width; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
return (write_data (info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data) |
||||
{ |
||||
FPWV *addr = (FPWV *) dest; |
||||
ulong status; |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
*addr = (FPW) 0x00400040; /* write setup */ |
||||
*addr = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
start = get_timer (0); |
||||
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { |
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (1); |
||||
} |
||||
} |
||||
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
|
||||
return (0); |
||||
} |
@ -0,0 +1,318 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Heiko Schocher, DENX Software Engineering, <hs@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc8260.h> |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ |
||||
/* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ |
||||
/* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ |
||||
/* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ |
||||
/* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ |
||||
/* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ |
||||
/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ |
||||
#if defined(CONFIG_SOFT_I2C) |
||||
/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ |
||||
/* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ |
||||
#else /* normal I/O port pins */ |
||||
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ |
||||
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ |
||||
#endif |
||||
/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ |
||||
/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ |
||||
/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ |
||||
/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ |
||||
/* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ |
||||
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ |
||||
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ |
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ |
||||
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ |
||||
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ |
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ |
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ |
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ |
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ |
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ |
||||
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ |
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ |
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ |
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ |
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ |
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ |
||||
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ |
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ |
||||
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ |
||||
/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ |
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ |
||||
/* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ |
||||
/* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ |
||||
/* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ |
||||
/* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ |
||||
/* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ |
||||
/* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ |
||||
/* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ |
||||
/* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ |
||||
/* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ |
||||
#if defined(CONFIG_HARD_I2C) |
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ |
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ |
||||
#else /* normal I/O port pins */ |
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ |
||||
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ |
||||
#endif |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ |
||||
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* Check Board Identity:
|
||||
*/ |
||||
int checkboard (void) |
||||
{ |
||||
puts ("Board: IDS 8247\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
|
||||
* |
||||
* This routine performs standard 8260 initialization sequence |
||||
* and calculates the available memory size. It may be called |
||||
* several times to try different SDRAM configurations on both |
||||
* 60x and local buses. |
||||
*/ |
||||
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, |
||||
ulong orx, volatile uchar * base) |
||||
{ |
||||
volatile uchar c = 0xff; |
||||
volatile uint *sdmr_ptr; |
||||
volatile uint *orx_ptr; |
||||
ulong maxsize, size; |
||||
int i; |
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be |
||||
* mapped by the controller. That means, that the initial mapping has |
||||
* to be (at least) twice as large as the maximum expected size. |
||||
*/ |
||||
maxsize = (1 + (~orx | 0x7fff)) / 2; |
||||
|
||||
sdmr_ptr = &memctl->memc_psdmr; |
||||
orx_ptr = &memctl->memc_or2; |
||||
|
||||
*orx_ptr = orx; |
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): |
||||
* |
||||
* "At system reset, initialization software must set up the |
||||
* programmable parameters in the memory controller banks registers |
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured, |
||||
* system software should execute the following initialization sequence |
||||
* for each SDRAM device. |
||||
* |
||||
* 1. Issue a PRECHARGE-ALL-BANKS command |
||||
* 2. Issue eight CBR REFRESH commands |
||||
* 3. Issue a MODE-SET command to initialize the mode register |
||||
* |
||||
* The initial commands are executed by setting P/LSDMR[OP] and |
||||
* accessing the SDRAM with a single-byte transaction." |
||||
* |
||||
* The appropriate BRx/ORx registers have already been set when we |
||||
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. |
||||
*/ |
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_PREA; |
||||
*base = c; |
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_CBRR; |
||||
for (i = 0; i < 8; i++) |
||||
*base = c; |
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_MRW; |
||||
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ |
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; |
||||
*base = c; |
||||
|
||||
size = get_ram_size((long *)base, maxsize); |
||||
*orx_ptr = orx | ~(size - 1); |
||||
|
||||
return (size); |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8260_t *memctl = &immap->im_memctl; |
||||
|
||||
long psize, lsize; |
||||
|
||||
psize = 16 * 1024 * 1024; |
||||
lsize = 0; |
||||
|
||||
memctl->memc_psrt = CFG_PSRT; |
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
/* 60x SDRAM setup:
|
||||
*/ |
||||
psize = try_init (memctl, CFG_PSDMR, CFG_OR2, |
||||
(uchar *) CFG_SDRAM_BASE); |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
icache_enable (); |
||||
|
||||
return (psize); |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_flashstart = 0xff800000; |
||||
} |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
extern ulong |
||||
nand_probe (ulong physadr); |
||||
|
||||
void |
||||
nand_init (void) |
||||
{ |
||||
ulong totlen = 0; |
||||
|
||||
debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); |
||||
totlen += nand_probe (CFG_NAND0_BASE); |
||||
|
||||
printf ("%4lu MB\n", totlen >>20); |
||||
} |
||||
|
||||
#endif /* CFG_CMD_NAND */ |
@ -0,0 +1,123 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Heiko Schocher, DENX Software Engineering, <hs@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8260/start.o (.text) |
||||
*(.text) |
||||
common/environment.o(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,524 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Heiko Schocher, DENX Software Engineering, <hs@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
||||
#define CONFIG_MPC8272_FAMILY 1 |
||||
#define CONFIG_IDS8247 1 |
||||
#define CPU_ID_STR "MPC8247" |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw " \
|
||||
"console=ttyS0,115200\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/IDS8247/uImage\0" \
|
||||
"kernel_addr=ff800000\0" \
|
||||
"ramdisk_addr=ffa00000\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
|
||||
#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00000080) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00000080) |
||||
#define I2C_READ ((iop->pdat & 0x00000080) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ |
||||
else iop->pdat &= ~0x00000080 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ |
||||
else iop->pdat &= ~0x00000100 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#if 0 |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
#define CONFIG_I2C_X |
||||
#endif |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* use the extern UART for the console |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
|
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
|
||||
#define CFG_NS16550_CLK 14745600 |
||||
|
||||
#define CFG_UART_BASE 0xE0000000 |
||||
#define CFG_UART_SIZE 0x10000 |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000) |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
* |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_SNTP ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk |
||||
* The main FLASH is whichever is connected to *CS0. |
||||
*/ |
||||
#define CFG_FLASH0_BASE 0xFFF00000 |
||||
#define CFG_FLASH0_SIZE 8 |
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/ |
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
/* Environment in flash */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000) |
||||
#define CFG_ENV_SIZE 0x20000 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
|
||||
#define CFG_NAND0_BASE 0xE1000000 |
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define SECTORSIZE 512 |
||||
#define NAND_NO_RB |
||||
|
||||
#define ADDR_COLUMN 1 |
||||
#define ADDR_PAGE 2 |
||||
#define ADDR_COLUMN_PAGE 3 |
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00 |
||||
#define NAND_MAX_FLOORS 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
|
||||
#define NAND_DISABLE_CE(nand) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
|
||||
} while(0) |
||||
|
||||
#define NAND_ENABLE_CE(nand) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_CLRALE(nandptr) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)nandptr) + 0x8) = 0; \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_SETALE(nandptr) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)nandptr) + 0x9) = 0; \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_CLRCLE(nandptr) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)nandptr) + 0x8) = 0; \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_SETCLE(nandptr) do \ |
||||
{ \
|
||||
*(((volatile __u8 *)nandptr) + 0xa) = 0; \
|
||||
} while(0) |
||||
|
||||
#ifdef NAND_NO_RB |
||||
/* constant delay (see also tR in the datasheet) */ |
||||
#define NAND_WAIT_READY(nand) do { \ |
||||
udelay(12); \
|
||||
} while (0) |
||||
#else |
||||
/* use the R/B pin */ |
||||
#endif |
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) |
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) |
||||
|
||||
#endif /* CFG_CMD_NAND */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
|
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) |
||||
#define CFG_HID0_FINAL 0 |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_BCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR (0x00000028 | SCCR_DFBRG01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 16 bit FLASH |
||||
* 1 60x GPCM 8 bit NAND |
||||
* 2 60x SDRAM 32 bit SDRAM |
||||
* 3 60x GPCM 8 bit UART |
||||
* |
||||
*/ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ |
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2] |
||||
*/ |
||||
#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ |
||||
|
||||
#define CFG_MPTPR 0x6600 |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MRS_OFFS 0x00000110 |
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_SCY_6_CLK ) |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
/* Bank 1 - NAND Flash
|
||||
*/ |
||||
#define CFG_NAND_BASE CFG_NAND0_BASE |
||||
#define CFG_NAND_SIZE 0x8000 |
||||
|
||||
#define CFG_OR_TIMING_NAND 0x000036 |
||||
|
||||
#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND ) |
||||
#endif |
||||
|
||||
/* Bank 2 - 60x bus SDRAM
|
||||
*/ |
||||
#define CFG_PSRT 0x20 |
||||
#define CFG_LSRT 0x20 |
||||
|
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2 |
||||
|
||||
|
||||
/* SDRAM initialization values
|
||||
*/ |
||||
#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A10 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ |
||||
PSDMR_BSMA_A15_A17 |\
|
||||
PSDMR_SDA10_PBI0_A11 |\
|
||||
PSDMR_RFRC_5_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_2C |\
|
||||
PSDMR_WRC_3C |\
|
||||
PSDMR_CL_3) |
||||
|
||||
/* Bank 3 - UART
|
||||
*/ |
||||
|
||||
#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
||||
#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue