This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
Masahiro Yamada
10 years ago
committed by
Tom Rini
parent
1521cdc530
commit
9ed3246e19
@ -1,59 +0,0 @@ |
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/*
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* Copyright (c) 2010, Applied Micro Circuits Corporation |
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* Author: Tirumala R Marri <tmarri@apm.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _APM821XX_H_ |
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#define _APM821XX_H_ |
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ |
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/* Memory mapped registers */ |
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#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 |
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) |
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) |
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) |
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#define SDR0_SRST0_DMC 0x00200000 |
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#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ |
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/* AHB config. */ |
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#define AHB_TOP 0xA4 |
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#define AHB_BOT 0xA5 |
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/* clk divisors */ |
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#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
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#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ |
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#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ |
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#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ |
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#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ |
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#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ |
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#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ |
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#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
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#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ |
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/*
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+ * Clocking Controller |
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+ */ |
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#define CPR0_CLKUPD 0x0020 |
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#define CPR0_PLLC 0x0040 |
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#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) |
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#define CPR0_PLLD 0x0060 |
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#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) |
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#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) |
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#define CPR0_CPUD 0x0080 |
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#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) |
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#define CPR0_PLB2D 0x00a0 |
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#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) |
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#define CPR0_OPBD 0x00c0 |
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#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) |
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#define CPR0_PERD 0x00e0 |
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#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) |
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#define CPR0_DDR2D 0x0100 |
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#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) |
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#define CLK_ICFG 0x0140 |
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#endif /* _APM821XX_H_ */ |
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@ -1,12 +0,0 @@ |
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if TARGET_BLUESTONE |
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config SYS_BOARD |
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default "bluestone" |
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config SYS_VENDOR |
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default "amcc" |
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config SYS_CONFIG_NAME |
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default "bluestone" |
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endif |
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@ -1,6 +0,0 @@ |
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BLUESTONE BOARD |
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#M: Tirumala Marri <tmarri@apm.com> |
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S: Orphan (since 2014-03) |
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F: board/amcc/bluestone/ |
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F: include/configs/bluestone.h |
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F: configs/bluestone_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# Copyright (c) 2010, Applied Micro Circuits Corporation
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# Author: Tirumala R Marri <tmarri@apm.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := bluestone.o
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extra-y += init.o
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@ -1,99 +0,0 @@ |
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/*
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* Bluestone board support |
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* |
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* Copyright (c) 2010, Applied Micro Circuits Corporation |
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* Author: Tirumala R Marri <tmarri@apm.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/apm821xx.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <i2c.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <asm/mmu.h> |
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#include <asm/ppc4xx-gpio.h> |
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int board_early_init_f(void) |
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{ |
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/*
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* Setup the interrupt controller polarities, triggers, etc. |
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*/ |
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mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC0ER, 0x00000000); /* disable all */ |
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ |
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mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ |
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ |
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC1ER, 0x00000000); /* disable all */ |
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */ |
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ |
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ |
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC2ER, 0x00000000); /* disable all */ |
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */ |
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ |
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ |
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC3ER, 0x00000000); /* disable all */ |
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */ |
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ |
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mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ |
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mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
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/*
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* Configure PFC (Pin Function Control) registers |
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* UART0: 2 pins |
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*/ |
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mtsdr(SDR0_PFC1, 0x0000000); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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char buf[64]; |
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int i = getenv_f("serial#", buf, sizeof(buf)); |
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puts("Board: Bluestone Evaluation Board"); |
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if (i > 0) { |
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puts(", serial# "); |
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puts(buf); |
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} |
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putc('\n'); |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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u32 sdr0_srst1 = 0; |
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/* Setup PLB4-AHB bridge based on the system address map */ |
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mtdcr(AHB_TOP, 0x8000004B); |
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mtdcr(AHB_BOT, 0x8000004B); |
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/*
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* The AHB Bridge core is held in reset after power-on or reset |
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* so enable it now |
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*/ |
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mfsdr(SDR0_SRST1, sdr0_srst1); |
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sdr0_srst1 &= ~SDR0_SRST1_AHB; |
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mtsdr(SDR0_SRST1, sdr0_srst1); |
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return 0; |
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} |
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@ -1,18 +0,0 @@ |
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#
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# Copyright (c) 2010, Applied Micro Circuits Corporation
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# Author: Tirumala R Marri <tmarri@apm.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Applied Micro APM821XX Evaluation board.
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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@ -1,45 +0,0 @@ |
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/* |
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* Copyright (c) 2010, Applied Micro Circuits Corporation |
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* Author: Tirumala R Marri <tmarri@apm.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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#include <asm/mmu.h> |
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#include <asm/ppc4xx.h> |
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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.globl tlbtab
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tlbtab: |
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tlbtab_start |
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/* TLB 0 */ |
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, |
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4, AC_RWX | SA_G) |
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, |
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0, AC_RWX | SA_G) |
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/* TLB-entry for OCM */ |
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, |
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AC_RWX | SA_I) |
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/* TLB-entry for Local Configuration registers => peripherals */ |
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, |
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CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) |
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tlbtab_end |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_4xx=y |
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CONFIG_TARGET_BLUESTONE=y |
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@ -1,168 +0,0 @@ |
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/*
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* bluestone.h - configuration for Bluestone (APM821XX) |
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* |
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* Copyright (c) 2010, Applied Micro Circuits Corporation |
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* Author: Tirumala R Marri <tmarri@apm.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_APM821XX 1 /* APM821XX series */ |
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#define CONFIG_HOSTNAME bluestone |
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#define CONFIG_440 1 |
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#ifndef CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
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#endif |
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/*
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* Include common defines/options for all AMCC eval boards |
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*/ |
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#include "amcc-common.h" |
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#define CONFIG_SYS_CLK_FREQ 50000000 |
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#define CONFIG_BOARD_TYPES 1 /* support board types */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
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/*
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* Base addresses -- Note these are effective addresses where the |
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* actual resources get mapped (not physical addresses) |
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*/ |
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/* EBC stuff */ |
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/* later mapped to this addr */ |
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#define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
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#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ |
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/* EBC Boot Space: 0xFF000000 */ |
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 |
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#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ |
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#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ |
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#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ |
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#define CONFIG_SYS_SRAM_SIZE (256 << 10) |
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/*
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* Initial RAM & stack pointer (placed in OCM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
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#define CONFIG_SYS_GBL_DATA_OFFSET \ |
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*
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* Environment |
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*/ |
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/*
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* Define here the location of the environment variables (FLASH). |
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*/ |
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
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/*
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* FLASH related |
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*/ |
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT |
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
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/* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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/* max number of sectors on one chip */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 80 |
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/* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
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/* Timeout for Flash Write (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
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/* use buffered writes (20x faster) */ |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
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/* print 'E' for empty sector on flinfo */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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#endif /* CONFIG_ENV_IS_IN_FLASH */ |
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/* SDRAM */ |
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
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#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ |
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ |
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#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ |
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#define CONFIG_DDR_ECC 1 /* with ECC support */ |
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/*
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* Serial Port |
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*/ |
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
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/*
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* I2C |
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*/ |
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
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#define CONFIG_SYS_I2C_MULTI_EEPROMS |
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ |
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/* I2C bootstrap EEPROM */ |
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 |
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 |
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 |
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/*
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* Ethernet |
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*/ |
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#define CONFIG_IBM_EMAC4_V4 1 |
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#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII |
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#define CONFIG_HAS_ETH0 |
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/* PHY address, See schematics */ |
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#define CONFIG_PHY_ADDR 0x1f |
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/* reset phy upon startup */ |
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#define CONFIG_PHY_RESET 1 |
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/* Include GbE speed/duplex detection */ |
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#define CONFIG_PHY_GIGE 1 |
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#define CONFIG_PHY_DYNAMIC_ANEG 1 |
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/*
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* External Bus Controller (EBC) Setup |
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**/ |
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#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ |
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EBC_CFG_PTD_ENABLE | \
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EBC_CFG_RTC_2048PERCLK | \
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EBC_CFG_ATC_HI | \
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EBC_CFG_DTC_HI | \
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EBC_CFG_CTC_HI | \
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EBC_CFG_OEO_PREVIOUS) |
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/* NOR Flash */ |
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
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EBC_BXAP_TWT_ENCODE(64) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(1) | \
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EBC_BXAP_OEN_ENCODE(2) | \
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EBC_BXAP_WBN_ENCODE(2) | \
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EBC_BXAP_WBF_ENCODE(2) | \
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EBC_BXAP_TH_ENCODE(7) | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED) |
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/* Peripheral Bank Configuration Register - EBC_BxCR */ |
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#define CONFIG_SYS_EBC_PB0CR \ |
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(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_8BIT) |
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|
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#endif /* __CONFIG_H */ |
||||
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