Albert ARIBAUD
11 years ago
commit
9ed887caec
@ -1,28 +0,0 @@ |
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := mx6qsabrelite.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,832 +0,0 @@ |
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/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6q_pins.h> |
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#include <asm/errno.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <malloc.h> |
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#include <micrel.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <linux/fb.h> |
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#include <ipu_pixfmt.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mxc_hdmi.h> |
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#include <i2c.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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iomux_v3_cfg_t const uart1_pads[] = { |
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MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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iomux_v3_cfg_t const uart2_pads[] = { |
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MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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/* I2C1, SGTL5000 */ |
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struct i2c_pads_info i2c_pad_info0 = { |
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.scl = { |
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.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, |
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.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, |
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.gp = IMX_GPIO_NR(3, 21) |
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}, |
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.sda = { |
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.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, |
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.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, |
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.gp = IMX_GPIO_NR(3, 28) |
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} |
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}; |
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/* I2C2 Camera, MIPI */ |
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struct i2c_pads_info i2c_pad_info1 = { |
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.scl = { |
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, |
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, |
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.gp = IMX_GPIO_NR(4, 12) |
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}, |
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.sda = { |
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, |
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, |
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.gp = IMX_GPIO_NR(4, 13) |
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} |
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}; |
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/* I2C3, J15 - RGB connector */ |
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struct i2c_pads_info i2c_pad_info2 = { |
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.scl = { |
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.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, |
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.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, |
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.gp = IMX_GPIO_NR(1, 5) |
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}, |
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.sda = { |
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.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, |
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.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, |
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.gp = IMX_GPIO_NR(7, 11) |
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} |
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}; |
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iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const usdhc4_pads[] = { |
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t const enet_pads1[] = { |
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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/* pin 35 - 1 (PHY_AD2) on reset */ |
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MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 32 - 1 - (MODE0) all */ |
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MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 31 - 1 - (MODE1) all */ |
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MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 28 - 1 - (MODE2) all */ |
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MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 27 - 1 - (MODE3) all */ |
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MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ |
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MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* pin 42 PHY nRST */ |
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MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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iomux_v3_cfg_t const enet_pads2[] = { |
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MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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}; |
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/* Button assignments for J14 */ |
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static iomux_v3_cfg_t const button_pads[] = { |
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/* Menu */ |
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MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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/* Back */ |
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MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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/* Labelled Search (mapped to Power under Android) */ |
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MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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/* Home */ |
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MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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/* Volume Down */ |
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MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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/* Volume Up */ |
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MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), |
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}; |
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static void setup_iomux_enet(void) |
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{ |
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gpio_direction_output(IMX_GPIO_NR(3, 23), 0); |
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gpio_direction_output(IMX_GPIO_NR(6, 30), 1); |
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gpio_direction_output(IMX_GPIO_NR(6, 25), 1); |
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gpio_direction_output(IMX_GPIO_NR(6, 27), 1); |
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gpio_direction_output(IMX_GPIO_NR(6, 28), 1); |
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gpio_direction_output(IMX_GPIO_NR(6, 29), 1); |
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imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); |
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gpio_direction_output(IMX_GPIO_NR(6, 24), 1); |
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/* Need delay 10ms according to KSZ9021 spec */ |
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udelay(1000 * 10); |
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gpio_set_value(IMX_GPIO_NR(3, 23), 1); |
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imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); |
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} |
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iomux_v3_cfg_t const usb_pads[] = { |
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MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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} |
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#ifdef CONFIG_USB_EHCI_MX6 |
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int board_ehci_hcd_init(int port) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); |
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/* Reset USB hub */ |
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gpio_direction_output(IMX_GPIO_NR(7, 12), 0); |
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mdelay(2); |
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gpio_set_value(IMX_GPIO_NR(7, 12), 1); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg usdhc_cfg[2] = { |
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{USDHC3_BASE_ADDR}, |
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{USDHC4_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret; |
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if (cfg->esdhc_base == USDHC3_BASE_ADDR) { |
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gpio_direction_input(IMX_GPIO_NR(7, 0)); |
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ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); |
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} else { |
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gpio_direction_input(IMX_GPIO_NR(2, 6)); |
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ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); |
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} |
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return ret; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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s32 status = 0; |
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u32 index = 0; |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
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usdhc_cfg[0].max_bus_width = 4; |
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usdhc_cfg[1].max_bus_width = 4; |
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { |
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switch (index) { |
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case 0: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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break; |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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break; |
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default: |
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printf("Warning: you configured more USDHC controllers" |
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"(%d) then supported by the board (%d)\n", |
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index + 1, CONFIG_SYS_FSL_USDHC_NUM); |
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return status; |
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} |
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); |
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} |
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return status; |
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} |
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#endif |
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#ifdef CONFIG_MXC_SPI |
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iomux_v3_cfg_t const ecspi1_pads[] = { |
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/* SS1 */ |
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MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
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}; |
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void setup_spi(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, |
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ARRAY_SIZE(ecspi1_pads)); |
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} |
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#endif |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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/* min rx data delay */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); |
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/* min tx data delay */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); |
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/* max rx/tx clock delay, min rx/tx control */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); |
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if (phydev->drv->config) |
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phydev->drv->config(phydev); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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uint32_t base = IMX_FEC_BASE; |
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struct mii_dev *bus = NULL; |
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struct phy_device *phydev = NULL; |
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int ret; |
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setup_iomux_enet(); |
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#ifdef CONFIG_FEC_MXC |
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bus = fec_get_miibus(base, -1); |
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if (!bus) |
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return 0; |
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/* scan phy 4,5,6,7 */ |
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phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); |
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if (!phydev) { |
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free(bus); |
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return 0; |
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} |
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printf("using phy at %d\n", phydev->addr); |
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ret = fec_probe(bis, -1, base, bus, phydev); |
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if (ret) { |
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printf("FEC MXC: %s:failed\n", __func__); |
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free(phydev); |
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free(bus); |
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} |
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#endif |
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return 0; |
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} |
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static void setup_buttons(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(button_pads, |
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ARRAY_SIZE(button_pads)); |
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} |
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#ifdef CONFIG_CMD_SATA |
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int setup_sata(void) |
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{ |
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struct iomuxc_base_regs *const iomuxc_regs |
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= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; |
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int ret = enable_sata_clock(); |
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if (ret) |
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return ret; |
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clrsetbits_le32(&iomuxc_regs->gpr[13], |
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IOMUXC_GPR13_SATA_MASK, |
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IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB |
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|IOMUXC_GPR13_SATA_PHY_7_SATA2M |
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|IOMUXC_GPR13_SATA_SPEED_3G |
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|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) |
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|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED |
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|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 |
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|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB |
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|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V |
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|IOMUXC_GPR13_SATA_PHY_1_SLOW); |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_VIDEO_IPUV3) |
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static iomux_v3_cfg_t const backlight_pads[] = { |
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/* Backlight on RGB connector: J15 */ |
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MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) |
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/* Backlight on LVDS connector: J6 */ |
||||
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const rgb_pads[] = { |
||||
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, |
||||
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, |
||||
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, |
||||
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, |
||||
MX6_PAD_DI0_PIN4__GPIO_4_20, |
||||
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, |
||||
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, |
||||
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, |
||||
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, |
||||
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, |
||||
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, |
||||
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, |
||||
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, |
||||
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, |
||||
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, |
||||
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, |
||||
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, |
||||
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, |
||||
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, |
||||
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, |
||||
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, |
||||
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, |
||||
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, |
||||
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, |
||||
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, |
||||
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, |
||||
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, |
||||
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, |
||||
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, |
||||
}; |
||||
|
||||
struct display_info_t { |
||||
int bus; |
||||
int addr; |
||||
int pixfmt; |
||||
int (*detect)(struct display_info_t const *dev); |
||||
void (*enable)(struct display_info_t const *dev); |
||||
struct fb_videomode mode; |
||||
}; |
||||
|
||||
|
||||
static int detect_hdmi(struct display_info_t const *dev) |
||||
{ |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; |
||||
} |
||||
|
||||
static void enable_hdmi(struct display_info_t const *dev) |
||||
{ |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
u8 reg; |
||||
printf("%s: setup HDMI monitor\n", __func__); |
||||
reg = readb(&hdmi->phy_conf0); |
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
|
||||
udelay(3000); |
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
udelay(3000); |
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
||||
writeb(reg, &hdmi->phy_conf0); |
||||
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
||||
} |
||||
|
||||
static int detect_i2c(struct display_info_t const *dev) |
||||
{ |
||||
return ((0 == i2c_set_bus_num(dev->bus)) |
||||
&& |
||||
(0 == i2c_probe(dev->addr))); |
||||
} |
||||
|
||||
static void enable_lvds(struct display_info_t const *dev) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *) |
||||
IOMUXC_BASE_ADDR; |
||||
u32 reg = readl(&iomux->gpr[2]); |
||||
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; |
||||
writel(reg, &iomux->gpr[2]); |
||||
gpio_direction_output(LVDS_BACKLIGHT_GP, 1); |
||||
} |
||||
|
||||
static void enable_rgb(struct display_info_t const *dev) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
rgb_pads, |
||||
ARRAY_SIZE(rgb_pads)); |
||||
gpio_direction_output(RGB_BACKLIGHT_GP, 1); |
||||
} |
||||
|
||||
static struct display_info_t const displays[] = {{ |
||||
.bus = -1, |
||||
.addr = 0, |
||||
.pixfmt = IPU_PIX_FMT_RGB24, |
||||
.detect = detect_hdmi, |
||||
.enable = enable_hdmi, |
||||
.mode = { |
||||
.name = "HDMI", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 768, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x4, |
||||
.pixfmt = IPU_PIX_FMT_LVDS666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_lvds, |
||||
.mode = { |
||||
.name = "Hannstar-XGA", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 768, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x38, |
||||
.pixfmt = IPU_PIX_FMT_LVDS666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_lvds, |
||||
.mode = { |
||||
.name = "wsvga-lvds", |
||||
.refresh = 60, |
||||
.xres = 1024, |
||||
.yres = 600, |
||||
.pixclock = 15385, |
||||
.left_margin = 220, |
||||
.right_margin = 40, |
||||
.upper_margin = 21, |
||||
.lower_margin = 7, |
||||
.hsync_len = 60, |
||||
.vsync_len = 10, |
||||
.sync = FB_SYNC_EXT, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} }, { |
||||
.bus = 2, |
||||
.addr = 0x48, |
||||
.pixfmt = IPU_PIX_FMT_RGB666, |
||||
.detect = detect_i2c, |
||||
.enable = enable_rgb, |
||||
.mode = { |
||||
.name = "wvga-rgb", |
||||
.refresh = 57, |
||||
.xres = 800, |
||||
.yres = 480, |
||||
.pixclock = 37037, |
||||
.left_margin = 40, |
||||
.right_margin = 60, |
||||
.upper_margin = 10, |
||||
.lower_margin = 10, |
||||
.hsync_len = 20, |
||||
.vsync_len = 10, |
||||
.sync = 0, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
} } }; |
||||
|
||||
int board_video_skip(void) |
||||
{ |
||||
int i; |
||||
int ret; |
||||
char const *panel = getenv("panel"); |
||||
if (!panel) { |
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) { |
||||
struct display_info_t const *dev = displays+i; |
||||
if (dev->detect(dev)) { |
||||
panel = dev->mode.name; |
||||
printf("auto-detected panel %s\n", panel); |
||||
break; |
||||
} |
||||
} |
||||
if (!panel) { |
||||
panel = displays[0].mode.name; |
||||
printf("No panel detected: default to %s\n", panel); |
||||
} |
||||
} else { |
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) { |
||||
if (!strcmp(panel, displays[i].mode.name)) |
||||
break; |
||||
} |
||||
} |
||||
if (i < ARRAY_SIZE(displays)) { |
||||
ret = ipuv3_fb_init(&displays[i].mode, 0, |
||||
displays[i].pixfmt); |
||||
if (!ret) { |
||||
displays[i].enable(displays+i); |
||||
printf("Display: %s (%ux%u)\n", |
||||
displays[i].mode.name, |
||||
displays[i].mode.xres, |
||||
displays[i].mode.yres); |
||||
} else |
||||
printf("LCD %s cannot be configured: %d\n", |
||||
displays[i].mode.name, ret); |
||||
} else { |
||||
printf("unsupported panel %s\n", panel); |
||||
ret = -EINVAL; |
||||
} |
||||
return (0 != ret); |
||||
} |
||||
|
||||
static void setup_display(void) |
||||
{ |
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
||||
|
||||
int reg; |
||||
|
||||
/* Turn on LDB0,IPU,IPU DI0 clocks */ |
||||
reg = __raw_readl(&mxc_ccm->CCGR3); |
||||
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET |
||||
|MXC_CCM_CCGR3_LDB_DI0_MASK; |
||||
writel(reg, &mxc_ccm->CCGR3); |
||||
|
||||
/* Turn on HDMI PHY clock */ |
||||
reg = __raw_readl(&mxc_ccm->CCGR2); |
||||
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK |
||||
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
||||
writel(reg, &mxc_ccm->CCGR2); |
||||
|
||||
/* clear HDMI PHY reset */ |
||||
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ |
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); |
||||
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); |
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */ |
||||
reg = readl(&mxc_ccm->cs2cdr); |
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
||||
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
||||
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
||||
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
||||
writel(reg, &mxc_ccm->cs2cdr); |
||||
|
||||
reg = readl(&mxc_ccm->cscmr2); |
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; |
||||
writel(reg, &mxc_ccm->cscmr2); |
||||
|
||||
reg = readl(&mxc_ccm->chsccdr); |
||||
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) |
||||
|(CHSCCDR_PODF_DIVIDE_BY_3 |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
||||
|(CHSCCDR_IPU_PRE_CLK_540M_PFD |
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
||||
writel(reg, &mxc_ccm->chsccdr); |
||||
|
||||
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
||||
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
||||
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
||||
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
||||
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
||||
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
||||
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
||||
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
||||
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; |
||||
writel(reg, &iomux->gpr[2]); |
||||
|
||||
reg = readl(&iomux->gpr[3]); |
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
||||
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
||||
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); |
||||
writel(reg, &iomux->gpr[3]); |
||||
|
||||
/* backlights off until needed */ |
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads, |
||||
ARRAY_SIZE(backlight_pads)); |
||||
gpio_direction_input(LVDS_BACKLIGHT_GP); |
||||
gpio_direction_input(RGB_BACKLIGHT_GP); |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
setup_buttons(); |
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3) |
||||
setup_display(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Do not overwrite the console |
||||
* Use always serial for U-Boot console |
||||
*/ |
||||
int overwrite_console(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
#ifdef CONFIG_MXC_SPI |
||||
setup_spi(); |
||||
#endif |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); |
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
||||
|
||||
#ifdef CONFIG_CMD_SATA |
||||
setup_sata(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: MX6Q-Sabre Lite\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct button_key { |
||||
char const *name; |
||||
unsigned gpnum; |
||||
char ident; |
||||
}; |
||||
|
||||
static struct button_key const buttons[] = { |
||||
{"back", IMX_GPIO_NR(2, 2), 'B'}, |
||||
{"home", IMX_GPIO_NR(2, 4), 'H'}, |
||||
{"menu", IMX_GPIO_NR(2, 1), 'M'}, |
||||
{"search", IMX_GPIO_NR(2, 3), 'S'}, |
||||
{"volup", IMX_GPIO_NR(7, 13), 'V'}, |
||||
{"voldown", IMX_GPIO_NR(4, 5), 'v'}, |
||||
}; |
||||
|
||||
/*
|
||||
* generate a null-terminated string containing the buttons pressed |
||||
* returns number of keys pressed |
||||
*/ |
||||
static int read_keys(char *buf) |
||||
{ |
||||
int i, numpressed = 0; |
||||
for (i = 0; i < ARRAY_SIZE(buttons); i++) { |
||||
if (!gpio_get_value(buttons[i].gpnum)) |
||||
buf[numpressed++] = buttons[i].ident; |
||||
} |
||||
buf[numpressed] = '\0'; |
||||
return numpressed; |
||||
} |
||||
|
||||
static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
char envvalue[ARRAY_SIZE(buttons)+1]; |
||||
int numpressed = read_keys(envvalue); |
||||
setenv("keybd", envvalue); |
||||
return numpressed == 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
kbd, 1, 1, do_kbd, |
||||
"Tests for keypresses, sets 'keybd' environment variable", |
||||
"Returns 0 (true) to shell if key is pressed." |
||||
); |
||||
|
||||
#ifdef CONFIG_PREBOOT |
||||
static char const kbd_magic_prefix[] = "key_magic"; |
||||
static char const kbd_command_prefix[] = "key_cmd"; |
||||
|
||||
static void preboot_keys(void) |
||||
{ |
||||
int numpressed; |
||||
char keypress[ARRAY_SIZE(buttons)+1]; |
||||
numpressed = read_keys(keypress); |
||||
if (numpressed) { |
||||
char *kbd_magic_keys = getenv("magic_keys"); |
||||
char *suffix; |
||||
/*
|
||||
* loop over all magic keys |
||||
*/ |
||||
for (suffix = kbd_magic_keys; *suffix; ++suffix) { |
||||
char *keys; |
||||
char magic[sizeof(kbd_magic_prefix) + 1]; |
||||
sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); |
||||
keys = getenv(magic); |
||||
if (keys) { |
||||
if (!strcmp(keys, keypress)) |
||||
break; |
||||
} |
||||
} |
||||
if (*suffix) { |
||||
char cmd_name[sizeof(kbd_command_prefix) + 1]; |
||||
char *cmd; |
||||
sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); |
||||
cmd = getenv(cmd_name); |
||||
if (cmd) { |
||||
setenv("preboot", cmd); |
||||
return; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
||||
{"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_PREBOOT |
||||
preboot_keys(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
return 0; |
||||
} |
||||
@ -1,284 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Freescale i.MX6Q Sabre Lite board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_MX6 |
||||
#define CONFIG_MX6Q |
||||
|
||||
#include "mx6_common.h" |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define CONFIG_MACH_TYPE 3769 |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
#define CONFIG_CMD_FUSE |
||||
#ifdef CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
#endif |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
|
||||
#define CONFIG_CMD_SF |
||||
#ifdef CONFIG_CMD_SF |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SST |
||||
#define CONFIG_MXC_SPI |
||||
#define CONFIG_SF_DEFAULT_BUS 0 |
||||
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) |
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000 |
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
||||
#endif |
||||
|
||||
/* I2C Configs */ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_MXC |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_CMD_SATA |
||||
/*
|
||||
* SATA Configs |
||||
*/ |
||||
#ifdef CONFIG_CMD_SATA |
||||
#define CONFIG_DWC_AHSATA |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0 |
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_LIBATA |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 6 |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX6 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
#define CONFIG_USB_ETHER_SMSC95XX |
||||
#define CONFIG_MXC_USB_PORT 1 |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
|
||||
/* Miscellaneous commands */ |
||||
#define CONFIG_CMD_BMODE |
||||
|
||||
/* Framebuffer and LCD */ |
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_VIDEO_IPUV3 |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_IPUV3_CLK 260000000 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Command definition */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_BOOTDELAY 1 |
||||
|
||||
#define CONFIG_PREBOOT "" |
||||
|
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc1\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx6q-sabrelite.dtb\0" \
|
||||
"fdt_addr=0x11000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > " |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000 |
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
/* #define CONFIG_ENV_IS_IN_SPI_FLASH */ |
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC) |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) |
||||
#define CONFIG_ENV_OFFSET (768 * 1024) |
||||
#define CONFIG_ENV_SECT_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS |
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS |
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE |
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
||||
#endif |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,191 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __CONFIGS_MXS_H__ |
||||
#define __CONFIGS_MXS_H__ |
||||
|
||||
/*
|
||||
* Includes |
||||
*/ |
||||
|
||||
#if defined(CONFIG_MX23) && defined(CONFIG_MX28) |
||||
#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! |
||||
#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) |
||||
#error Select one of CONFIG_MX23 or CONFIG_MX28 ! |
||||
#endif |
||||
|
||||
#include <asm/arch/regs-base.h> |
||||
|
||||
#if defined(CONFIG_MX23) |
||||
#include <asm/arch/iomux-mx23.h> |
||||
#elif defined(CONFIG_MX28) |
||||
#include <asm/arch/iomux-mx28.h> |
||||
#endif |
||||
|
||||
/*
|
||||
* CPU specifics |
||||
*/ |
||||
|
||||
/* Ticks per second */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* MXS uses FDT */ |
||||
#define CONFIG_OF_LIBFDT |
||||
|
||||
/* Startup hooks */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_ARCH_MISC_INIT |
||||
|
||||
/* SPL */ |
||||
#define CONFIG_SPL |
||||
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE |
||||
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" |
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_GPIO_SUPPORT |
||||
|
||||
/* Memory sizes */ |
||||
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ |
||||
|
||||
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 |
||||
#if defined(CONFIG_MX23) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) |
||||
#elif defined(CONFIG_MX28) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) |
||||
#endif |
||||
|
||||
/* Point initial SP in SRAM so SPL can use it too. */ |
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/*
|
||||
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some |
||||
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot |
||||
* binary. In case there was more of this mess, 0x100 bytes are skipped. |
||||
*/ |
||||
#define CONFIG_SYS_TEXT_BASE 0x40000100 |
||||
|
||||
/* U-Boot general configuration */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#ifndef CONFIG_SYS_PROMPT |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#endif |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
/* Print buffer size */ |
||||
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
/* Boot argument buffer size */ |
||||
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ |
||||
#define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command history etc */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* Booting Linux */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
|
||||
/*
|
||||
* Drivers |
||||
*/ |
||||
|
||||
/* APBH DMA */ |
||||
#define CONFIG_APBH_DMA |
||||
|
||||
/* GPIO */ |
||||
#define CONFIG_MXS_GPIO |
||||
|
||||
/* DUART Serial Driver */ |
||||
#define CONFIG_PL011_SERIAL |
||||
#define CONFIG_PL011_CLOCK 24000000 |
||||
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } |
||||
#define CONFIG_CONS_INDEX 0 |
||||
/* Default baudrate can be overriden by board! */ |
||||
#ifndef CONFIG_BAUDRATE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#endif |
||||
|
||||
/* FEC Ethernet on SoC */ |
||||
#ifdef CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#ifndef CONFIG_ETHPRIME |
||||
#define CONFIG_ETHPRIME "FEC0" |
||||
#endif |
||||
#ifndef CONFIG_FEC_XCV_TYPE |
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#endif |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#ifdef CONFIG_CMD_I2C |
||||
#define CONFIG_I2C_MXS |
||||
#define CONFIG_HARD_I2C |
||||
#ifndef CONFIG_SYS_I2C_SPEED |
||||
#define CONFIG_SYS_I2C_SPEED 400000 |
||||
#endif |
||||
#endif |
||||
|
||||
/* LCD */ |
||||
#ifdef CONFIG_VIDEO |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VIDEO_MXS |
||||
#define CONFIG_VIDEO_SW_CURSOR |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#endif |
||||
|
||||
/* MMC */ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_MXS_MMC |
||||
#endif |
||||
|
||||
/* NAND */ |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_NAND_MXS |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x60000000 |
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||||
#endif |
||||
|
||||
/* SPI */ |
||||
#ifdef CONFIG_CMD_SPI |
||||
#define CONFIG_HARD_SPI |
||||
#define CONFIG_MXS_SPI |
||||
#define CONFIG_SPI_HALF_DUPLEX |
||||
#endif |
||||
|
||||
/* USB */ |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MXS |
||||
#define CONFIG_EHCI_IS_TDI |
||||
#endif |
||||
|
||||
#endif /* __CONFIGS_MXS_H__ */ |
||||
Loading…
Reference in new issue