stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>master
Vikas Manocha
10 years ago
committed by
Tom Rini
parent
32fdf0e4d8
commit
9fa32b1237
@ -0,0 +1,9 @@ |
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#
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# (C) Copyright 2014
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# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := timer.o clock.o pinmux.o reset.o
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obj-y += lowlevel.o
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@ -0,0 +1,27 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/stv0991_cgu.h> |
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#include<asm/arch/stv0991_periph.h> |
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static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
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(struct stv0991_cgu_regs *) (CGU_BASE_ADDR); |
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void clock_setup(int peripheral) |
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{ |
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switch (peripheral) { |
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case UART_CLOCK_CFG: |
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writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); |
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break; |
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case ETH_CLOCK_CFG: |
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break; |
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default: |
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break; |
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} |
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} |
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@ -0,0 +1,12 @@ |
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/* |
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* (C) Copyright 2014 stmicroelectronics |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <linux/linkage.h> |
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ENTRY(lowlevel_init) |
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mov pc, lr |
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ENDPROC(lowlevel_init) |
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@ -0,0 +1,48 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/io.h> |
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#include <asm/arch/stv0991_creg.h> |
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#include <asm/arch/stv0991_periph.h> |
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#include <asm/arch/hardware.h> |
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static struct stv0991_creg *const stv0991_creg = \
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(struct stv0991_creg *)CREG_BASE_ADDR; |
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int stv0991_pinmux_config(int peripheral) |
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{ |
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switch (peripheral) { |
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case UART_GPIOC_30_31: |
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/* SSDA/SSCL pad muxing to UART Rx/Dx */ |
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writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | |
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CFG_GPIOC_31_UART_RX, |
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&stv0991_creg->mux12); |
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writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | |
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CFG_GPIOC_30_UART_TX, |
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&stv0991_creg->mux12); |
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/* SSDA/SSCL pad config to push pull*/ |
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writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | |
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CFG_GPIOC_31_MODE_PP, |
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&stv0991_creg->cfg_pad6); |
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writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | |
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CFG_GPIOC_30_MODE_HIGH, |
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&stv0991_creg->cfg_pad6); |
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break; |
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case UART_GPIOB_16_17: |
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/* ethernet rx_6/7 to UART Rx/Dx */ |
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writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | |
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CFG_GPIOB_17_UART_RX, |
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&stv0991_creg->mux7); |
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writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | |
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CFG_GPIOB_16_UART_TX, |
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&stv0991_creg->mux7); |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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@ -0,0 +1,26 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/stv0991_wdru.h> |
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void reset_cpu(ulong ignored) |
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{ |
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puts("System is going to reboot ...\n"); |
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/*
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* This 1 second delay will allow the above message |
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* to be printed before reset |
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*/ |
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udelay((1000 * 1000)); |
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/* Setting bit 1 of the WDRU unit will reset the SoC */ |
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writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1); |
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/* system will restart */ |
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while (1) |
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; |
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} |
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@ -0,0 +1,114 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch-stv0991/hardware.h> |
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#include <asm/arch-stv0991/stv0991_cgu.h> |
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#include <asm/arch-stv0991/stv0991_gpt.h> |
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static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
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(struct stv0991_cgu_regs *) (CGU_BASE_ADDR); |
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#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) |
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#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) |
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DECLARE_GLOBAL_DATA_PTR; |
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#define timestamp gd->arch.tbl |
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#define lastdec gd->arch.lastinc |
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int timer_init(void) |
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{ |
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/* Timer1 clock configuration */ |
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writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); |
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writel(readl(&stv0991_cgu_regs->cgu_enable_2) | |
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TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); |
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/* Stop the timer */ |
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writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); |
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writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc); |
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/* Configure timer for auto-reload */ |
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writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, |
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&gpt1_regs_ptr->cr1); |
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/* load value for free running */ |
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writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); |
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/* start timer */ |
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writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, |
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&gpt1_regs_ptr->cr1); |
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/* Reset the timer */ |
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lastdec = READ_TIMER(); |
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timestamp = 0; |
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return 0; |
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} |
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/*
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* timer without interrupts |
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*/ |
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ulong get_timer(ulong base) |
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{ |
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return (get_timer_masked() / GPT_RESOLUTION) - base; |
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} |
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void __udelay(unsigned long usec) |
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{ |
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ulong tmo; |
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ulong start = get_timer_masked(); |
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ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); |
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ulong rndoff; |
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rndoff = (usec % 10) ? 1 : 0; |
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/* tenudelcnt timer tick gives 10 microsecconds delay */ |
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tmo = ((usec / 10) + rndoff) * tenudelcnt; |
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while ((ulong) (get_timer_masked() - start) < tmo) |
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; |
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} |
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ulong get_timer_masked(void) |
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{ |
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ulong now = READ_TIMER(); |
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if (now >= lastdec) { |
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/* normal mode */ |
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timestamp += now - lastdec; |
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} else { |
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/* we have an overflow ... */ |
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timestamp += now + GPT_FREE_RUNNING - lastdec; |
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} |
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lastdec = now; |
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return timestamp; |
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} |
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void udelay_masked(unsigned long usec) |
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{ |
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return udelay(usec); |
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} |
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/*
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* This function is derived from PowerPC code (read timebase as long long). |
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* On ARM it just returns the timer value. |
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*/ |
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unsigned long long get_ticks(void) |
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{ |
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return get_timer(0); |
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} |
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/*
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* This function is derived from PowerPC code (timebase clock frequency). |
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* On ARM it returns the number of timer ticks per second. |
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*/ |
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ulong get_tbclk(void) |
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{ |
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return CONFIG_STV0991_HZ; |
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} |
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@ -0,0 +1,73 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_HARDWARE_H |
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#define _ASM_ARCH_HARDWARE_H |
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/* STV0991 */ |
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#define SRAM0_BASE_ADDR 0x00000000UL |
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#define SRAM1_BASE_ADDR 0x00068000UL |
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#define SRAM2_BASE_ADDR 0x000D0000UL |
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#define SRAM3_BASE_ADDR 0x00138000UL |
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#define CFS_SRAM0_BASE_ADDR 0x00198000UL |
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#define CFS_SRAM1_BASE_ADDR 0x001B8000UL |
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#define FAST_SRAM_BASE_ADDR 0x001D8000UL |
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#define FLASH_BASE_ADDR 0x40000000UL |
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#define PL310_BASE_ADDR 0x70000000UL |
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#define HSAXIM_BASE_ADDR 0x70100000UL |
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#define IMGSS_BASE_ADDR 0x70200000UL |
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#define ADC_BASE_ADDR 0x80000000UL |
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#define GPIOA_BASE_ADDR 0x80001000UL |
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#define GPIOB_BASE_ADDR 0x80002000UL |
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#define GPIOC_BASE_ADDR 0x80003000UL |
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#define HDM_BASE_ADDR 0x80004000UL |
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#define THSENS_BASE_ADDR 0x80200000UL |
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#define GPTIMER2_BASE_ADDR 0x80201000UL |
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#define GPTIMER1_BASE_ADDR 0x80202000UL |
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#define QSPI_BASE_ADDR 0x80203000UL |
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#define CGU_BASE_ADDR 0x80204000UL |
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#define CREG_BASE_ADDR 0x80205000UL |
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#define PEC_BASE_ADDR 0x80206000UL |
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#define WDRU_BASE_ADDR 0x80207000UL |
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#define BSEC_BASE_ADDR 0x80208000UL |
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#define DAP_ROM_BASE_ADDR 0x80210000UL |
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#define SOC_CTI_BASE_ADDR 0x80211000UL |
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#define TPIU_BASE_ADDR 0x80212000UL |
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#define TMC_ETF_BASE_ADDR 0x80213000UL |
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#define R4_ETM_BASE_ADDR 0x80214000UL |
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#define R4_CTI_BASE_ADDR 0x80215000UL |
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#define R4_DBG_BASE_ADDR 0x80216000UL |
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#define GMAC_BASE_ADDR 0x80300000UL |
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#define RNSS_BASE_ADDR 0x80302000UL |
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#define CRYP_BASE_ADDR 0x80303000UL |
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#define HASH_BASE_ADDR 0x80304000UL |
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#define GPDMA_BASE_ADDR 0x80305000UL |
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#define ISA_BASE_ADDR 0x8032A000UL |
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#define HCI_BASE_ADDR 0x80400000UL |
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#define I2C1_BASE_ADDR 0x80401000UL |
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#define I2C2_BASE_ADDR 0x80402000UL |
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#define SAI_BASE_ADDR 0x80403000UL |
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#define USI_BASE_ADDR 0x80404000UL |
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#define SPI1_BASE_ADDR 0x80405000UL |
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#define UART_BASE_ADDR 0x80406000UL |
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#define SPI2_BASE_ADDR 0x80500000UL |
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#define CAN_BASE_ADDR 0x80501000UL |
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#define USART1_BASE_ADDR 0x80502000UL |
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#define USART2_BASE_ADDR 0x80503000UL |
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#define USART3_BASE_ADDR 0x80504000UL |
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#define USART4_BASE_ADDR 0x80505000UL |
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#define USART5_BASE_ADDR 0x80506000UL |
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#define USART6_BASE_ADDR 0x80507000UL |
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#define SDI2_BASE_ADDR 0x80600000UL |
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#define SDI1_BASE_ADDR 0x80601000UL |
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#define VICA_BASE_ADDR 0x81000000UL |
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#define VICB_BASE_ADDR 0x81001000UL |
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#define STM_CHANNELS_BASE_ADDR 0x81100000UL |
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#define STM_BASE_ADDR 0x81110000UL |
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#define SROM_BASE_ADDR 0xFFFF0000UL |
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#endif /* _ASM_ARCH_HARDWARE_H */ |
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@ -0,0 +1,80 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _STV0991_CGU_H |
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#define _STV0991_CGU_H |
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struct stv0991_cgu_regs { |
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u32 cpu_freq; /* offset 0x0 */ |
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u32 icn2_freq; /* offset 0x4 */ |
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u32 dma_freq; /* offset 0x8 */ |
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u32 isp_freq; /* offset 0xc */ |
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u32 h264_freq; /* offset 0x10 */ |
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u32 osif_freq; /* offset 0x14 */ |
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u32 ren_freq; /* offset 0x18 */ |
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u32 tim_freq; /* offset 0x1c */ |
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u32 sai_freq; /* offset 0x20 */ |
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u32 eth_freq; /* offset 0x24 */ |
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u32 i2c_freq; /* offset 0x28 */ |
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u32 spi_freq; /* offset 0x2c */ |
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u32 uart_freq; /* offset 0x30 */ |
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u32 qspi_freq; /* offset 0x34 */ |
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u32 sdio_freq; /* offset 0x38 */ |
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u32 usi_freq; /* offset 0x3c */ |
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u32 can_line_freq; /* offset 0x40 */ |
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u32 debug_freq; /* offset 0x44 */ |
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u32 trace_freq; /* offset 0x48 */ |
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u32 stm_freq; /* offset 0x4c */ |
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u32 eth_ctrl; /* offset 0x50 */ |
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u32 reserved[3]; /* offset 0x54 */ |
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u32 osc_ctrl; /* offset 0x60 */ |
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u32 pll1_ctrl; /* offset 0x64 */ |
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u32 pll1_freq; /* offset 0x68 */ |
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u32 pll1_fract; /* offset 0x6c */ |
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u32 pll1_spread; /* offset 0x70 */ |
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u32 pll1_status; /* offset 0x74 */ |
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u32 pll2_ctrl; /* offset 0x78 */ |
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u32 pll2_freq; /* offset 0x7c */ |
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u32 pll2_fract; /* offset 0x80 */ |
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u32 pll2_spread; /* offset 0x84 */ |
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u32 pll2_status; /* offset 0x88 */ |
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u32 cgu_enable_1; /* offset 0x8c */ |
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u32 cgu_enable_2; /* offset 0x90 */ |
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u32 cgu_isp_pulse; /* offset 0x94 */ |
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u32 cgu_h264_pulse; /* offset 0x98 */ |
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u32 cgu_osif_pulse; /* offset 0x9c */ |
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u32 cgu_ren_pulse; /* offset 0xa0 */ |
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}; |
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/* CGU Timer */ |
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#define CLK_TMR_OSC 0 |
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#define CLK_TMR_MCLK 1 |
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#define CLK_TMR_PLL1 2 |
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#define CLK_TMR_PLL2 3 |
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#define MDIV_SHIFT_TMR 3 |
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#define DIV_SHIFT_TMR 6 |
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#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ |
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| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) |
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/* Clock Enable/Disable */ |
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#define TIMER1_CLK_EN (1 << 15) |
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/* CGU Uart config */ |
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#define CLK_UART_MCLK 0 |
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#define CLK_UART_PLL1 1 |
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#define CLK_UART_PLL2 2 |
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#define MDIV_SHIFT_UART 3 |
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#define DIV_SHIFT_UART 6 |
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#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ |
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| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) |
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#endif |
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@ -0,0 +1,82 @@ |
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/*
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* (C) Copyright 2014 |
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _STV0991_CREG_H |
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#define _STV0991_CREG_H |
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struct stv0991_creg { |
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u32 version; /* offset 0x0 */ |
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u32 hdpctl; /* offset 0x4 */ |
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u32 hdpval; /* offset 0x8 */ |
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u32 hdpgposet; /* offset 0xc */ |
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u32 hdpgpoclr; /* offset 0x10 */ |
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u32 hdpgpoval; /* offset 0x14 */ |
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u32 stm_mux; /* offset 0x18 */ |
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u32 sysctrl_1; /* offset 0x1c */ |
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u32 sysctrl_2; /* offset 0x20 */ |
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u32 sysctrl_3; /* offset 0x24 */ |
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u32 sysctrl_4; /* offset 0x28 */ |
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u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ |
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u32 mux1; /* offset 0x100 */ |
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u32 mux2; /* offset 0x104 */ |
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u32 mux3; /* offset 0x108 */ |
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u32 mux4; /* offset 0x10c */ |
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u32 mux5; /* offset 0x110 */ |
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u32 mux6; /* offset 0x114 */ |
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u32 mux7; /* offset 0x118 */ |
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u32 mux8; /* offset 0x11c */ |
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u32 mux9; /* offset 0x120 */ |
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u32 mux10; /* offset 0x124 */ |
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u32 mux11; /* offset 0x128 */ |
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u32 mux12; /* offset 0x12c */ |
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u32 mux13; /* offset 0x130 */ |
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u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ |
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u32 cfg_pad1; /* offset 0x200 */ |
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u32 cfg_pad2; /* offset 0x204 */ |
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u32 cfg_pad3; /* offset 0x208 */ |
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u32 cfg_pad4; /* offset 0x20c */ |
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u32 cfg_pad5; /* offset 0x210 */ |
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u32 cfg_pad6; /* offset 0x214 */ |
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u32 cfg_pad7; /* offset 0x218 */ |
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u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ |
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u32 vdd_pad1; /* offset 0x300 */ |
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u32 vdd_pad2; /* offset 0x304 */ |
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u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ |
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u32 vdd_comp1; /* offset 0x400 */ |
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}; |
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/* CREG MUX 12 register */ |
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#define GPIOC_30_MUX_SHIFT 24 |
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#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) |
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#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) |
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#define GPIOC_31_MUX_SHIFT 28 |
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#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) |
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#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) |
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/* CREG MUX 7 register */ |
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#define GPIOB_16_MUX_SHIFT 0 |
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#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) |
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#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) |
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#define GPIOB_17_MUX_SHIFT 4 |
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#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) |
||||
#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) |
||||
|
||||
/* CREG CFG_PAD6 register */ |
||||
|
||||
#define GPIOC_31_MODE_SHIFT 30 |
||||
#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) |
||||
#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) |
||||
#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) |
||||
|
||||
#define GPIOC_30_MODE_SHIFT 28 |
||||
#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) |
||||
#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) |
||||
#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) |
||||
|
||||
#endif |
||||
@ -0,0 +1,16 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __STV0991_DEFS_H__ |
||||
#define __STV0991_DEFS_H__ |
||||
#include <asm/arch/stv0991_periph.h> |
||||
|
||||
extern int stv0991_pinmux_config(enum periph_id); |
||||
extern int clock_setup(enum periph_clock); |
||||
|
||||
#endif |
||||
|
||||
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _STV0991_GPT_H |
||||
#define _STV0991_GPT_H |
||||
|
||||
#include <asm/arch-stv0991/hardware.h> |
||||
|
||||
struct gpt_regs { |
||||
u32 cr1; |
||||
u32 cr2; |
||||
u32 reserved_1; |
||||
u32 dier; /* dma_int_en */ |
||||
u32 sr; /* status reg */ |
||||
u32 egr; /* event gen */ |
||||
u32 reserved_2[3]; /* offset 0x18--0x20*/ |
||||
u32 cnt; |
||||
u32 psc; |
||||
u32 arr; |
||||
}; |
||||
|
||||
struct gpt_regs *const gpt1_regs_ptr = |
||||
(struct gpt_regs *) GPTIMER1_BASE_ADDR; |
||||
|
||||
/* Timer control1 register */ |
||||
#define GPT_CR1_CEN 0x0001 |
||||
#define GPT_MODE_AUTO_RELOAD (1 << 7) |
||||
|
||||
/* Timer prescalar reg */ |
||||
#define GPT_PRESCALER_128 0x128 |
||||
|
||||
/* Auto reload register for free running config */ |
||||
#define GPT_FREE_RUNNING 0xFFFF |
||||
|
||||
/* Timer, HZ specific defines */ |
||||
#define CONFIG_STV0991_HZ 1000 |
||||
#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 |
||||
|
||||
#endif |
||||
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_PERIPH_H |
||||
#define __ASM_ARM_ARCH_PERIPH_H |
||||
|
||||
/*
|
||||
* Peripherals required for pinmux configuration. List will |
||||
* grow with support for more devices getting added. |
||||
* Numbering based on interrupt table. |
||||
* |
||||
*/ |
||||
enum periph_id { |
||||
UART_GPIOC_30_31 = 0, |
||||
UART_GPIOB_16_17, |
||||
PERIPH_ID_I2C0, |
||||
PERIPH_ID_I2C1, |
||||
PERIPH_ID_I2C2, |
||||
PERIPH_ID_I2C3, |
||||
PERIPH_ID_I2C4, |
||||
PERIPH_ID_I2C5, |
||||
PERIPH_ID_I2C6, |
||||
PERIPH_ID_I2C7, |
||||
PERIPH_ID_SPI0, |
||||
PERIPH_ID_SPI1, |
||||
PERIPH_ID_SPI2, |
||||
PERIPH_ID_SDMMC0, |
||||
PERIPH_ID_SDMMC1, |
||||
PERIPH_ID_SDMMC2, |
||||
PERIPH_ID_SDMMC3, |
||||
PERIPH_ID_I2S1, |
||||
}; |
||||
|
||||
enum periph_clock { |
||||
UART_CLOCK_CFG = 0, |
||||
ETH_CLOCK_CFG, |
||||
}; |
||||
|
||||
#endif /* __ASM_ARM_ARCH_PERIPH_H */ |
||||
@ -0,0 +1,28 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _STV0991_WD_RST_H |
||||
#define _STV0991_WD_RST_H |
||||
#include <asm/arch-stv0991/hardware.h> |
||||
|
||||
struct stv0991_wd_ru { |
||||
u32 wdru_config; |
||||
u32 wdru_ctrl1; |
||||
u32 wdru_ctrl2; |
||||
u32 wdru_tim; |
||||
u32 wdru_count; |
||||
u32 wdru_stat; |
||||
u32 wdru_wrlock; |
||||
}; |
||||
|
||||
struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
|
||||
(struct stv0991_wd_ru *)WDRU_BASE_ADDR; |
||||
|
||||
/* Watchdog control register */ |
||||
#define WDRU_RST_SYS 0x1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,23 @@ |
||||
if TARGET_STV0991 |
||||
|
||||
config SYS_CPU |
||||
string |
||||
default "armv7" |
||||
|
||||
config SYS_BOARD |
||||
string |
||||
default "stv0991" |
||||
|
||||
config SYS_VENDOR |
||||
string |
||||
default "st" |
||||
|
||||
config SYS_SOC |
||||
string |
||||
default "stv0991" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
string |
||||
default "stv0991" |
||||
|
||||
endif |
||||
@ -0,0 +1,5 @@ |
||||
STV0991 APPLICATION BOARD |
||||
M: Vikas Manocha <vikas.manocha@st.com> |
||||
S: Maintained |
||||
F: board/st/stv0991/ |
||||
F: include/configs/stv0991.h |
||||
@ -0,0 +1,8 @@ |
||||
#
|
||||
# (C) Copyright 2014
|
||||
# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := stv0991.o
|
||||
@ -0,0 +1,54 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <miiphy.h> |
||||
#include <asm/arch/stv0991_periph.h> |
||||
#include <asm/arch/stv0991_defs.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
printf("%i\n", progress); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int board_uart_init(void) |
||||
{ |
||||
stv0991_pinmux_config(UART_GPIOC_30_31); |
||||
clock_setup(UART_CLOCK_CFG); |
||||
return 0; |
||||
} |
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F |
||||
int board_early_init_f(void) |
||||
{ |
||||
board_uart_init(); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = PHYS_SDRAM_1_SIZE; |
||||
return 0; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
} |
||||
@ -0,0 +1,3 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="stv0991" |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_STV0991=y |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_STV0991_H |
||||
#define __CONFIG_STV0991_H |
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_SYS_ICACHE_OFF |
||||
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_SYS_CORTEX_R4 |
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/* ram memory-related information */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define PHYS_SDRAM_1_SIZE 0x00198000 |
||||
|
||||
#define CONFIG_ENV_SIZE 0x10000 |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR \ |
||||
(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) |
||||
|
||||
/* serial port (PL011) configuration */ |
||||
#define CONFIG_SYS_SERIAL0 0x80406000 |
||||
#define CONFIG_PL011_SERIAL |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} |
||||
#define CONFIG_PL011_CLOCK (2700 * 1000) |
||||
|
||||
/* user interface */ |
||||
#define CONFIG_SYS_PROMPT "STV0991> " |
||||
#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/* MISC */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x00000000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 |
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
/* U-boot Load Address */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x00010000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue