This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>master
Max Krummenacher
8 years ago
committed by
Stefano Babic
parent
592f4aed6d
commit
a02d517b01
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2014-2016, Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D |
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 |
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 |
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB |
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 |
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DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 |
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 |
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D |
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/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ |
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 |
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/* DDR3 DATA BUS SIZE: 64BIT */ |
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/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ |
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/* DDR3 DATA BUS SIZE: 32BIT */ |
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DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 |
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/* Write commands to DDR */ |
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/* Load Mode Registers */ |
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/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ |
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/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 |
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/* ZQ calibration */ |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 |
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 |
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 |
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 |
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A |
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 |
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 |
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 |
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E |
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 |
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D |
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2014-2016, Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D |
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 |
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 |
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB |
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 |
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DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 |
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 |
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D |
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/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ |
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 |
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/* DDR3 DATA BUS SIZE: 64BIT */ |
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DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 |
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/* DDR3 DATA BUS SIZE: 32BIT */ |
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/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ |
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/* Write commands to DDR */ |
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/* Load Mode Registers */ |
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/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ |
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/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 |
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/* ZQ calibration */ |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 |
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 |
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 |
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 |
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 |
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A |
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 |
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 |
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 |
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E |
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 |
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 |
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 |
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D |
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
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@ -0,0 +1,44 @@ |
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if TARGET_COLIBRI_IMX6 |
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config SYS_BOARD |
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default "colibri_imx6" |
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config SYS_CONFIG_NAME |
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default "colibri_imx6" |
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config SYS_CPU |
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default "armv7" |
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config SYS_SOC |
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default "mx6" |
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config SYS_VENDOR |
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default "toradex" |
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config TDX_CFG_BLOCK |
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default y |
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config TDX_HAVE_MMC |
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default y |
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config TDX_CFG_BLOCK_DEV |
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default "0" |
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config TDX_CFG_BLOCK_PART |
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default "1" |
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# Toradex config block in eMMC, at the end of 1st "boot sector" |
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config TDX_CFG_BLOCK_OFFSET |
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default "-512" |
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config TDX_CMD_IMX_MFGR |
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bool "Enable factory testing commands for Toradex iMX 6 modules" |
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help |
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This adds the commands |
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pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 |
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If executed on already fused modules it doesn't change any fuse setting. |
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default y |
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source "board/toradex/common/Kconfig" |
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endif |
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@ -0,0 +1,8 @@ |
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Colibri iMX6 |
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M: Max Krummenacher <max.krummenacher@toradex.com> |
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W: http://developer.toradex.com/software/linux/linux-software |
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S: Maintained |
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F: board/toradex/colibri_imx6/ |
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F: include/configs/colibri_imx6.h |
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F: configs/colibri_imx6_defconfig |
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F: configs/colibri_imx6_nospl_defconfig |
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# Copyright (c) 2012-2014 Toradex, Inc.
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := colibri_imx6.o do_fuse.o
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obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2014-2016, Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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/* set the default clock gate to save power */ |
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DATA 4, CCM_CCGR0, 0x00C03F3F |
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DATA 4, CCM_CCGR1, 0x0030FC03 |
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DATA 4, CCM_CCGR2, 0x0FFFC000 |
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DATA 4, CCM_CCGR3, 0x3FF00000 |
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DATA 4, CCM_CCGR4, 0x00FFF300 |
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DATA 4, CCM_CCGR5, 0x0F0000C3 |
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DATA 4, CCM_CCGR6, 0x000003FF |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF |
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F |
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F |
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/* |
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* Setup CCM_CCOSR register as follows: |
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* |
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* cko1_en = 1 --> CKO1 enabled |
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* cko1_div = 111 --> divide by 8 |
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* cko1_sel = 1011 --> ahb_clk_root |
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* |
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz |
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*/ |
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DATA 4, CCM_CCOSR, 0x000000fb |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,38 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2014 Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of |
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* spi, sd (the board has no nand neither onenand) |
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*/ |
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BOOT_FROM sd |
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#define __ASSEMBLY__ |
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#include <config.h> |
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#include "asm/arch/mx6-ddr.h" |
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#include "asm/arch/iomux.h" |
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#include "asm/arch/crm_regs.h" |
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#include "ddr-setup.cfg" |
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#if CONFIG_DDR_MB == 256 |
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#include "800mhz_2x64mx16.cfg" |
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#elif CONFIG_DDR_MB == 512 |
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#include "800mhz_4x64mx16.cfg" |
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#else |
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#error "unknown DDR size" |
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#endif |
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#include "clocks.cfg" |
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@ -0,0 +1,98 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2014-2016, Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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/* |
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* DDR3 settings |
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* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), |
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* memory bus width: 64 bits x16/x32/x64 |
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* MX6DL ddr is limited to 800 MHz(400 MHz clock) |
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* memory bus width: 64 bits x16/x32/x64 |
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* MX6SOLO ddr is limited to 800 MHz(400 MHz clock) |
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* memory bus width: 32 bits x16/x32 |
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*/ |
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 |
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 |
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 |
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 |
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 |
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 |
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 |
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 |
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/* (differential input) */ |
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 |
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/* (differential input) */ |
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 |
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/* disable ddr pullups */ |
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 |
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 |
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 |
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/* Read data DQ Byte0-3 delay */ |
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 |
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 |
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/* |
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* MDMISC mirroring interleaved (row/bank/col) |
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*/ |
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/* TODO: check what the RALAT field does */ |
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 |
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/* |
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* MDSCR con_req |
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*/ |
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
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@ -0,0 +1,98 @@ |
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/*
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* Copyright (C) 2014-2016, Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Helpers for i.MX OTP fusing during module production |
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*/ |
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#include <common.h> |
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#ifndef CONFIG_SPL_BUILD |
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#include <console.h> |
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#include <fuse.h> |
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static int mfgr_fuse(void) |
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{ |
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unsigned val, val6; |
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fuse_sense(0, 5, &val); |
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printf("Fuse 0, 5: %8x\n", val); |
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fuse_sense(0, 6, &val6); |
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printf("Fuse 0, 6: %8x\n", val6); |
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fuse_sense(4, 3, &val); |
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printf("Fuse 4, 3: %8x\n", val); |
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fuse_sense(4, 2, &val); |
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printf("Fuse 4, 2: %8x\n", val); |
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if (val6 & 0x10) { |
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puts("BT_FUSE_SEL already fused, will do nothing\n"); |
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return CMD_RET_FAILURE; |
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} |
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/* boot cfg */ |
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fuse_prog(0, 5, 0x00005072); |
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/* BT_FUSE_SEL */ |
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fuse_prog(0, 6, 0x00000010); |
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return CMD_RET_SUCCESS; |
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} |
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int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc, |
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char * const argv[]) |
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{ |
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int ret; |
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puts("Fusing...\n"); |
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ret = mfgr_fuse(); |
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if (ret == CMD_RET_SUCCESS) |
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puts("done.\n"); |
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else |
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puts("failed.\n"); |
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return ret; |
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} |
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int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc, |
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char * const argv[]) |
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{ |
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unsigned val; |
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int ret; |
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int confirmed = argc >= 1 && !strcmp(argv[1], "-y"); |
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/* can be used in scripts for command availability check */ |
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if (argc >= 1 && !strcmp(argv[1], "-n")) |
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return CMD_RET_SUCCESS; |
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/* boot cfg */ |
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fuse_sense(0, 5, &val); |
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printf("Fuse 0, 5: %8x\n", val); |
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if (val & 0x10) { |
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puts("Fast boot mode already fused, no need to fuse\n"); |
||||
return CMD_RET_SUCCESS; |
||||
} |
||||
if (!confirmed) { |
||||
puts("Warning: Programming fuses is an irreversible operation!\n" |
||||
" Updating to fast boot mode prevents easy\n" |
||||
" downgrading to previous BSP versions.\n" |
||||
"\nReally perform this fuse programming? <y/N>\n"); |
||||
if (!confirm_yesno()) |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
puts("Fusing fast boot mode...\n"); |
||||
ret = fuse_prog(0, 5, 0x00005072); |
||||
if (ret == CMD_RET_SUCCESS) |
||||
puts("done.\n"); |
||||
else |
||||
puts("failed.\n"); |
||||
return ret; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
mfgr_fuse, 1, 0, do_mfgr_fuse, |
||||
"OTP fusing during module production", |
||||
"" |
||||
); |
||||
|
||||
U_BOOT_CMD( |
||||
updt_fuse, 2, 0, do_updt_fuse, |
||||
"OTP fusing during module update", |
||||
"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" |
||||
); |
||||
#endif /* CONFIG_SPL_BUILD */ |
||||
@ -0,0 +1,211 @@ |
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
|
||||
#include "pf0100_otp.inc" |
||||
#include "pf0100.h" |
||||
|
||||
/* define for PMIC register dump */ |
||||
/*#define DEBUG */ |
||||
|
||||
/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ |
||||
static iomux_v3_cfg_t const pmic_prog_pads[] = { |
||||
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3) |
||||
}; |
||||
|
||||
unsigned pmic_init(void) |
||||
{ |
||||
unsigned programmed = 0; |
||||
uchar bus = 1; |
||||
uchar devid, revid, val; |
||||
|
||||
puts("PMIC: "); |
||||
if (!((0 == i2c_set_bus_num(bus)) && |
||||
(0 == i2c_probe(PFUZE100_I2C_ADDR)))) { |
||||
puts("i2c bus failed\n"); |
||||
return 0; |
||||
} |
||||
/* get device ident */ |
||||
if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { |
||||
puts("i2c pmic devid read failed\n"); |
||||
return 0; |
||||
} |
||||
if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { |
||||
puts("i2c pmic revid read failed\n"); |
||||
return 0; |
||||
} |
||||
printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); |
||||
|
||||
#ifdef DEBUG |
||||
{ |
||||
unsigned i, j; |
||||
|
||||
for (i = 0; i < 16; i++) |
||||
printf("\t%x", i); |
||||
for (j = 0; j < 0x80; ) { |
||||
printf("\n%2x", j); |
||||
for (i = 0; i < 16; i++) { |
||||
i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); |
||||
printf("\t%2x", val); |
||||
} |
||||
j += 0x10; |
||||
} |
||||
printf("\nEXT Page 1"); |
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE1; |
||||
if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, |
||||
&val, 1)) { |
||||
puts("i2c write failed\n"); |
||||
return 0; |
||||
} |
||||
|
||||
for (j = 0x80; j < 0x100; ) { |
||||
printf("\n%2x", j); |
||||
for (i = 0; i < 16; i++) { |
||||
i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); |
||||
printf("\t%2x", val); |
||||
} |
||||
j += 0x10; |
||||
} |
||||
printf("\nEXT Page 2"); |
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE2; |
||||
if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, |
||||
&val, 1)) { |
||||
puts("i2c write failed\n"); |
||||
return 0; |
||||
} |
||||
|
||||
for (j = 0x80; j < 0x100; ) { |
||||
printf("\n%2x", j); |
||||
for (i = 0; i < 16; i++) { |
||||
i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); |
||||
printf("\t%2x", val); |
||||
} |
||||
j += 0x10; |
||||
} |
||||
printf("\n"); |
||||
} |
||||
#endif |
||||
/* get device programmed state */ |
||||
val = PFUZE100_PAGE_REGISTER_PAGE1; |
||||
if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { |
||||
puts("i2c write failed\n"); |
||||
return 0; |
||||
} |
||||
if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { |
||||
puts("i2c fuse_por read failed\n"); |
||||
return 0; |
||||
} |
||||
if (val & PFUZE100_FUSE_POR_M) |
||||
programmed++; |
||||
|
||||
if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { |
||||
puts("i2c fuse_por read failed\n"); |
||||
return programmed; |
||||
} |
||||
if (val & PFUZE100_FUSE_POR_M) |
||||
programmed++; |
||||
|
||||
if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { |
||||
puts("i2c fuse_por read failed\n"); |
||||
return programmed; |
||||
} |
||||
if (val & PFUZE100_FUSE_POR_M) |
||||
programmed++; |
||||
|
||||
switch (programmed) { |
||||
case 0: |
||||
printf("PMIC: not programmed\n"); |
||||
break; |
||||
case 3: |
||||
printf("PMIC: programmed\n"); |
||||
break; |
||||
default: |
||||
printf("PMIC: undefined programming state\n"); |
||||
break; |
||||
} |
||||
|
||||
return programmed; |
||||
} |
||||
|
||||
int pf0100_prog(void) |
||||
{ |
||||
unsigned char bus = 1; |
||||
unsigned char val; |
||||
unsigned int i; |
||||
|
||||
if (pmic_init() == 3) { |
||||
puts("PMIC already programmed, exiting\n"); |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
/* set up gpio to manipulate vprog, initially off */ |
||||
imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, |
||||
ARRAY_SIZE(pmic_prog_pads)); |
||||
gpio_direction_output(PMIC_PROG_VOLTAGE, 0); |
||||
|
||||
if (!((0 == i2c_set_bus_num(bus)) && |
||||
(0 == i2c_probe(PFUZE100_I2C_ADDR)))) { |
||||
puts("i2c bus failed\n"); |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) { |
||||
switch (pmic_otp_prog[i].cmd) { |
||||
case pmic_i2c: |
||||
val = (unsigned char) (pmic_otp_prog[i].value & 0xff); |
||||
if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, |
||||
1, &val, 1)) { |
||||
printf("i2c write failed, reg 0x%2x, value 0x%2x\n", |
||||
pmic_otp_prog[i].reg, val); |
||||
return CMD_RET_FAILURE; |
||||
} |
||||
break; |
||||
case pmic_delay: |
||||
udelay(pmic_otp_prog[i].value * 1000); |
||||
break; |
||||
case pmic_vpgm: |
||||
gpio_direction_output(PMIC_PROG_VOLTAGE, |
||||
pmic_otp_prog[i].value); |
||||
break; |
||||
case pmic_pwr: |
||||
/* TODO */ |
||||
break; |
||||
} |
||||
} |
||||
return CMD_RET_SUCCESS; |
||||
} |
||||
|
||||
int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc, |
||||
char * const argv[]) |
||||
{ |
||||
int ret; |
||||
puts("Programming PMIC OTP..."); |
||||
ret = pf0100_prog(); |
||||
if (ret == CMD_RET_SUCCESS) |
||||
puts("done.\n"); |
||||
else |
||||
puts("failed.\n"); |
||||
return ret; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
pf0100_otp_prog, 1, 0, do_pf0100_prog, |
||||
"Program the OTP fuses on the PMIC PF0100", |
||||
"" |
||||
); |
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100 |
||||
*/ |
||||
|
||||
#ifndef PF0100_H_ |
||||
#define PF0100_H_ |
||||
|
||||
/* 7-bit I2C bus slave address */ |
||||
#define PFUZE100_I2C_ADDR (0x08) |
||||
/* Register Addresses */ |
||||
#define PFUZE100_DEVICEID (0x0) |
||||
#define PFUZE100_REVID (0x3) |
||||
#define PFUZE100_SW1AMODE (0x23) |
||||
#define PFUZE100_SW1ACON 36 |
||||
#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ |
||||
#define PFUZE100_SW1ACON_SPEED_M (0x3<<6) |
||||
#define PFUZE100_SW1CCON 49 |
||||
#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */ |
||||
#define PFUZE100_SW1CCON_SPEED_M (0x3<<6) |
||||
#define PFUZE100_SW1AVOL 32 |
||||
#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) |
||||
#define PFUZE100_SW1CVOL 46 |
||||
#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) |
||||
#define PFUZE100_VGEN1CTL (0x6c) |
||||
#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */ |
||||
#define PFUZE100_SWBSTCTL (0x66) |
||||
/* Always ON, Auto Switching Mode, 5.0V */ |
||||
#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00) |
||||
|
||||
/* chooses the extended page (registers 0x80..0xff) */ |
||||
#define PFUZE100_PAGE_REGISTER 0x7f |
||||
#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0) |
||||
#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M) |
||||
#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) |
||||
|
||||
/* extended page 1 */ |
||||
#define PFUZE100_FUSE_POR1 0xe4 |
||||
#define PFUZE100_FUSE_POR2 0xe5 |
||||
#define PFUZE100_FUSE_POR3 0xe6 |
||||
#define PFUZE100_FUSE_POR_M (0x1 << 1) |
||||
|
||||
|
||||
/* output some informational messages, return the number FUSE_POR=1 */ |
||||
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ |
||||
unsigned pmic_init(void); |
||||
|
||||
/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */ |
||||
int pf0100_prog(void); |
||||
|
||||
#endif /* PF0100_H_ */ |
||||
@ -0,0 +1,189 @@ |
||||
/* |
||||
* Copyright (C) 2014-2016, Toradex AG |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
// Register Output for PF0100 programmer |
||||
// Customer: Toradex AG |
||||
// Program: Colibri iMX6 |
||||
// Sample marking: |
||||
// Date: 24.07.2015 |
||||
// Time: 10:52:58 |
||||
// Generated from Spreadsheet Revision: P1.8 |
||||
|
||||
/* sed commands to get from programmer script to struct */ |
||||
/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc |
||||
sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc |
||||
sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ |
||||
|
||||
enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; |
||||
struct pmic_otp_prog_t{ |
||||
unsigned char cmd; |
||||
unsigned char reg; |
||||
unsigned short value; |
||||
}; |
||||
|
||||
struct pmic_otp_prog_t pmic_otp_prog[] = { |
||||
{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1 |
||||
{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94 |
||||
{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95 |
||||
{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96 |
||||
{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102 |
||||
{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103 |
||||
{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104 |
||||
{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106 |
||||
{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108 |
||||
{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110 |
||||
{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111 |
||||
{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112 |
||||
{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114 |
||||
{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115 |
||||
{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116 |
||||
{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118 |
||||
{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120 |
||||
{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123 |
||||
{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126 |
||||
{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130 |
||||
{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 |
||||
{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 |
||||
{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 |
||||
{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 |
||||
{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 |
||||
{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 |
||||
{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 |
||||
{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154 |
||||
{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155 |
||||
{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158 |
||||
|
||||
#if 0 /* TBB mode */ |
||||
{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1 |
||||
{pmic_delay, 0, 10}, |
||||
#else |
||||
// Write OTP |
||||
{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1 |
||||
{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1 |
||||
{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1 |
||||
{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register |
||||
{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register |
||||
{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2 |
||||
{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register |
||||
{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST |
||||
//VPGM:DOWN:n |
||||
//VPGM:UP:n |
||||
{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up |
||||
//----------------------------------------------------------------------------------- |
||||
// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 1 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 2 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 3 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 4 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 5 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 6 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 7 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 8 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 9 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN |
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
// BANK 10 |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN |
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete |
||||
{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN |
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits |
||||
//----------------------------------------------------------------------------------- |
||||
{pmic_vpgm, 0, 0}, // Turn off 8V SWBST |
||||
{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off |
||||
{pmic_i2c, 0xD0, 0x00}, // Clear |
||||
{pmic_i2c, 0xD1, 0x00}, // Clear |
||||
{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data |
||||
{pmic_delay, 0, 500}, |
||||
{pmic_pwr, 0, 1}, |
||||
#endif |
||||
}; |
||||
@ -0,0 +1,50 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_COLIBRI_IMX6=y |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
CONFIG_SPL_MMC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_VIDEO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" |
||||
CONFIG_BOOTDELAY=1 |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_DMA_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="Colibri iMX6 # " |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
CONFIG_CMD_ASKENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="Toradex" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x1b67 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0x4020 |
||||
CONFIG_OF_LIBFDT=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -0,0 +1,44 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_COLIBRI_IMX6=y |
||||
CONFIG_VIDEO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" |
||||
CONFIG_BOOTDELAY=1 |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="Colibri iMX6 # " |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
CONFIG_CMD_ASKENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_DM=y |
||||
CONFIG_DM_THERMAL=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="Toradex" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x1b67 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0x4020 |
||||
CONFIG_OF_LIBFDT=y |
||||
# CONFIG_EFI_LOADER is not set |
||||
@ -0,0 +1,310 @@ |
||||
/*
|
||||
* Copyright 2013-2015 Toradex, Inc. |
||||
* |
||||
* Configuration settings for the Toradex Colibri iMX6 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include "mx6_common.h" |
||||
#define CONFIG_SYS_THUMB_BUILD |
||||
/* These are not provided in SPL and result in a linker error */ |
||||
#if !defined(CONFIG_SPL_BUILD) |
||||
#define CONFIG_USE_ARCH_MEMCPY |
||||
#define CONFIG_USE_ARCH_MEMSET |
||||
#endif |
||||
|
||||
#undef CONFIG_DISPLAY_BOARDINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ |
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
#ifdef CONFIG_SPL |
||||
#include "imx6_spl.h" |
||||
#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */ |
||||
#endif |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SERIAL_TAG |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
|
||||
/* Make the HW version stuff available in U-Boot env */ |
||||
#define CONFIG_VERSION_VARIABLE /* ver environment variable */ |
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG |
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
|
||||
/* I2C Configs */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* OCOTP Configs */ |
||||
#define CONFIG_CMD_FUSE |
||||
#ifdef CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
#endif |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_FAT_WRITE |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* Network */ |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 1 |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_IP_DEFRAG |
||||
#define CONFIG_TFTP_BLOCKSIZE 16352 |
||||
#define CONFIG_TFTP_TSIZE |
||||
|
||||
/* USB Configs */ |
||||
/* Host */ |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_KEYBOARD |
||||
#ifdef CONFIG_USB_KEYBOARD |
||||
#define CONFIG_SYS_USB_EVENT_POLL |
||||
#endif /* CONFIG_USB_KEYBOARD */ |
||||
/* Client */ |
||||
#define CONFIG_USB_GADGET_VBUS_DRAW 2 |
||||
#define CONFIG_USBD_HS |
||||
|
||||
#define CONFIG_USB_GADGET_MASS_STORAGE |
||||
#define CONFIG_USB_FUNCTION_MASS_STORAGE |
||||
#define CONFIG_G_DNL_MANUFACTURER "Toradex" |
||||
/* USB DFU */ |
||||
#define CONFIG_DFU_MMC |
||||
|
||||
/* Miscellaneous commands */ |
||||
#define CONFIG_CMD_BMODE |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
/* Framebuffer and LCD */ |
||||
#define CONFIG_VIDEO_IPUV3 |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_SPLASH_SCREEN_ALIGN |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_VIDEO_BMP_LOGO |
||||
#define CONFIG_IPUV3_CLK 260000000 |
||||
#define CONFIG_CMD_HDMIDETECT |
||||
#define CONFIG_CONSOLE_MUX |
||||
#define CONFIG_IMX_HDMI |
||||
#define CONFIG_IMX_VIDEO_SKIP |
||||
#define CONFIG_CMD_BMP |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Command definition */ |
||||
#undef CONFIG_CMD_LOADB |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_NFS |
||||
#undef CONFIG_CMD_FLASH |
||||
|
||||
#undef CONFIG_IPADDR |
||||
#define CONFIG_IPADDR 192.168.10.2 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#undef CONFIG_SERVERIP |
||||
#define CONFIG_SERVERIP 192.168.10.1 |
||||
|
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_DRIVE_MMC "mmc " |
||||
#else |
||||
#define CONFIG_DRIVE_MMC |
||||
#endif |
||||
|
||||
#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC |
||||
|
||||
#define DFU_ALT_EMMC_INFO \ |
||||
"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
|
||||
"boot part 0 1;" \
|
||||
"rootfs part 0 2;" \
|
||||
"uImage fat 0 1;" \
|
||||
"imx6q-colibri-eval-v3.dtb fat 0 1;" \
|
||||
"imx6q-colibri-cam-eval-v3.dtb fat 0 1" |
||||
|
||||
#define EMMC_BOOTCMD \ |
||||
"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
|
||||
"rootwait\0" \
|
||||
"emmcboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
|
||||
"${vidargs}; echo Booting from internal eMMC chip...; " \
|
||||
"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
|
||||
"${boot_file} && run fdt_fixup && " \
|
||||
"bootm ${kernel_addr_r} ${dtbparam}\0" \
|
||||
"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
|
||||
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" |
||||
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \ |
||||
"fdt_addr_r=0x12000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"kernel_addr_r=0x11000000\0" \
|
||||
"ramdisk_addr_r=0x12100000\0" |
||||
|
||||
#define NFS_BOOTCMD \ |
||||
"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
|
||||
"nfsboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
|
||||
"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
|
||||
"run nfsdtbload; dhcp ${kernel_addr_r} " \
|
||||
"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
|
||||
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
|
||||
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" |
||||
|
||||
#define SD_BOOTCMD \ |
||||
"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
|
||||
"rootwait\0" \
|
||||
"sdboot=run setup; " \
|
||||
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
|
||||
"${vidargs}; echo Booting from SD card; " \
|
||||
"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
|
||||
"${boot_file} && run fdt_fixup && " \
|
||||
"bootm ${kernel_addr_r} ${dtbparam}\0" \
|
||||
"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
|
||||
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" |
||||
|
||||
#define USB_BOOTCMD \ |
||||
"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
|
||||
"rootwait\0" \
|
||||
"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
|
||||
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
|
||||
"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
|
||||
"${boot_file} && run fdt_fixup && " \
|
||||
"bootm ${kernel_addr_r} ${dtbparam}\0" \
|
||||
"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
|
||||
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" |
||||
|
||||
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
|
||||
"run nfsboot ; echo ; echo nfsboot failed ; " \
|
||||
"usb start ;" \
|
||||
"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
|
||||
"boot_file=uImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
|
||||
"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
|
||||
EMMC_BOOTCMD \
|
||||
"fdt_file=" FDT_FILE "\0" \
|
||||
"fdt_fixup=;\0" \
|
||||
MEM_LAYOUT_ENV_SETTINGS \
|
||||
NFS_BOOTCMD \
|
||||
SD_BOOTCMD \
|
||||
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
|
||||
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
|
||||
"flash_eth.img && source ${loadaddr}\0" \
|
||||
"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
|
||||
"${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
|
||||
"source ${loadaddr}\0" \
|
||||
"setup=setenv setupargs fec_mac=${ethaddr} " \
|
||||
"consoleblank=0 no_console_suspend=1 console=tty1 " \
|
||||
"console=${console},${baudrate}n8\0 " \
|
||||
"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
|
||||
"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
|
||||
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
|
||||
"source ${loadaddr}\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
|
||||
"video=mxcfb1:off fbmem=8M\0 " |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#undef CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#undef CONFIG_SYS_MAXARGS |
||||
#define CONFIG_SYS_MAXARGS 48 |
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000 |
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC) |
||||
/* Environment in eMMC, before config block at the end of 1st "boot sector" */ |
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ |
||||
CONFIG_TDX_CFG_BLOCK_OFFSET) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_SYS_MMC_ENV_PART 1 |
||||
#endif |
||||
|
||||
#define CONFIG_OF_SYSTEM_SETUP |
||||
|
||||
#define CONFIG_CMD_TIME |
||||
|
||||
#define CONFIG_SUPPORT_RAW_INITRD |
||||
|
||||
#define CONFIG_CRC32_VERIFY |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue