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armv7: ls102xa: Move smmu and stream id initialization into the common soc code

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The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
master
Alison Wang 8 years ago committed by York Sun
parent a12a0ef89e
commit a08b1921b4
4 changed files with 52 additions and 83 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 48
      arch/arm/cpu/armv7/ls102xa/soc.c
  2. 2
      arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
  3. 42
      board/freescale/ls1021aqds/ls1021aqds.c
  4. 43
      board/freescale/ls1021atwr/ls1021atwr.c

48
arch/arm/cpu/armv7/ls102xa/soc.c
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@ -9,6 +9,43 @@
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
};
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
{ 0x108, 0x03, "ETSEC MAC3" },
{ 0x10c, 0x04, "PEX1" },
{ 0x110, 0x05, "PEX2" },
{ 0x114, 0x06, "qDMA" },
{ 0x118, 0x07, "SATA" },
{ 0x11c, 0x08, "USB3" },
{ 0x120, 0x09, "QE" },
{ 0x124, 0x0a, "eSDHC" },
{ 0x128, 0x0b, "eMA" },
{ 0x14c, 0x0c, "2D-ACE" },
{ 0x150, 0x0d, "USB2" },
{ 0x18c, 0x0e, "DEBUG" },
};
unsigned int get_soc_major_rev(void)
{
@ -88,3 +125,14 @@ int arch_soc_init(void)
return 0;
}
int ls102xa_smmu_stream_id_init(void)
{
ls1021x_config_caam_stream_id(sec_liodn_tbl,
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
return 0;
}

2
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
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@ -9,4 +9,6 @@
unsigned int get_soc_major_rev(void);
int arch_soc_init(void);
int ls102xa_smmu_stream_id_init(void);
#endif /* __FSL_LS102XA_SOC_H */

42
board/freescale/ls1021aqds/ls1021aqds.c
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@ -10,7 +10,6 @@
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_sata.h>
@ -426,42 +425,6 @@ int misc_init_r(void)
return 0;
}
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
};
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
{ 0x108, 0x03, "ETSEC MAC3" },
{ 0x10c, 0x04, "PEX1" },
{ 0x110, 0x05, "PEX2" },
{ 0x114, 0x06, "qDMA" },
{ 0x118, 0x07, "SATA" },
{ 0x11c, 0x08, "USB3" },
{ 0x120, 0x09, "QE" },
{ 0x124, 0x0a, "eSDHC" },
{ 0x128, 0x0b, "eMA" },
{ 0x14c, 0x0c, "2D-ACE" },
{ 0x150, 0x0d, "USB2" },
{ 0x18c, 0x0e, "DEBUG" },
};
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@ -481,10 +444,7 @@ int board_init(void)
config_serdes_mux();
#endif
ls1021x_config_caam_stream_id(sec_liodn_tbl,
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
ls102xa_smmu_stream_id_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();

43
board/freescale/ls1021atwr/ls1021atwr.c
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@ -10,7 +10,6 @@
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_sata.h>
@ -448,43 +447,6 @@ void board_init_f(ulong dummy)
}
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
};
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
{ 0x108, 0x03, "ETSEC MAC3" },
{ 0x10c, 0x04, "PEX1" },
{ 0x110, 0x05, "PEX2" },
{ 0x114, 0x06, "qDMA" },
{ 0x118, 0x07, "SATA" },
{ 0x11c, 0x08, "USB3" },
{ 0x120, 0x09, "QE" },
{ 0x124, 0x0a, "eSDHC" },
{ 0x128, 0x0b, "eMA" },
{ 0x14c, 0x0c, "2D-ACE" },
{ 0x150, 0x0d, "USB2" },
{ 0x18c, 0x0e, "DEBUG" },
};
#ifdef CONFIG_DEEP_SLEEP
/* program the regulator (MC34VR500) to support deep sleep */
void ls1twr_program_regulator(void)
@ -525,10 +487,7 @@ int board_init(void)
#endif
#endif
ls1021x_config_caam_stream_id(sec_liodn_tbl,
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
ls102xa_smmu_stream_id_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();

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