Arndale board is based on samsung's exynos5250 soc. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>master
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#
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# Copyright (C) 2013 Samsung Electronics
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS += arndale_spl.o
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ifndef CONFIG_SPL_BUILD |
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COBJS += arndale.o
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endif |
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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ALL := $(obj).depend $(LIB)
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all: $(ALL) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,87 @@ |
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/*
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* Copyright (C) 2013 Samsung Electronics |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch/power.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_init(void) |
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{ |
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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int i; |
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u32 addr; |
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); |
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gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); |
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} |
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return 0; |
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} |
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int power_init_board(void) |
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{ |
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set_ps_hold_ctrl(); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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int i; |
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u32 addr, size; |
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); |
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size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); |
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gd->bd->bi_dram[i].start = addr; |
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gd->bd->bi_dram[i].size = size; |
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} |
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} |
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static int board_uart_init(void) |
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{ |
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int err = 0, uart_id; |
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for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { |
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err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); |
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if (err) { |
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debug("UART%d not configured\n", |
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(uart_id - PERIPH_ID_UART0)); |
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return err; |
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} |
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} |
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return err; |
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} |
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#ifdef CONFIG_BOARD_EARLY_INIT_F |
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int board_early_init_f(void) |
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{ |
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int err; |
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err = board_uart_init(); |
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if (err) { |
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debug("UART init failed\n"); |
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return err; |
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} |
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return err; |
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} |
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#endif |
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#ifdef CONFIG_DISPLAY_BOARDINFO |
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int checkboard(void) |
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{ |
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printf("\nBoard: Arndale\n"); |
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return 0; |
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} |
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#endif |
@ -0,0 +1,50 @@ |
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/*
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* Copyright (c) 2012 The Chromium OS Authors. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/spl.h> |
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#define SIGNATURE 0xdeadbeef |
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/* Parameters of early board initialization in SPL */ |
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static struct spl_machine_param machine_param |
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__attribute__((section(".machine_param"))) = { |
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.signature = SIGNATURE, |
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.version = 1, |
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.params = "vmubfasirM", |
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.size = sizeof(machine_param), |
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.mem_iv_size = 0x1f, |
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.mem_type = DDR_MODE_DDR3, |
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/*
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* Set uboot_size to 0x100000 bytes. |
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* |
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* This is an overly conservative value chosen to accommodate all |
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* possible U-Boot image. You are advised to set this value to a |
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* smaller realistic size via scripts that modifies the .machine_param |
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* section of output U-Boot image. |
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*/ |
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.uboot_size = 0x100000, |
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.boot_source = BOOT_MODE_OM, |
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.frequency_mhz = 800, |
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.arm_freq_mhz = 1000, |
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.serial_base = 0x12c30000, |
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.i2c_base = 0x12c60000, |
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.mem_manuf = MEM_MANUF_SAMSUNG, |
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}; |
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struct spl_machine_param *spl_get_machine_params(void) |
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{ |
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if (machine_param.signature != SIGNATURE) { |
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/* Will hang if SIGNATURE dont match */ |
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while (1) |
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; |
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} |
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return &machine_param; |
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} |
@ -0,0 +1,21 @@ |
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/* |
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* SAMSUNG Arndale board device tree source |
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* |
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* Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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/include/ ARCH_CPU_DTS |
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/ { |
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model = "SAMSUNG Arndale board based on EXYNOS5250"; |
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compatible = "samsung,arndale", "samsung,exynos5250"; |
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aliases { |
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serial0 = "/serial@12C20000"; |
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console = "/serial@12C20000"; |
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}; |
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}; |
@ -0,0 +1,255 @@ |
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/*
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* Copyright (C) 2013 Samsung Electronics |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Configuration settings for the SAMSUNG Arndale board. |
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*/ |
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#ifndef __CONFIG_ARNDALE_H |
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#define __CONFIG_ARNDALE_H |
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/* High Level Configuration Options */ |
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */ |
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#define CONFIG_S5P /* S5P Family */ |
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#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ |
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#define CONFIG_EXYNOS5250 |
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#include <asm/arch/cpu.h> /* get chip and board defs */ |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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/* Enable fdt support for Exynos5250 */ |
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#define CONFIG_ARCH_DEVICE_TREE exynos5250 |
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#define CONFIG_OF_CONTROL |
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#define CONFIG_OF_SEPARATE |
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/* Allow tracing to be enabled */ |
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#define CONFIG_TRACE |
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#define CONFIG_CMD_TRACE |
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#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) |
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#define CONFIG_TRACE_EARLY_SIZE (8 << 20) |
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#define CONFIG_TRACE_EARLY |
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#define CONFIG_TRACE_EARLY_ADDR 0x50000000 |
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/* Keep L2 Cache Disabled */ |
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#define CONFIG_SYS_DCACHE_OFF |
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#define CONFIG_SYS_SDRAM_BASE 0x40000000 |
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#define CONFIG_SYS_TEXT_BASE 0x43E00000 |
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/* input clock of PLL: SMDK5250 has 24MHz input clock */ |
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#define CONFIG_SYS_CLK_FREQ 24000000 |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_CMDLINE_EDITING |
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/* Power Down Modes */ |
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#define S5P_CHECK_SLEEP 0x00000BAD |
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#define S5P_CHECK_DIDLE 0xBAD00000 |
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#define S5P_CHECK_LPA 0xABAD0000 |
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/* Offset for inform registers */ |
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#define INFORM0_OFFSET 0x800 |
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#define INFORM1_OFFSET 0x804 |
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/* Size of malloc() pool */ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) |
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/* select serial console configuration */ |
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#define CONFIG_BAUDRATE 115200 |
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#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 |
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#define CONFIG_SILENT_CONSOLE |
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/* Console configuration */ |
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#define CONFIG_CONSOLE_MUX |
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
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#define EXYNOS_DEVICE_SETTINGS \ |
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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EXYNOS_DEVICE_SETTINGS |
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/* SD/MMC configuration */ |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_MMC |
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#define CONFIG_SDHCI |
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#define CONFIG_S5P_SDHCI |
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#define CONFIG_DWMMC |
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#define CONFIG_EXYNOS_DWMMC |
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#define CONFIG_SUPPORT_EMMC_BOOT |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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/* PWM */ |
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#define CONFIG_PWM |
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/* allow to overwrite serial and ethaddr */ |
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#define CONFIG_ENV_OVERWRITE |
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/* Command definition*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_MMC |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_HASH |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_ZERO_BOOTDELAY_CHECK |
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/* USB */ |
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#define CONFIG_CMD_USB |
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#define CONFIG_USB_EHCI |
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#define CONFIG_USB_EHCI_EXYNOS |
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#define CONFIG_USB_STORAGE |
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/* MMC SPL */ |
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#define CONFIG_SPL |
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#define COPY_BL2_FNPTR_ADDR 0x02020030 |
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#define CONFIG_SPL_LIBCOMMON_SUPPORT |
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/* specific .lds file */ |
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#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" |
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#define CONFIG_SPL_TEXT_BASE 0x02023400 |
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#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
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#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
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#define CONFIG_SYS_PROMPT "ARNDALE # " |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
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/* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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/* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) |
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_RD_LVL |
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#define CONFIG_NR_DRAM_BANKS 8 |
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ |
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) |
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE |
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) |
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE |
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#define CONFIG_SYS_MONITOR_BASE 0x00000000 |
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/* FLASH and environment organization */ |
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#define CONFIG_SYS_NO_FLASH |
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#undef CONFIG_CMD_IMLS |
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#define CONFIG_IDENT_STRING " for ARNDALE" |
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#define CONFIG_SYS_MMC_ENV_DEV 0 |
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#define CONFIG_ENV_IS_IN_MMC |
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#define CONFIG_SECURE_BL1_ONLY |
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/* Secure FW size configuration */ |
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#ifdef CONFIG_SECURE_BL1_ONLY |
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#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ |
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#else |
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#define CONFIG_SEC_FW_SIZE 0 |
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#endif |
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/* Configuration of BL1, BL2, ENV Blocks on mmc */ |
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#define CONFIG_RES_BLOCK_SIZE (512) |
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#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ |
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#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ |
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ |
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#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) |
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#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) |
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#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) |
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/* U-boot copy size from boot Media to DRAM.*/ |
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#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) |
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#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) |
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#define CONFIG_SPI_BOOTING |
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#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
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#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_EFI_PARTITION |
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#define CONFIG_CMD_PART |
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#define CONFIG_PARTITION_UUIDS |
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#define CONFIG_IRAM_STACK 0x02050000 |
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK |
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/* I2C */ |
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#define CONFIG_SYS_I2C_INIT_BOARD |
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#define CONFIG_HARD_I2C |
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#define CONFIG_CMD_I2C |
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ |
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#define CONFIG_DRIVER_S3C24X0_I2C |
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#define CONFIG_I2C_MULTI_BUS |
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#define CONFIG_MAX_I2C_NUM 8 |
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#define CONFIG_SYS_I2C_SLAVE 0x0 |
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#define CONFIG_I2C_EDID |
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/* PMIC */ |
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#define CONFIG_PMIC |
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#define CONFIG_PMIC_I2C |
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#define CONFIG_PMIC_MAX77686 |
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#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale |
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/* Ethernet Controllor Driver */ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_SMC911X |
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#define CONFIG_SMC911X_BASE 0x5000000 |
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#define CONFIG_SMC911X_16_BIT |
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#define CONFIG_ENV_SROM_BANK 1 |
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#endif /*CONFIG_CMD_NET*/ |
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/* Enable PXE Support */ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_CMD_PXE |
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#define CONFIG_MENU |
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#endif |
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/* Enable devicetree support */ |
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#define CONFIG_OF_LIBFDT |
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/* Enable Time Command */ |
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#define CONFIG_CMD_TIME |
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#endif /* __CONFIG_H */ |
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Reference in new issue