This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ |
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#define __SOC_ROCKCHIP_RK3399_GRF_H__ |
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struct rk3399_grf_regs { |
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u32 reserved[0x800]; |
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u32 usb3_perf_con0; |
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u32 usb3_perf_con1; |
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u32 usb3_perf_con2; |
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u32 usb3_perf_rd_max_latency_num; |
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u32 usb3_perf_rd_latency_samp_num; |
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u32 usb3_perf_rd_latency_acc_num; |
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u32 usb3_perf_rd_axi_total_byte; |
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u32 usb3_perf_wr_axi_total_byte; |
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u32 usb3_perf_working_cnt; |
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u32 reserved1[0x103]; |
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u32 usb3otg0_con0; |
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u32 usb3otg0_con1; |
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u32 reserved2[2]; |
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u32 usb3otg1_con0; |
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u32 usb3otg1_con1; |
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u32 reserved3[2]; |
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u32 usb3otg0_status_lat0; |
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u32 usb3otg0_status_lat1; |
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u32 usb3otg0_status_cb; |
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u32 reserved4; |
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u32 usb3otg1_status_lat0; |
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u32 usb3otg1_status_lat1; |
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u32 usb3ogt1_status_cb; |
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u32 reserved5[0x6e5]; |
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u32 pcie_perf_con0; |
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u32 pcie_perf_con1; |
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u32 pcie_perf_con2; |
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u32 pcie_perf_rd_max_latency_num; |
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u32 pcie_perf_rd_latency_samp_num; |
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u32 pcie_perf_rd_laterncy_acc_num; |
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u32 pcie_perf_rd_axi_total_byte; |
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u32 pcie_perf_wr_axi_total_byte; |
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u32 pcie_perf_working_cnt; |
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u32 reserved6[0x37]; |
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u32 usb20_host0_con0; |
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u32 usb20_host0_con1; |
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u32 reserved7[2]; |
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u32 usb20_host1_con0; |
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u32 usb20_host1_con1; |
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u32 reserved8[2]; |
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u32 hsic_con0; |
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u32 hsic_con1; |
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u32 reserved9[6]; |
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u32 grf_usbhost0_status; |
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u32 grf_usbhost1_Status; |
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u32 grf_hsic_status; |
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u32 reserved10[0xc9]; |
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u32 hsicphy_con0; |
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u32 reserved11[3]; |
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u32 usbphy0_ctrl[26]; |
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u32 reserved12[6]; |
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u32 usbphy1[26]; |
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u32 reserved13[0x72f]; |
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u32 soc_con9; |
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u32 reserved14[0x0a]; |
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u32 soc_con20; |
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u32 soc_con21; |
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u32 soc_con22; |
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u32 soc_con23; |
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u32 soc_con24; |
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u32 soc_con25; |
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u32 soc_con26; |
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u32 reserved15[0xf65]; |
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u32 cpu_con[4]; |
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u32 reserved16[0x1c]; |
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u32 cpu_status[6]; |
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u32 reserved17[0x1a]; |
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u32 a53_perf_con[4]; |
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u32 a53_perf_rd_mon_st; |
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u32 a53_perf_rd_mon_end; |
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u32 a53_perf_wr_mon_st; |
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u32 a53_perf_wr_mon_end; |
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u32 a53_perf_rd_max_latency_num; |
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u32 a53_perf_rd_latency_samp_num; |
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u32 a53_perf_rd_laterncy_acc_num; |
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u32 a53_perf_rd_axi_total_byte; |
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u32 a53_perf_wr_axi_total_byte; |
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u32 a53_perf_working_cnt; |
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u32 a53_perf_int_status; |
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u32 reserved18[0x31]; |
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u32 a72_perf_con[4]; |
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u32 a72_perf_rd_mon_st; |
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u32 a72_perf_rd_mon_end; |
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u32 a72_perf_wr_mon_st; |
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u32 a72_perf_wr_mon_end; |
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u32 a72_perf_rd_max_latency_num; |
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u32 a72_perf_rd_latency_samp_num; |
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u32 a72_perf_rd_laterncy_acc_num; |
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u32 a72_perf_rd_axi_total_byte; |
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u32 a72_perf_wr_axi_total_byte; |
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u32 a72_perf_working_cnt; |
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u32 a72_perf_int_status; |
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u32 reserved19[0x7f6]; |
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u32 soc_con5; |
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u32 soc_con6; |
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u32 reserved20[0x779]; |
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u32 gpio2a_iomux; |
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union { |
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u32 iomux_spi2; |
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u32 gpio2b_iomux; |
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}; |
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union { |
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u32 gpio2c_iomux; |
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u32 iomux_spi5; |
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}; |
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u32 gpio2d_iomux; |
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union { |
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u32 gpio3a_iomux; |
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u32 iomux_spi0; |
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}; |
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u32 gpio3b_iomux; |
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u32 gpio3c_iomux; |
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union { |
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u32 iomux_i2s0; |
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u32 gpio3d_iomux; |
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}; |
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union { |
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u32 iomux_i2sclk; |
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u32 gpio4a_iomux; |
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}; |
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union { |
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u32 iomux_sdmmc; |
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u32 iomux_uart2a; |
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u32 gpio4b_iomux; |
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}; |
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union { |
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u32 iomux_pwm_0; |
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u32 iomux_pwm_1; |
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u32 iomux_uart2b; |
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u32 iomux_uart2c; |
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u32 iomux_edp_hotplug; |
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u32 gpio4c_iomux; |
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}; |
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u32 gpio4d_iomux; |
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u32 reserved21[4]; |
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u32 gpio2_p[3][4]; |
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u32 reserved22[4]; |
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u32 gpio2_sr[3][4]; |
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u32 reserved23[4]; |
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u32 gpio2_smt[3][4]; |
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u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; |
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u32 gpio4b_e01; |
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u32 gpio4b_e2; |
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u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; |
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u32 soc_con0; |
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u32 soc_con1; |
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u32 soc_con2; |
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u32 soc_con3; |
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u32 soc_con4; |
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u32 soc_con5_pcie; |
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u32 reserved25; |
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u32 soc_con7; |
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u32 soc_con8; |
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u32 soc_con9_pcie; |
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u32 reserved26[0x1e]; |
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u32 soc_status[6]; |
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u32 reserved27[0x32]; |
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u32 ddrc0_con0; |
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u32 ddrc0_con1; |
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u32 ddrc1_con0; |
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u32 ddrc1_con1; |
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u32 reserved28[0xac]; |
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u32 io_vsel; |
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u32 saradc_testbit; |
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u32 tsadc_testbit_l; |
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u32 tsadc_testbit_h; |
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u32 reserved29[0x6c]; |
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u32 chip_id_addr; |
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u32 reserved30[0x1f]; |
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u32 fast_boot_addr; |
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u32 reserved31[0x1df]; |
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u32 emmccore_con[12]; |
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u32 reserved32[4]; |
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u32 emmccore_status[4]; |
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u32 reserved33[0x1cc]; |
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u32 emmcphy_con[7]; |
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u32 reserved34; |
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u32 emmcphy_status; |
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}; |
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check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); |
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struct rk3399_pmugrf_regs { |
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union { |
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u32 iomux_pwm_3a; |
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u32 gpio0a_iomux; |
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}; |
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u32 gpio0b_iomux; |
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u32 reserved0[2]; |
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union { |
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u32 spi1_rxd; |
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u32 tsadc_int; |
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u32 gpio1a_iomux; |
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}; |
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union { |
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u32 spi1_csclktx; |
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u32 iomux_pwm_3b; |
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u32 iomux_i2c0_sda; |
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u32 gpio1b_iomux; |
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}; |
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union { |
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u32 iomux_pwm_2; |
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u32 iomux_i2c0_scl; |
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u32 gpio1c_iomux; |
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}; |
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u32 gpio1d_iomux; |
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u32 reserved1[8]; |
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u32 gpio0_p[2][4]; |
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u32 reserved3[8]; |
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u32 gpio0a_e; |
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u32 reserved4; |
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u32 gpio0b_e; |
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u32 reserved5[5]; |
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u32 gpio1a_e; |
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u32 reserved6; |
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u32 gpio1b_e; |
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u32 reserved7; |
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u32 gpio1c_e; |
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u32 reserved8; |
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u32 gpio1d_e; |
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u32 reserved9[0x11]; |
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u32 gpio0l_sr; |
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u32 reserved10; |
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u32 gpio1l_sr; |
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u32 gpio1h_sr; |
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u32 reserved11[4]; |
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u32 gpio0a_smt; |
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u32 gpio0b_smt; |
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u32 reserved12[2]; |
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u32 gpio1a_smt; |
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u32 gpio1b_smt; |
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u32 gpio1c_smt; |
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u32 gpio1d_smt; |
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u32 reserved13[8]; |
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u32 gpio0l_he; |
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u32 reserved14; |
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u32 gpio1l_he; |
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u32 gpio1h_he; |
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u32 reserved15[4]; |
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u32 soc_con0; |
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u32 reserved16[9]; |
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u32 soc_con10; |
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u32 soc_con11; |
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u32 reserved17[0x24]; |
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u32 pmupvtm_con0; |
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u32 pmupvtm_con1; |
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u32 pmupvtm_status0; |
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u32 pmupvtm_status1; |
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u32 grf_osc_e; |
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u32 reserved18[0x2b]; |
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u32 os_reg0; |
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u32 os_reg1; |
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u32 os_reg2; |
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u32 os_reg3; |
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}; |
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check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); |
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struct rk3399_pmusgrf_regs { |
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u32 ddr_rgn_con[35]; |
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u32 reserved[0x1fe5]; |
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u32 soc_con8; |
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u32 soc_con9; |
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u32 soc_con10; |
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u32 soc_con11; |
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u32 soc_con12; |
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u32 soc_con13; |
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u32 soc_con14; |
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u32 soc_con15; |
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u32 reserved1[3]; |
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u32 soc_con19; |
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u32 soc_con20; |
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u32 soc_con21; |
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u32 soc_con22; |
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u32 reserved2[0x29]; |
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u32 perilp_con[9]; |
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u32 reserved4[7]; |
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u32 perilp_status; |
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u32 reserved5[0xfaf]; |
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u32 soc_con0; |
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u32 soc_con1; |
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u32 reserved6[0x3e]; |
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u32 pmu_con[9]; |
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u32 reserved7[0x17]; |
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u32 fast_boot_addr; |
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u32 reserved8[0x1f]; |
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u32 efuse_prg_mask; |
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u32 efuse_read_mask; |
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u32 reserved9[0x0e]; |
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u32 pmu_slv_con0; |
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u32 pmu_slv_con1; |
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u32 reserved10[0x771]; |
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u32 soc_con3; |
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u32 soc_con4; |
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u32 soc_con5; |
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u32 soc_con6; |
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u32 soc_con7; |
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u32 reserved11[8]; |
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u32 soc_con16; |
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u32 soc_con17; |
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u32 soc_con18; |
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u32 reserved12[0xdd]; |
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u32 slv_secure_con0; |
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u32 slv_secure_con1; |
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u32 reserved13; |
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u32 slv_secure_con2; |
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u32 slv_secure_con3; |
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u32 slv_secure_con4; |
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}; |
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check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); |
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#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ |
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <asm/io.h> |
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#include <asm/arch/grf_rk3399.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/periph.h> |
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#include <asm/arch/clock.h> |
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#include <dm/pinctrl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct rk3399_pinctrl_priv { |
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struct rk3399_grf_regs *grf; |
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struct rk3399_pmugrf_regs *pmugrf; |
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}; |
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enum { |
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/* GRF_GPIO2B_IOMUX */ |
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GRF_GPIO2B1_SEL_SHIFT = 0, |
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GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, |
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GRF_SPI2TPM_RXD = 1, |
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GRF_GPIO2B2_SEL_SHIFT = 2, |
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GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, |
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GRF_SPI2TPM_TXD = 1, |
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GRF_GPIO2B3_SEL_SHIFT = 6, |
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GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, |
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GRF_SPI2TPM_CLK = 1, |
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GRF_GPIO2B4_SEL_SHIFT = 8, |
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GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, |
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GRF_SPI2TPM_CSN0 = 1, |
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/* GRF_GPIO3A_IOMUX */ |
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GRF_GPIO3A4_SEL_SHIFT = 8, |
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GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, |
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GRF_SPI0NORCODEC_RXD = 2, |
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GRF_GPIO3A5_SEL_SHIFT = 10, |
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GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, |
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GRF_SPI0NORCODEC_TXD = 2, |
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GRF_GPIO3A6_SEL_SHIFT = 12, |
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GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, |
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GRF_SPI0NORCODEC_CLK = 2, |
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GRF_GPIO3A7_SEL_SHIFT = 14, |
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GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, |
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GRF_SPI0NORCODEC_CSN0 = 2, |
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/* GRF_GPIO3B_IOMUX */ |
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GRF_GPIO3B0_SEL_SHIFT = 0, |
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GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, |
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GRF_SPI0NORCODEC_CSN1 = 2, |
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/* GRF_GPIO4B_IOMUX */ |
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GRF_GPIO4B0_SEL_SHIFT = 0, |
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GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, |
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GRF_SDMMC_DATA0 = 1, |
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GRF_UART2DBGA_SIN = 2, |
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GRF_GPIO4B1_SEL_SHIFT = 2, |
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GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, |
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GRF_SDMMC_DATA1 = 1, |
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GRF_UART2DBGA_SOUT = 2, |
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GRF_GPIO4B2_SEL_SHIFT = 4, |
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GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, |
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GRF_SDMMC_DATA2 = 1, |
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GRF_GPIO4B3_SEL_SHIFT = 6, |
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GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, |
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GRF_SDMMC_DATA3 = 1, |
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GRF_GPIO4B4_SEL_SHIFT = 8, |
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GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, |
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GRF_SDMMC_CLKOUT = 1, |
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GRF_GPIO4B5_SEL_SHIFT = 10, |
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GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, |
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GRF_SDMMC_CMD = 1, |
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/* GRF_GPIO4C_IOMUX */ |
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GRF_GPIO4C2_SEL_SHIFT = 4, |
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GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, |
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GRF_PWM_0 = 1, |
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GRF_GPIO4C3_SEL_SHIFT = 6, |
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GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, |
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GRF_UART2DGBC_SIN = 1, |
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GRF_GPIO4C4_SEL_SHIFT = 8, |
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GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, |
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GRF_UART2DBGC_SOUT = 1, |
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GRF_GPIO4C6_SEL_SHIFT = 12, |
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GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, |
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GRF_PWM_1 = 1, |
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/* PMUGRF_GPIO0A_IOMUX */ |
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PMUGRF_GPIO0A6_SEL_SHIFT = 12, |
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PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, |
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PMUGRF_PWM_3A = 1, |
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/* PMUGRF_GPIO1A_IOMUX */ |
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PMUGRF_GPIO1A7_SEL_SHIFT = 14, |
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PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, |
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PMUGRF_SPI1EC_RXD = 2, |
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/* PMUGRF_GPIO1B_IOMUX */ |
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PMUGRF_GPIO1B0_SEL_SHIFT = 0, |
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PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, |
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PMUGRF_SPI1EC_TXD = 2, |
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PMUGRF_GPIO1B1_SEL_SHIFT = 2, |
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PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, |
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PMUGRF_SPI1EC_CLK = 2, |
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PMUGRF_GPIO1B2_SEL_SHIFT = 4, |
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PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, |
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PMUGRF_SPI1EC_CSN0 = 2, |
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PMUGRF_GPIO1B6_SEL_SHIFT = 12, |
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PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, |
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PMUGRF_PWM_3B = 1, |
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PMUGRF_GPIO1B7_SEL_SHIFT = 14, |
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PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, |
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PMUGRF_I2C0PMU_SDA = 2, |
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/* PMUGRF_GPIO1C_IOMUX */ |
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PMUGRF_GPIO1C0_SEL_SHIFT = 0, |
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PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, |
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PMUGRF_I2C0PMU_SCL = 2, |
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PMUGRF_GPIO1C3_SEL_SHIFT = 6, |
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PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, |
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PMUGRF_PWM_2 = 1, |
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}; |
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static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, |
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struct rk3399_pmugrf_regs *pmugrf, int pwm_id) |
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{ |
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switch (pwm_id) { |
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case PERIPH_ID_PWM0: |
||||
rk_clrsetreg(&grf->gpio4c_iomux, |
||||
GRF_GPIO4C2_SEL_MASK, |
||||
GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_PWM1: |
||||
rk_clrsetreg(&grf->gpio4c_iomux, |
||||
GRF_GPIO4C6_SEL_MASK, |
||||
GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_PWM2: |
||||
rk_clrsetreg(&pmugrf->gpio1c_iomux, |
||||
PMUGRF_GPIO1C3_SEL_MASK, |
||||
PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_PWM3: |
||||
if (readl(&pmugrf->soc_con0) & (1 << 5)) |
||||
rk_clrsetreg(&pmugrf->gpio1b_iomux, |
||||
PMUGRF_GPIO1B6_SEL_MASK, |
||||
PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT); |
||||
else |
||||
rk_clrsetreg(&pmugrf->gpio0a_iomux, |
||||
PMUGRF_GPIO0A6_SEL_MASK, |
||||
PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT); |
||||
break; |
||||
default: |
||||
debug("pwm id = %d iomux error!\n", pwm_id); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, |
||||
struct rk3399_pmugrf_regs *pmugrf, |
||||
int i2c_id) |
||||
{ |
||||
switch (i2c_id) { |
||||
case PERIPH_ID_I2C0: |
||||
rk_clrsetreg(&pmugrf->gpio1b_iomux, |
||||
PMUGRF_GPIO1B7_SEL_MASK, |
||||
PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT); |
||||
rk_clrsetreg(&pmugrf->gpio1c_iomux, |
||||
PMUGRF_GPIO1C0_SEL_MASK, |
||||
PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_I2C1: |
||||
case PERIPH_ID_I2C2: |
||||
case PERIPH_ID_I2C3: |
||||
case PERIPH_ID_I2C4: |
||||
case PERIPH_ID_I2C5: |
||||
default: |
||||
debug("i2c id = %d iomux error!\n", i2c_id); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id) |
||||
{ |
||||
switch (lcd_id) { |
||||
case PERIPH_ID_LCDC0: |
||||
break; |
||||
default: |
||||
debug("lcdc id = %d iomux error!\n", lcd_id); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, |
||||
struct rk3399_pmugrf_regs *pmugrf, |
||||
enum periph_id spi_id, int cs) |
||||
{ |
||||
switch (spi_id) { |
||||
case PERIPH_ID_SPI0: |
||||
switch (cs) { |
||||
case 0: |
||||
rk_clrsetreg(&grf->gpio3a_iomux, |
||||
GRF_GPIO3A7_SEL_MASK, |
||||
GRF_SPI0NORCODEC_CSN0 |
||||
<< GRF_GPIO3A7_SEL_SHIFT); |
||||
break; |
||||
case 1: |
||||
rk_clrsetreg(&grf->gpio3b_iomux, |
||||
GRF_GPIO3B0_SEL_MASK, |
||||
GRF_SPI0NORCODEC_CSN1 |
||||
<< GRF_GPIO3B0_SEL_SHIFT); |
||||
break; |
||||
default: |
||||
goto err; |
||||
} |
||||
rk_clrsetreg(&grf->gpio3a_iomux, |
||||
GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT |
||||
| GRF_GPIO3A6_SEL_SHIFT, |
||||
GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT |
||||
| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT |
||||
| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SPI1: |
||||
if (cs != 0) |
||||
goto err; |
||||
rk_clrsetreg(&pmugrf->gpio1a_iomux, |
||||
PMUGRF_GPIO1A7_SEL_MASK, |
||||
PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT); |
||||
rk_clrsetreg(&pmugrf->gpio1b_iomux, |
||||
PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK |
||||
| PMUGRF_GPIO1B2_SEL_MASK, |
||||
PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT |
||||
| PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT |
||||
| PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_SPI2: |
||||
if (cs != 0) |
||||
goto err; |
||||
rk_clrsetreg(&grf->gpio2b_iomux, |
||||
GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK |
||||
| GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK, |
||||
GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT |
||||
| GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT |
||||
| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT |
||||
| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); |
||||
break; |
||||
default: |
||||
goto err; |
||||
} |
||||
|
||||
return 0; |
||||
err: |
||||
debug("rkspi: periph%d cs=%d not supported", spi_id, cs); |
||||
return -ENOENT; |
||||
} |
||||
|
||||
static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf, |
||||
struct rk3399_pmugrf_regs *pmugrf, |
||||
int uart_id) |
||||
{ |
||||
switch (uart_id) { |
||||
case PERIPH_ID_UART2: |
||||
/* Using channel-C by default */ |
||||
rk_clrsetreg(&grf->gpio4c_iomux, |
||||
GRF_GPIO4C3_SEL_MASK, |
||||
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); |
||||
rk_clrsetreg(&grf->gpio4c_iomux, |
||||
GRF_GPIO4C4_SEL_MASK, |
||||
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); |
||||
break; |
||||
case PERIPH_ID_UART0: |
||||
case PERIPH_ID_UART1: |
||||
case PERIPH_ID_UART3: |
||||
case PERIPH_ID_UART4: |
||||
default: |
||||
debug("uart id = %d iomux error!\n", uart_id); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) |
||||
{ |
||||
switch (mmc_id) { |
||||
case PERIPH_ID_EMMC: |
||||
break; |
||||
case PERIPH_ID_SDCARD: |
||||
rk_clrsetreg(&grf->gpio4b_iomux, |
||||
GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK |
||||
| GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK |
||||
| GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK, |
||||
GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT |
||||
| GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT |
||||
| GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT |
||||
| GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT |
||||
| GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT |
||||
| GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT); |
||||
break; |
||||
default: |
||||
debug("mmc id = %d iomux error!\n", mmc_id); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) |
||||
{ |
||||
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); |
||||
|
||||
debug("%s: func=%x, flags=%x\n", __func__, func, flags); |
||||
switch (func) { |
||||
case PERIPH_ID_PWM0: |
||||
case PERIPH_ID_PWM1: |
||||
case PERIPH_ID_PWM2: |
||||
case PERIPH_ID_PWM3: |
||||
case PERIPH_ID_PWM4: |
||||
pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func); |
||||
break; |
||||
case PERIPH_ID_I2C0: |
||||
case PERIPH_ID_I2C1: |
||||
case PERIPH_ID_I2C2: |
||||
case PERIPH_ID_I2C3: |
||||
case PERIPH_ID_I2C4: |
||||
case PERIPH_ID_I2C5: |
||||
pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); |
||||
break; |
||||
case PERIPH_ID_SPI0: |
||||
case PERIPH_ID_SPI1: |
||||
case PERIPH_ID_SPI2: |
||||
pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); |
||||
break; |
||||
case PERIPH_ID_UART0: |
||||
case PERIPH_ID_UART1: |
||||
case PERIPH_ID_UART2: |
||||
case PERIPH_ID_UART3: |
||||
case PERIPH_ID_UART4: |
||||
pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func); |
||||
break; |
||||
case PERIPH_ID_LCDC0: |
||||
case PERIPH_ID_LCDC1: |
||||
pinctrl_rk3399_lcdc_config(priv->grf, func); |
||||
break; |
||||
case PERIPH_ID_SDMMC0: |
||||
case PERIPH_ID_SDMMC1: |
||||
pinctrl_rk3399_sdmmc_config(priv->grf, func); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rk3399_pinctrl_get_periph_id(struct udevice *dev, |
||||
struct udevice *periph) |
||||
{ |
||||
u32 cell[3]; |
||||
int ret; |
||||
|
||||
ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, |
||||
"interrupts", cell, ARRAY_SIZE(cell)); |
||||
if (ret < 0) |
||||
return -EINVAL; |
||||
|
||||
switch (cell[1]) { |
||||
case 68: |
||||
return PERIPH_ID_SPI0; |
||||
case 53: |
||||
return PERIPH_ID_SPI1; |
||||
case 52: |
||||
return PERIPH_ID_SPI2; |
||||
case 57: |
||||
return PERIPH_ID_I2C0; |
||||
case 59: /* Note strange order */ |
||||
return PERIPH_ID_I2C1; |
||||
case 35: |
||||
return PERIPH_ID_I2C2; |
||||
case 34: |
||||
return PERIPH_ID_I2C3; |
||||
case 56: |
||||
return PERIPH_ID_I2C4; |
||||
case 38: |
||||
return PERIPH_ID_I2C5; |
||||
case 65: |
||||
return PERIPH_ID_SDMMC1; |
||||
} |
||||
|
||||
return -ENOENT; |
||||
} |
||||
|
||||
static int rk3399_pinctrl_set_state_simple(struct udevice *dev, |
||||
struct udevice *periph) |
||||
{ |
||||
int func; |
||||
|
||||
func = rk3399_pinctrl_get_periph_id(dev, periph); |
||||
if (func < 0) |
||||
return func; |
||||
|
||||
return rk3399_pinctrl_request(dev, func, 0); |
||||
} |
||||
|
||||
static struct pinctrl_ops rk3399_pinctrl_ops = { |
||||
.set_state_simple = rk3399_pinctrl_set_state_simple, |
||||
.request = rk3399_pinctrl_request, |
||||
.get_periph_id = rk3399_pinctrl_get_periph_id, |
||||
}; |
||||
|
||||
static int rk3399_pinctrl_probe(struct udevice *dev) |
||||
{ |
||||
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); |
||||
int ret = 0; |
||||
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
||||
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
||||
debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static const struct udevice_id rk3399_pinctrl_ids[] = { |
||||
{ .compatible = "rockchip,rk3399-pinctrl" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(pinctrl_rk3399) = { |
||||
.name = "rockchip_rk3399_pinctrl", |
||||
.id = UCLASS_PINCTRL, |
||||
.of_match = rk3399_pinctrl_ids, |
||||
.priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), |
||||
.ops = &rk3399_pinctrl_ops, |
||||
.bind = dm_scan_fdt_dev, |
||||
.probe = rk3399_pinctrl_probe, |
||||
}; |
Loading…
Reference in new issue