Tom Rini
7 years ago
commit
a375ff8e14
@ -1,194 +0,0 @@ |
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/* |
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* Copyright 2016 Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ or X11 |
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*/ |
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#include "imx7d-pinfunc.h" |
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#include "skeleton.dtsi" |
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|
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/ { |
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aliases { |
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gpio0 = &gpio1; |
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gpio1 = &gpio2; |
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gpio2 = &gpio3; |
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gpio3 = &gpio4; |
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gpio4 = &gpio5; |
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gpio5 = &gpio6; |
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gpio6 = &gpio7; |
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i2c0 = &i2c1; |
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i2c1 = &i2c2; |
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i2c2 = &i2c3; |
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i2c3 = &i2c4; |
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serial0 = &uart1; |
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serial1 = &uart2; |
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serial2 = &uart3; |
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serial3 = &uart4; |
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serial4 = &uart5; |
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serial5 = &uart6; |
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serial6 = &uart7; |
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}; |
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|
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges; |
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|
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aips1: aips-bus@30000000 { |
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compatible = "fsl,aips-bus", "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x30000000 0x400000>; |
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ranges; |
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|
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gpio1: gpio@30200000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30200000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio2: gpio@30210000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30210000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio3: gpio@30220000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30220000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio4: gpio@30230000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30230000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio5: gpio@30240000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30240000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio6: gpio@30250000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30250000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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gpio7: gpio@30260000 { |
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
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reg = <0x30260000 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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|
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iomuxc_lpsr: iomuxc-lpsr@302c0000 { |
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compatible = "fsl,imx7d-iomuxc-lpsr"; |
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reg = <0x302c0000 0x10000>; |
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fsl,input-sel = <&iomuxc>; |
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}; |
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|
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iomuxc: iomuxc@30330000 { |
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compatible = "fsl,imx7d-iomuxc"; |
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reg = <0x30330000 0x10000>; |
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}; |
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}; |
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|
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aips3: aips-bus@30800000 { |
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compatible = "fsl,aips-bus", "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x30800000 0x400000>; |
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ranges; |
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|
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uart1: serial@30860000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30860000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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uart2: serial@30890000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30890000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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uart3: serial@30880000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30880000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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i2c1: i2c@30a20000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
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reg = <0x30a20000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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i2c2: i2c@30a30000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
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reg = <0x30a30000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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i2c3: i2c@30a40000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
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reg = <0x30a40000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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i2c4: i2c@30a50000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
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reg = <0x30a50000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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uart4: serial@30a60000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30a60000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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uart5: serial@30a70000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30a70000 0x10000>; |
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status = "disabled"; |
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}; |
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|
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uart6: serial@30a80000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30a80000 0x10000>; |
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status = "disabled"; |
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}; |
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uart7: serial@30a90000 { |
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compatible = "fsl,imx7d-uart", |
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"fsl,imx6q-uart"; |
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reg = <0x30a90000 0x10000>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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}; |
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@ -0,0 +1,309 @@ |
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/* |
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* Copyright 2017 NXP |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "imx7d.dtsi" |
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/ { |
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model = "Freescale i.MX7 SabreSD Board"; |
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compatible = "fsl,imx7d-sdb", "fsl,imx7d"; |
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|
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memory { |
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reg = <0x80000000 0x80000000>; |
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}; |
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|
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spi4 { |
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compatible = "spi-gpio"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_spi1>; |
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status = "okay"; |
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gpio-sck = <&gpio1 13 0>; |
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gpio-mosi = <&gpio1 9 0>; |
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cs-gpios = <&gpio1 12 0>; |
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num-chipselects = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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gpio_spi: gpio_spi@0 { |
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compatible = "fairchild,74hc595"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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reg = <0>; |
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registers-number = <1>; |
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registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ |
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spi-max-frequency = <100000>; |
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}; |
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}; |
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|
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regulators { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg_usb_otg1_vbus: regulator@0 { |
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compatible = "regulator-fixed"; |
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reg = <0>; |
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regulator-name = "usb_otg1_vbus"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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reg_usb_otg2_vbus: regulator@1 { |
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compatible = "regulator-fixed"; |
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reg = <1>; |
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regulator-name = "usb_otg2_vbus"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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reg_sd1_vmmc: regulator@3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "VDD_SD1"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
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startup-delay-us = <200000>; |
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enable-active-high; |
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}; |
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}; |
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}; |
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|
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&iomuxc { |
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imx7d-sdb { |
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pinctrl_spi1: spi1grp { |
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fsl,pins = < |
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 |
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 |
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 |
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>; |
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}; |
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|
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pinctrl_i2c1: i2c1grp { |
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fsl,pins = < |
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f |
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MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f |
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>; |
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}; |
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pinctrl_i2c2: i2c2grp { |
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fsl,pins = < |
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f |
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f |
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>; |
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}; |
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|
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pinctrl_i2c3: i2c3grp { |
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fsl,pins = < |
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MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f |
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MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f |
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>; |
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}; |
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|
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pinctrl_i2c4: i2c4grp { |
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fsl,pins = < |
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f |
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MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f |
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>; |
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}; |
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|
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pinctrl_usdhc1_gpio: usdhc1_gpiogrp { |
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fsl,pins = < |
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ |
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MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ |
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ |
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MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ |
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>; |
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}; |
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|
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pinctrl_usdhc1: usdhc1grp { |
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fsl,pins = < |
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MX7D_PAD_SD1_CMD__SD1_CMD 0x59 |
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MX7D_PAD_SD1_CLK__SD1_CLK 0x19 |
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 |
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 |
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 |
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 |
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>; |
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}; |
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|
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pinctrl_usdhc2: usdhc2grp { |
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fsl,pins = < |
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MX7D_PAD_SD2_CMD__SD2_CMD 0x59 |
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MX7D_PAD_SD2_CLK__SD2_CLK 0x19 |
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MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 |
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MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 |
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MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 |
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MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 |
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MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ |
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MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ |
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>; |
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}; |
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|
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pinctrl_usdhc3: usdhc3grp { |
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fsl,pins = < |
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
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MX7D_PAD_SD3_CLK__SD3_CLK 0x19 |
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 |
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 |
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 |
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 |
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 |
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>; |
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}; |
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}; |
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}; |
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|
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&i2c1 { |
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clock-frequency = <100000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c1>; |
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status = "okay"; |
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|
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pmic: pfuze3000@08 { |
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compatible = "fsl,pfuze3000"; |
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reg = <0x08>; |
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|
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regulators { |
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sw1a_reg: sw1a { |
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regulator-min-microvolt = <700000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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regulator-ramp-delay = <6250>; |
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}; |
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|
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/* use sw1c_reg to align with pfuze100/pfuze200 */ |
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sw1c_reg: sw1b { |
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regulator-min-microvolt = <700000>; |
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regulator-max-microvolt = <1475000>; |
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regulator-boot-on; |
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regulator-always-on; |
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regulator-ramp-delay = <6250>; |
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}; |
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|
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sw2_reg: sw2 { |
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regulator-min-microvolt = <1500000>; |
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regulator-max-microvolt = <1850000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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sw3a_reg: sw3 { |
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regulator-min-microvolt = <900000>; |
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regulator-max-microvolt = <1650000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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swbst_reg: swbst { |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5150000>; |
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}; |
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|
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snvs_reg: vsnvs { |
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regulator-min-microvolt = <1000000>; |
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regulator-max-microvolt = <3000000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vref_reg: vrefddr { |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vgen1_reg: vldo1 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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vgen2_reg: vldo2 { |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <1550000>; |
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regulator-always-on; |
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}; |
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|
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vgen3_reg: vccsd { |
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regulator-min-microvolt = <2850000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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vgen4_reg: v33 { |
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regulator-min-microvolt = <2850000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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vgen5_reg: vldo3 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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vgen6_reg: vldo4 { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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}; |
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}; |
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}; |
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|
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&i2c2 { |
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clock-frequency = <100000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c2>; |
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status = "okay"; |
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}; |
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|
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&i2c3 { |
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clock-frequency = <100000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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status = "okay"; |
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}; |
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|
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&i2c4 { |
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clock-frequency = <100000>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c4>; |
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status = "okay"; |
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}; |
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|
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&usdhc1 { |
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pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; |
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
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wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
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vmmc-supply = <®_sd1_vmmc>; |
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status = "okay"; |
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}; |
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|
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&usdhc2 { |
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pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
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pinctrl-0 = <&pinctrl_usdhc2>; |
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non-removable; |
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status = "okay"; |
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}; |
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|
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&usdhc3 { |
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pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
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pinctrl-0 = <&pinctrl_usdhc3>; |
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bus-width = <8>; |
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non-removable; |
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status = "okay"; |
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}; |
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@ -0,0 +1,140 @@ |
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/* |
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* Copyright 2016 Toradex AG |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#include "imx7s.dtsi" |
||||
|
||||
/ { |
||||
cpus { |
||||
cpu0: cpu@0 { |
||||
operating-points = < |
||||
/* KHz uV */ |
||||
996000 1075000 |
||||
792000 975000 |
||||
>; |
||||
clock-frequency = <996000000>; |
||||
}; |
||||
|
||||
cpu1: cpu@1 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <1>; |
||||
clock-frequency = <996000000>; |
||||
}; |
||||
}; |
||||
|
||||
soc { |
||||
etm@3007d000 { |
||||
compatible = "arm,coresight-etm3x", "arm,primecell"; |
||||
reg = <0x3007d000 0x1000>; |
||||
|
||||
/* |
||||
* System will hang if added nosmp in kernel command line |
||||
* without arm,primecell-periphid because amba bus try to |
||||
* read id and core1 power off at this time. |
||||
*/ |
||||
arm,primecell-periphid = <0xbb956>; |
||||
cpu = <&cpu1>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
port { |
||||
etm1_out_port: endpoint { |
||||
remote-endpoint = <&ca_funnel_in_port1>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&aips3 { |
||||
usbotg2: usb@30b20000 { |
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; |
||||
reg = <0x30b20000 0x200>; |
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>; |
||||
fsl,usbphy = <&usbphynop2>; |
||||
fsl,usbmisc = <&usbmisc2 0>; |
||||
phy-clkgate-delay-us = <400>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbmisc2: usbmisc@30b20200 { |
||||
#index-cells = <1>; |
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
||||
reg = <0x30b20200 0x200>; |
||||
}; |
||||
|
||||
usbphynop2: usbphynop2 { |
||||
compatible = "usb-nop-xceiv"; |
||||
clocks = <&clks IMX7D_USB_PHY2_CLK>; |
||||
clock-names = "main_clk"; |
||||
}; |
||||
|
||||
fec2: ethernet@30bf0000 { |
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; |
||||
reg = <0x30bf0000 0x10000>; |
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, |
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>, |
||||
<&clks IMX7D_ENET2_TIME_ROOT_CLK>, |
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, |
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb", "ptp", |
||||
"enet_clk_ref", "enet_out"; |
||||
fsl,num-tx-queues=<3>; |
||||
fsl,num-rx-queues=<3>; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
&ca_funnel_ports { |
||||
port@1 { |
||||
reg = <1>; |
||||
ca_funnel_in_port1: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&etm1_out_port>; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,999 @@ |
||||
/* |
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* Copyright 2016 Toradex AG |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#include <dt-bindings/clock/imx7d-clock.h> |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/input/input.h> |
||||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
||||
#include "imx7d-pinfunc.h" |
||||
|
||||
/ { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
/* |
||||
* The decompressor and also some bootloaders rely on a |
||||
* pre-existing /chosen node to be available to insert the |
||||
* command line and merge other ATAGS info. |
||||
* Also for U-Boot there must be a pre-existing /memory node. |
||||
*/ |
||||
chosen {}; |
||||
memory { device_type = "memory"; reg = <0 0>; }; |
||||
|
||||
aliases { |
||||
gpio0 = &gpio1; |
||||
gpio1 = &gpio2; |
||||
gpio2 = &gpio3; |
||||
gpio3 = &gpio4; |
||||
gpio4 = &gpio5; |
||||
gpio5 = &gpio6; |
||||
gpio6 = &gpio7; |
||||
i2c0 = &i2c1; |
||||
i2c1 = &i2c2; |
||||
i2c2 = &i2c3; |
||||
i2c3 = &i2c4; |
||||
mmc0 = &usdhc1; |
||||
mmc1 = &usdhc2; |
||||
mmc2 = &usdhc3; |
||||
serial0 = &uart1; |
||||
serial1 = &uart2; |
||||
serial2 = &uart3; |
||||
serial3 = &uart4; |
||||
serial4 = &uart5; |
||||
serial5 = &uart6; |
||||
serial6 = &uart7; |
||||
spi0 = &ecspi1; |
||||
spi1 = &ecspi2; |
||||
spi2 = &ecspi3; |
||||
spi3 = &ecspi4; |
||||
}; |
||||
|
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
cpu0: cpu@0 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
clock-frequency = <792000000>; |
||||
clock-latency = <61036>; /* two CLK32 periods */ |
||||
clocks = <&clks IMX7D_CLK_ARM>; |
||||
}; |
||||
}; |
||||
|
||||
ckil: clock-cki { |
||||
compatible = "fixed-clock"; |
||||
#clock-cells = <0>; |
||||
clock-frequency = <32768>; |
||||
clock-output-names = "ckil"; |
||||
}; |
||||
|
||||
osc: clock-osc { |
||||
compatible = "fixed-clock"; |
||||
#clock-cells = <0>; |
||||
clock-frequency = <24000000>; |
||||
clock-output-names = "osc"; |
||||
}; |
||||
|
||||
soc { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "simple-bus"; |
||||
interrupt-parent = <&intc>; |
||||
ranges; |
||||
|
||||
funnel@30041000 { |
||||
compatible = "arm,coresight-funnel", "arm,primecell"; |
||||
reg = <0x30041000 0x1000>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
ca_funnel_ports: ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
/* funnel input ports */ |
||||
port@0 { |
||||
reg = <0>; |
||||
ca_funnel_in_port0: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&etm0_out_port>; |
||||
}; |
||||
}; |
||||
|
||||
/* funnel output port */ |
||||
port@2 { |
||||
reg = <0>; |
||||
ca_funnel_out_port0: endpoint { |
||||
remote-endpoint = <&hugo_funnel_in_port0>; |
||||
}; |
||||
}; |
||||
|
||||
/* the other input ports are not connect to anything */ |
||||
}; |
||||
}; |
||||
|
||||
etm@3007c000 { |
||||
compatible = "arm,coresight-etm3x", "arm,primecell"; |
||||
reg = <0x3007c000 0x1000>; |
||||
cpu = <&cpu0>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
port { |
||||
etm0_out_port: endpoint { |
||||
remote-endpoint = <&ca_funnel_in_port0>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
funnel@30083000 { |
||||
compatible = "arm,coresight-funnel", "arm,primecell"; |
||||
reg = <0x30083000 0x1000>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
/* funnel input ports */ |
||||
port@0 { |
||||
reg = <0>; |
||||
hugo_funnel_in_port0: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&ca_funnel_out_port0>; |
||||
}; |
||||
}; |
||||
|
||||
port@1 { |
||||
reg = <1>; |
||||
hugo_funnel_in_port1: endpoint { |
||||
slave-mode; /* M4 input */ |
||||
}; |
||||
}; |
||||
|
||||
port@2 { |
||||
reg = <0>; |
||||
hugo_funnel_out_port0: endpoint { |
||||
remote-endpoint = <&etf_in_port>; |
||||
}; |
||||
}; |
||||
|
||||
/* the other input ports are not connect to anything */ |
||||
}; |
||||
}; |
||||
|
||||
etf@30084000 { |
||||
compatible = "arm,coresight-tmc", "arm,primecell"; |
||||
reg = <0x30084000 0x1000>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
port@0 { |
||||
reg = <0>; |
||||
etf_in_port: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&hugo_funnel_out_port0>; |
||||
}; |
||||
}; |
||||
|
||||
port@1 { |
||||
reg = <0>; |
||||
etf_out_port: endpoint { |
||||
remote-endpoint = <&replicator_in_port0>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
etr@30086000 { |
||||
compatible = "arm,coresight-tmc", "arm,primecell"; |
||||
reg = <0x30086000 0x1000>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
port { |
||||
etr_in_port: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&replicator_out_port1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
tpiu@30087000 { |
||||
compatible = "arm,coresight-tpiu", "arm,primecell"; |
||||
reg = <0x30087000 0x1000>; |
||||
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
||||
clock-names = "apb_pclk"; |
||||
|
||||
port { |
||||
tpiu_in_port: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&replicator_out_port1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
replicator { |
||||
/* |
||||
* non-configurable replicators don't show up on the |
||||
* AMBA bus. As such no need to add "arm,primecell" |
||||
*/ |
||||
compatible = "arm,coresight-replicator"; |
||||
|
||||
ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
/* replicator output ports */ |
||||
port@0 { |
||||
reg = <0>; |
||||
replicator_out_port0: endpoint { |
||||
remote-endpoint = <&tpiu_in_port>; |
||||
}; |
||||
}; |
||||
|
||||
port@1 { |
||||
reg = <1>; |
||||
replicator_out_port1: endpoint { |
||||
remote-endpoint = <&etr_in_port>; |
||||
}; |
||||
}; |
||||
|
||||
/* replicator input port */ |
||||
port@2 { |
||||
reg = <0>; |
||||
replicator_in_port0: endpoint { |
||||
slave-mode; |
||||
remote-endpoint = <&etf_out_port>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
intc: interrupt-controller@31001000 { |
||||
compatible = "arm,cortex-a7-gic"; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
#interrupt-cells = <3>; |
||||
interrupt-controller; |
||||
reg = <0x31001000 0x1000>, |
||||
<0x31002000 0x2000>, |
||||
<0x31004000 0x2000>, |
||||
<0x31006000 0x2000>; |
||||
}; |
||||
|
||||
timer { |
||||
compatible = "arm,armv7-timer"; |
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
||||
}; |
||||
|
||||
aips1: aips-bus@30000000 { |
||||
compatible = "fsl,aips-bus", "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x30000000 0x400000>; |
||||
ranges; |
||||
|
||||
gpio1: gpio@30200000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30200000 0x10000>; |
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ |
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; |
||||
}; |
||||
|
||||
gpio2: gpio@30210000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30210000 0x10000>; |
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 13 32>; |
||||
}; |
||||
|
||||
gpio3: gpio@30220000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30220000 0x10000>; |
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 45 29>; |
||||
}; |
||||
|
||||
gpio4: gpio@30230000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30230000 0x10000>; |
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 74 24>; |
||||
}; |
||||
|
||||
gpio5: gpio@30240000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30240000 0x10000>; |
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 98 18>; |
||||
}; |
||||
|
||||
gpio6: gpio@30250000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30250000 0x10000>; |
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 116 23>; |
||||
}; |
||||
|
||||
gpio7: gpio@30260000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30260000 0x10000>; |
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
gpio-ranges = <&iomuxc 0 139 16>; |
||||
}; |
||||
|
||||
wdog1: wdog@30280000 { |
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; |
||||
reg = <0x30280000 0x10000>; |
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; |
||||
}; |
||||
|
||||
wdog2: wdog@30290000 { |
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; |
||||
reg = <0x30290000 0x10000>; |
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
wdog3: wdog@302a0000 { |
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; |
||||
reg = <0x302a0000 0x10000>; |
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
wdog4: wdog@302b0000 { |
||||
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; |
||||
reg = <0x302b0000 0x10000>; |
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 { |
||||
compatible = "fsl,imx7d-iomuxc-lpsr"; |
||||
reg = <0x302c0000 0x10000>; |
||||
fsl,input-sel = <&iomuxc>; |
||||
}; |
||||
|
||||
gpt1: gpt@302d0000 { |
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; |
||||
reg = <0x302d0000 0x10000>; |
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_GPT1_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
}; |
||||
|
||||
gpt2: gpt@302e0000 { |
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; |
||||
reg = <0x302e0000 0x10000>; |
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_GPT2_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
gpt3: gpt@302f0000 { |
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; |
||||
reg = <0x302f0000 0x10000>; |
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_GPT3_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
gpt4: gpt@30300000 { |
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; |
||||
reg = <0x30300000 0x10000>; |
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_GPT4_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
iomuxc: iomuxc@30330000 { |
||||
compatible = "fsl,imx7d-iomuxc"; |
||||
reg = <0x30330000 0x10000>; |
||||
}; |
||||
|
||||
gpr: iomuxc-gpr@30340000 { |
||||
compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; |
||||
reg = <0x30340000 0x10000>; |
||||
}; |
||||
|
||||
ocotp: ocotp-ctrl@30350000 { |
||||
compatible = "fsl,imx7d-ocotp", "syscon"; |
||||
reg = <0x30350000 0x10000>; |
||||
clocks = <&clks IMX7D_OCOTP_CLK>; |
||||
}; |
||||
|
||||
anatop: anatop@30360000 { |
||||
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", |
||||
"syscon", "simple-bus"; |
||||
reg = <0x30360000 0x10000>; |
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
||||
|
||||
reg_1p0d: regulator-vdd1p0d { |
||||
compatible = "fsl,anatop-regulator"; |
||||
regulator-name = "vdd1p0d"; |
||||
regulator-min-microvolt = <800000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
anatop-reg-offset = <0x210>; |
||||
anatop-vol-bit-shift = <8>; |
||||
anatop-vol-bit-width = <5>; |
||||
anatop-min-bit-val = <8>; |
||||
anatop-min-voltage = <800000>; |
||||
anatop-max-voltage = <1200000>; |
||||
}; |
||||
}; |
||||
|
||||
snvs: snvs@30370000 { |
||||
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
||||
reg = <0x30370000 0x10000>; |
||||
|
||||
snvs_rtc: snvs-rtc-lp { |
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
||||
regmap = <&snvs>; |
||||
offset = <0x34>; |
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
snvs_poweroff: snvs-poweroff { |
||||
compatible = "syscon-poweroff"; |
||||
regmap = <&snvs>; |
||||
offset = <0x38>; |
||||
mask = <0x60>; |
||||
}; |
||||
|
||||
snvs_pwrkey: snvs-powerkey { |
||||
compatible = "fsl,sec-v4.0-pwrkey"; |
||||
regmap = <&snvs>; |
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
||||
linux,keycode = <KEY_POWER>; |
||||
wakeup-source; |
||||
}; |
||||
}; |
||||
|
||||
clks: ccm@30380000 { |
||||
compatible = "fsl,imx7d-ccm"; |
||||
reg = <0x30380000 0x10000>; |
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
||||
#clock-cells = <1>; |
||||
clocks = <&ckil>, <&osc>; |
||||
clock-names = "ckil", "osc"; |
||||
}; |
||||
|
||||
src: src@30390000 { |
||||
compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; |
||||
reg = <0x30390000 0x10000>; |
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
||||
#reset-cells = <1>; |
||||
}; |
||||
}; |
||||
|
||||
aips2: aips-bus@30400000 { |
||||
compatible = "fsl,aips-bus", "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x30400000 0x400000>; |
||||
ranges; |
||||
|
||||
adc1: adc@30610000 { |
||||
compatible = "fsl,imx7d-adc"; |
||||
reg = <0x30610000 0x10000>; |
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ADC_ROOT_CLK>; |
||||
clock-names = "adc"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
adc2: adc@30620000 { |
||||
compatible = "fsl,imx7d-adc"; |
||||
reg = <0x30620000 0x10000>; |
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ADC_ROOT_CLK>; |
||||
clock-names = "adc"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ecspi4: ecspi@30630000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; |
||||
reg = <0x30630000 0x10000>; |
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, |
||||
<&clks IMX7D_ECSPI4_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pwm1: pwm@30660000 { |
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; |
||||
reg = <0x30660000 0x10000>; |
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_PWM1_ROOT_CLK>, |
||||
<&clks IMX7D_PWM1_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
#pwm-cells = <2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pwm2: pwm@30670000 { |
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; |
||||
reg = <0x30670000 0x10000>; |
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_PWM2_ROOT_CLK>, |
||||
<&clks IMX7D_PWM2_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
#pwm-cells = <2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pwm3: pwm@30680000 { |
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; |
||||
reg = <0x30680000 0x10000>; |
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_PWM3_ROOT_CLK>, |
||||
<&clks IMX7D_PWM3_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
#pwm-cells = <2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pwm4: pwm@30690000 { |
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; |
||||
reg = <0x30690000 0x10000>; |
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_PWM4_ROOT_CLK>, |
||||
<&clks IMX7D_PWM4_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
#pwm-cells = <2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
lcdif: lcdif@30730000 { |
||||
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; |
||||
reg = <0x30730000 0x10000>; |
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, |
||||
<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; |
||||
clock-names = "pix", "axi"; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
aips3: aips-bus@30800000 { |
||||
compatible = "fsl,aips-bus", "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x30800000 0x400000>; |
||||
ranges; |
||||
|
||||
ecspi1: ecspi@30820000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; |
||||
reg = <0x30820000 0x10000>; |
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, |
||||
<&clks IMX7D_ECSPI1_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ecspi2: ecspi@30830000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; |
||||
reg = <0x30830000 0x10000>; |
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, |
||||
<&clks IMX7D_ECSPI2_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ecspi3: ecspi@30840000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; |
||||
reg = <0x30840000 0x10000>; |
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, |
||||
<&clks IMX7D_ECSPI3_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@30860000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30860000 0x10000>; |
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART1_ROOT_CLK>, |
||||
<&clks IMX7D_UART1_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@30890000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30890000 0x10000>; |
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART2_ROOT_CLK>, |
||||
<&clks IMX7D_UART2_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart3: serial@30880000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30880000 0x10000>; |
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART3_ROOT_CLK>, |
||||
<&clks IMX7D_UART3_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sai1: sai@308a0000 { |
||||
#sound-dai-cells = <0>; |
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; |
||||
reg = <0x308a0000 0x10000>; |
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_SAI1_IPG_CLK>, |
||||
<&clks IMX7D_SAI1_ROOT_CLK>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>; |
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
||||
dma-names = "rx", "tx"; |
||||
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sai2: sai@308b0000 { |
||||
#sound-dai-cells = <0>; |
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; |
||||
reg = <0x308b0000 0x10000>; |
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_SAI2_IPG_CLK>, |
||||
<&clks IMX7D_SAI2_ROOT_CLK>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>; |
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
||||
dma-names = "rx", "tx"; |
||||
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sai3: sai@308c0000 { |
||||
#sound-dai-cells = <0>; |
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; |
||||
reg = <0x308c0000 0x10000>; |
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_SAI3_IPG_CLK>, |
||||
<&clks IMX7D_SAI3_ROOT_CLK>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>; |
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
||||
dma-names = "rx", "tx"; |
||||
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
flexcan1: can@30a00000 { |
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; |
||||
reg = <0x30a00000 0x10000>; |
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CAN1_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
flexcan2: can@30a10000 { |
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; |
||||
reg = <0x30a10000 0x10000>; |
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CAN2_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c1: i2c@30a20000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a20000 0x10000>; |
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_I2C1_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c2: i2c@30a30000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a30000 0x10000>; |
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_I2C2_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c3: i2c@30a40000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a40000 0x10000>; |
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_I2C3_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c4: i2c@30a50000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a50000 0x10000>; |
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_I2C4_ROOT_CLK>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart4: serial@30a60000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a60000 0x10000>; |
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART4_ROOT_CLK>, |
||||
<&clks IMX7D_UART4_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart5: serial@30a70000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a70000 0x10000>; |
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART5_ROOT_CLK>, |
||||
<&clks IMX7D_UART5_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart6: serial@30a80000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a80000 0x10000>; |
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART6_ROOT_CLK>, |
||||
<&clks IMX7D_UART6_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart7: serial@30a90000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a90000 0x10000>; |
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_UART7_ROOT_CLK>, |
||||
<&clks IMX7D_UART7_ROOT_CLK>; |
||||
clock-names = "ipg", "per"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbotg1: usb@30b10000 { |
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; |
||||
reg = <0x30b10000 0x200>; |
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>; |
||||
fsl,usbphy = <&usbphynop1>; |
||||
fsl,usbmisc = <&usbmisc1 0>; |
||||
phy-clkgate-delay-us = <400>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbh: usb@30b30000 { |
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; |
||||
reg = <0x30b30000 0x200>; |
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>; |
||||
fsl,usbphy = <&usbphynop3>; |
||||
fsl,usbmisc = <&usbmisc3 0>; |
||||
phy_type = "hsic"; |
||||
dr_mode = "host"; |
||||
phy-clkgate-delay-us = <400>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbmisc1: usbmisc@30b10200 { |
||||
#index-cells = <1>; |
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
||||
reg = <0x30b10200 0x200>; |
||||
}; |
||||
|
||||
usbmisc3: usbmisc@30b30200 { |
||||
#index-cells = <1>; |
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
||||
reg = <0x30b30200 0x200>; |
||||
}; |
||||
|
||||
usbphynop1: usbphynop1 { |
||||
compatible = "usb-nop-xceiv"; |
||||
clocks = <&clks IMX7D_USB_PHY1_CLK>; |
||||
clock-names = "main_clk"; |
||||
}; |
||||
|
||||
usbphynop3: usbphynop3 { |
||||
compatible = "usb-nop-xceiv"; |
||||
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; |
||||
clock-names = "main_clk"; |
||||
}; |
||||
|
||||
usdhc1: usdhc@30b40000 { |
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
||||
reg = <0x30b40000 0x10000>; |
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_USDHC1_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb", "per"; |
||||
bus-width = <4>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usdhc2: usdhc@30b50000 { |
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
||||
reg = <0x30b50000 0x10000>; |
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_USDHC2_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb", "per"; |
||||
bus-width = <4>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usdhc3: usdhc@30b60000 { |
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
||||
reg = <0x30b60000 0x10000>; |
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_CLK_DUMMY>, |
||||
<&clks IMX7D_USDHC3_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb", "per"; |
||||
bus-width = <4>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sdma: sdma@30bd0000 { |
||||
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; |
||||
reg = <0x30bd0000 0x10000>; |
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_SDMA_CORE_CLK>, |
||||
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb"; |
||||
#dma-cells = <3>; |
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; |
||||
}; |
||||
|
||||
fec1: ethernet@30be0000 { |
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; |
||||
reg = <0x30be0000 0x10000>; |
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, |
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>, |
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>, |
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, |
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; |
||||
clock-names = "ipg", "ahb", "ptp", |
||||
"enet_clk_ref", "enet_out"; |
||||
fsl,num-tx-queues=<3>; |
||||
fsl,num-rx-queues=<3>; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,7 @@ |
||||
# Copyright (C) 2016 Amarula Solutions B.V.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := board.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
@ -0,0 +1,82 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V. |
||||
* Copyright (C) 2016 Engicam S.r.l. |
||||
* Author: Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mmc.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
#include "board.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC |
||||
static void mmc_late_init(void) |
||||
{ |
||||
char cmd[32]; |
||||
char mmcblk[32]; |
||||
u32 dev_no = mmc_get_env_dev(); |
||||
|
||||
setenv_ulong("mmcdev", dev_no); |
||||
|
||||
/* Set mmcblk env */ |
||||
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); |
||||
setenv("mmcroot", mmcblk); |
||||
|
||||
sprintf(cmd, "mmc dev %d", dev_no); |
||||
run_command(cmd, 0); |
||||
} |
||||
#endif |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> |
||||
IMX6_BMODE_SHIFT) { |
||||
case IMX6_BMODE_SD: |
||||
case IMX6_BMODE_ESD: |
||||
case IMX6_BMODE_MMC: |
||||
case IMX6_BMODE_EMMC: |
||||
#ifdef CONFIG_ENV_IS_IN_MMC |
||||
mmc_late_init(); |
||||
#endif |
||||
setenv("modeboot", "mmcboot"); |
||||
break; |
||||
case IMX6_BMODE_NAND: |
||||
setenv("modeboot", "nandboot"); |
||||
break; |
||||
default: |
||||
setenv("modeboot", ""); |
||||
break; |
||||
} |
||||
|
||||
setenv_fdt_file(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
#ifdef CONFIG_NAND_MXS |
||||
setup_gpmi_nand(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_VIDEO_IPUV3 |
||||
setup_display(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = imx_ddr_size(); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,12 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
void setenv_fdt_file(void); |
||||
void setup_gpmi_nand(void); |
||||
void setup_display(void); |
||||
#endif /* _BOARD_H_ */ |
||||
@ -0,0 +1,393 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V. |
||||
* Copyright (C) 2016 Engicam S.r.l. |
||||
* Author: Jagan Teki <jagan@amarulasolutions.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
#include <linux/sizes.h> |
||||
|
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/video.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = { |
||||
#ifdef CONFIG_MX6QDL |
||||
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
#elif CONFIG_MX6UL |
||||
IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
#endif |
||||
}; |
||||
|
||||
#ifdef CONFIG_MX6QDL |
||||
/*
|
||||
* Driving strength: |
||||
* 0x30 == 40 Ohm |
||||
* 0x28 == 48 Ohm |
||||
*/ |
||||
#define IMX6DQ_DRIVE_STRENGTH 0x30 |
||||
#define IMX6SDL_DRIVE_STRENGTH 0x28 |
||||
|
||||
/* configure MX6Q/DUAL mmdc DDR io registers */ |
||||
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
||||
.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_cas = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_ras = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_reset = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, |
||||
.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* configure MX6Q/DUAL mmdc GRP io registers */ |
||||
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
||||
.grp_b0ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b1ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b2ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b3ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b4ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b5ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b6ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_b7ds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_addds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_ctlds = IMX6DQ_DRIVE_STRENGTH, |
||||
.grp_ddr_type = 0x000c0000, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
||||
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_cas = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_ras = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_reset = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_addds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* mt41j256 */ |
||||
static struct mx6_ddr3_cfg mt41j256 = { |
||||
.mem_speed = 1066, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 13, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
.SRT = 0, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { |
||||
.p0_mpwldectrl0 = 0x000E0009, |
||||
.p0_mpwldectrl1 = 0x0018000E, |
||||
.p1_mpwldectrl0 = 0x00000007, |
||||
.p1_mpwldectrl1 = 0x00000000, |
||||
.p0_mpdgctrl0 = 0x43280334, |
||||
.p0_mpdgctrl1 = 0x031C0314, |
||||
.p1_mpdgctrl0 = 0x4318031C, |
||||
.p1_mpdgctrl1 = 0x030C0258, |
||||
.p0_mprddlctl = 0x3E343A40, |
||||
.p1_mprddlctl = 0x383C3844, |
||||
.p0_mpwrdlctl = 0x40404440, |
||||
.p1_mpwrdlctl = 0x4C3E4446, |
||||
}; |
||||
|
||||
/* DDR 64bit */ |
||||
static struct mx6_ddr_sysinfo mem_q = { |
||||
.ddr_type = DDR_TYPE_DDR3, |
||||
.dsize = 2, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 2, |
||||
.rtt_wr = 2, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { |
||||
.p0_mpwldectrl0 = 0x001F0024, |
||||
.p0_mpwldectrl1 = 0x00110018, |
||||
.p1_mpwldectrl0 = 0x001F0024, |
||||
.p1_mpwldectrl1 = 0x00110018, |
||||
.p0_mpdgctrl0 = 0x4230022C, |
||||
.p0_mpdgctrl1 = 0x02180220, |
||||
.p1_mpdgctrl0 = 0x42440248, |
||||
.p1_mpdgctrl1 = 0x02300238, |
||||
.p0_mprddlctl = 0x44444A48, |
||||
.p1_mprddlctl = 0x46484A42, |
||||
.p0_mpwrdlctl = 0x38383234, |
||||
.p1_mpwrdlctl = 0x3C34362E, |
||||
}; |
||||
|
||||
/* DDR 64bit 1GB */ |
||||
static struct mx6_ddr_sysinfo mem_dl = { |
||||
.dsize = 2, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
/* DDR 32bit 512MB */ |
||||
static struct mx6_ddr_sysinfo mem_s = { |
||||
.dsize = 1, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
#endif /* CONFIG_MX6QDL */ |
||||
|
||||
#ifdef CONFIG_MX6UL |
||||
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
||||
.grp_addds = 0x00000030, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_ctlds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_ddr_type = 0x000c0000, |
||||
}; |
||||
|
||||
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
||||
.dram_dqm0 = 0x00000030, |
||||
.dram_dqm1 = 0x00000030, |
||||
.dram_ras = 0x00000030, |
||||
.dram_cas = 0x00000030, |
||||
.dram_odt0 = 0x00000030, |
||||
.dram_odt1 = 0x00000030, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdclk_0 = 0x00000008, |
||||
.dram_sdqs0 = 0x00000038, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_reset = 0x00000030, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6_mmcd_calib = { |
||||
.p0_mpwldectrl0 = 0x00070007, |
||||
.p0_mpdgctrl0 = 0x41490145, |
||||
.p0_mprddlctl = 0x40404546, |
||||
.p0_mpwrdlctl = 0x4040524D, |
||||
}; |
||||
|
||||
struct mx6_ddr_sysinfo ddr_sysinfo = { |
||||
.dsize = 0, |
||||
.cs_density = 20, |
||||
.ncs = 1, |
||||
.cs1_mirror = 0, |
||||
.rtt_wr = 2, |
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */ |
||||
.walat = 1, /* Write additional latency */ |
||||
.ralat = 5, /* Read additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
.ddr_type = DDR_TYPE_DDR3, |
||||
}; |
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = { |
||||
.mem_speed = 800, |
||||
.density = 4, |
||||
.width = 16, |
||||
.banks = 8, |
||||
#ifdef TARGET_MX6UL_ISIOT |
||||
.rowaddr = 15, |
||||
#else |
||||
.rowaddr = 13, |
||||
#endif |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
#endif /* CONFIG_MX6UL */ |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
#ifdef CONFIG_MX6QDL |
||||
writel(0x00003F3F, &ccm->CCGR0); |
||||
writel(0x0030FC00, &ccm->CCGR1); |
||||
writel(0x000FC000, &ccm->CCGR2); |
||||
writel(0x3F300000, &ccm->CCGR3); |
||||
writel(0xFF00F300, &ccm->CCGR4); |
||||
writel(0x0F0000C3, &ccm->CCGR5); |
||||
writel(0x000003CC, &ccm->CCGR6); |
||||
#elif CONFIG_MX6UL |
||||
writel(0x00c03f3f, &ccm->CCGR0); |
||||
writel(0xfcffff00, &ccm->CCGR1); |
||||
writel(0x0cffffcc, &ccm->CCGR2); |
||||
writel(0x3f3c3030, &ccm->CCGR3); |
||||
writel(0xff00fffc, &ccm->CCGR4); |
||||
writel(0x033f30ff, &ccm->CCGR5); |
||||
writel(0x00c00fff, &ccm->CCGR6); |
||||
#endif |
||||
} |
||||
|
||||
static void gpr_init(void) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
writel(0xF00000CF, &iomux->gpr[4]); |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
writel(0x007F007F, &iomux->gpr[6]); |
||||
writel(0x007F007F, &iomux->gpr[7]); |
||||
} |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
#ifdef CONFIG_MX6QDL |
||||
if (is_mx6solo()) { |
||||
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); |
||||
} else if (is_mx6dl()) { |
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); |
||||
} else if (is_mx6dq()) { |
||||
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); |
||||
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); |
||||
} |
||||
#elif CONFIG_MX6UL |
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
||||
#endif |
||||
|
||||
udelay(100); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
ccgr_init(); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
gpr_init(); |
||||
|
||||
/* iomux */ |
||||
SETUP_IOMUX_PADS(uart_pads); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
@ -1,131 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Refer doc/README.imximage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : one of |
||||
* spi, sd (the board has no nand neither onenand) |
||||
*/ |
||||
|
||||
BOOT_FROM sd |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
DATA 4 0x020e0774 0x000C0000 |
||||
DATA 4 0x020e0754 0x00000000 |
||||
DATA 4 0x020e04ac 0x00000030 |
||||
DATA 4 0x020e04b0 0x00000030 |
||||
DATA 4 0x020e0464 0x00000030 |
||||
DATA 4 0x020e0490 0x00000030 |
||||
DATA 4 0x020e074c 0x00000030 |
||||
DATA 4 0x020e0494 0x00000030 |
||||
DATA 4 0x020e04a0 0x00000000 |
||||
DATA 4 0x020e04b4 0x00000030 |
||||
DATA 4 0x020e04b8 0x00000030 |
||||
DATA 4 0x020e076c 0x00000030 |
||||
DATA 4 0x020e0750 0x00020000 |
||||
DATA 4 0x020e04bc 0x00000030 |
||||
DATA 4 0x020e04c0 0x00000030 |
||||
DATA 4 0x020e04c4 0x00000030 |
||||
DATA 4 0x020e04c8 0x00000030 |
||||
DATA 4 0x020e04cc 0x00000030 |
||||
DATA 4 0x020e04d0 0x00000030 |
||||
DATA 4 0x020e04d4 0x00000030 |
||||
DATA 4 0x020e04d8 0x00000030 |
||||
DATA 4 0x020e0760 0x00020000 |
||||
DATA 4 0x020e0764 0x00000030 |
||||
DATA 4 0x020e0770 0x00000030 |
||||
DATA 4 0x020e0778 0x00000030 |
||||
DATA 4 0x020e077c 0x00000030 |
||||
DATA 4 0x020e0780 0x00000030 |
||||
DATA 4 0x020e0784 0x00000030 |
||||
DATA 4 0x020e078c 0x00000030 |
||||
DATA 4 0x020e0748 0x00000030 |
||||
DATA 4 0x020e0470 0x00000030 |
||||
DATA 4 0x020e0474 0x00000030 |
||||
DATA 4 0x020e0478 0x00000030 |
||||
DATA 4 0x020e047c 0x00000030 |
||||
DATA 4 0x020e0480 0x00000030 |
||||
DATA 4 0x020e0484 0x00000030 |
||||
DATA 4 0x020e0488 0x00000030 |
||||
DATA 4 0x020e048c 0x00000030 |
||||
DATA 4 0x021b0800 0xa1390003 |
||||
DATA 4 0x021b080c 0x001F001F |
||||
DATA 4 0x021b0810 0x001F001F |
||||
DATA 4 0x021b480c 0x001F001F |
||||
DATA 4 0x021b4810 0x001F001F |
||||
DATA 4 0x021b083c 0x4220021F |
||||
DATA 4 0x021b0840 0x0207017E |
||||
DATA 4 0x021b483c 0x4201020C |
||||
DATA 4 0x021b4840 0x01660172 |
||||
DATA 4 0x021b0848 0x4A4D4E4D |
||||
DATA 4 0x021b4848 0x4A4F5049 |
||||
DATA 4 0x021b0850 0x3F3C3D31 |
||||
DATA 4 0x021b4850 0x3238372B |
||||
DATA 4 0x021b081c 0x33333333 |
||||
DATA 4 0x021b0820 0x33333333 |
||||
DATA 4 0x021b0824 0x33333333 |
||||
DATA 4 0x021b0828 0x33333333 |
||||
DATA 4 0x021b481c 0x33333333 |
||||
DATA 4 0x021b4820 0x33333333 |
||||
DATA 4 0x021b4824 0x33333333 |
||||
DATA 4 0x021b4828 0x33333333 |
||||
DATA 4 0x021b08b8 0x00000800 |
||||
DATA 4 0x021b48b8 0x00000800 |
||||
DATA 4 0x021b0004 0x0002002D |
||||
DATA 4 0x021b0008 0x00333030 |
||||
DATA 4 0x021b000c 0x3F435313 |
||||
DATA 4 0x021b0010 0xB66E8B63 |
||||
DATA 4 0x021b0014 0x01FF00DB |
||||
DATA 4 0x021b0018 0x00001740 |
||||
DATA 4 0x021b001c 0x00008000 |
||||
DATA 4 0x021b002c 0x000026d2 |
||||
DATA 4 0x021b0030 0x00431023 |
||||
DATA 4 0x021b0040 0x00000027 |
||||
DATA 4 0x021b0000 0x831A0000 |
||||
DATA 4 0x021b001c 0x04008032 |
||||
DATA 4 0x021b001c 0x00008033 |
||||
DATA 4 0x021b001c 0x00048031 |
||||
DATA 4 0x021b001c 0x05208030 |
||||
DATA 4 0x021b001c 0x04008040 |
||||
DATA 4 0x021b0020 0x00005800 |
||||
DATA 4 0x021b0818 0x00011117 |
||||
DATA 4 0x021b4818 0x00011117 |
||||
DATA 4 0x021b0004 0x0002556D |
||||
DATA 4 0x021b0404 0x00011006 |
||||
DATA 4 0x021b001c 0x00000000 |
||||
|
||||
/* set the default clock gate to save power */ |
||||
DATA 4 0x020c4068 0x00C03F3F |
||||
DATA 4 0x020c406c 0x0030FC03 |
||||
DATA 4 0x020c4070 0x0FFFC000 |
||||
DATA 4 0x020c4074 0x3FF00000 |
||||
DATA 4 0x020c4078 0x00FFF300 |
||||
DATA 4 0x020c407c 0x0F0000C3 |
||||
DATA 4 0x020c4080 0x000003FF |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
DATA 4 0x020e0010 0xF00000CF |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
DATA 4 0x020e0018 0x007F007F |
||||
DATA 4 0x020e001c 0x007F007F |
||||
@ -1,169 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. |
||||
* Jason Liu <r64343@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Refer doc/README.imximage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
/* image version */ |
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : one of |
||||
* spi, sd (the board has no nand neither onenand) |
||||
*/ |
||||
BOOT_FROM sd |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
DATA 4 0x020e05a8 0x00000030 |
||||
DATA 4 0x020e05b0 0x00000030 |
||||
DATA 4 0x020e0524 0x00000030 |
||||
DATA 4 0x020e051c 0x00000030 |
||||
|
||||
DATA 4 0x020e0518 0x00000030 |
||||
DATA 4 0x020e050c 0x00000030 |
||||
DATA 4 0x020e05b8 0x00000030 |
||||
DATA 4 0x020e05c0 0x00000030 |
||||
|
||||
DATA 4 0x020e05ac 0x00020030 |
||||
DATA 4 0x020e05b4 0x00020030 |
||||
DATA 4 0x020e0528 0x00020030 |
||||
DATA 4 0x020e0520 0x00020030 |
||||
|
||||
DATA 4 0x020e0514 0x00020030 |
||||
DATA 4 0x020e0510 0x00020030 |
||||
DATA 4 0x020e05bc 0x00020030 |
||||
DATA 4 0x020e05c4 0x00020030 |
||||
|
||||
DATA 4 0x020e056c 0x00020030 |
||||
DATA 4 0x020e0578 0x00020030 |
||||
DATA 4 0x020e0588 0x00020030 |
||||
DATA 4 0x020e0594 0x00020030 |
||||
|
||||
DATA 4 0x020e057c 0x00020030 |
||||
DATA 4 0x020e0590 0x00003000 |
||||
DATA 4 0x020e0598 0x00003000 |
||||
DATA 4 0x020e058c 0x00000000 |
||||
|
||||
DATA 4 0x020e059c 0x00003030 |
||||
DATA 4 0x020e05a0 0x00003030 |
||||
DATA 4 0x020e0784 0x00000030 |
||||
DATA 4 0x020e0788 0x00000030 |
||||
|
||||
DATA 4 0x020e0794 0x00000030 |
||||
DATA 4 0x020e079c 0x00000030 |
||||
DATA 4 0x020e07a0 0x00000030 |
||||
DATA 4 0x020e07a4 0x00000030 |
||||
|
||||
DATA 4 0x020e07a8 0x00000030 |
||||
DATA 4 0x020e0748 0x00000030 |
||||
DATA 4 0x020e074c 0x00000030 |
||||
DATA 4 0x020e0750 0x00020000 |
||||
|
||||
DATA 4 0x020e0758 0x00000000 |
||||
DATA 4 0x020e0774 0x00020000 |
||||
DATA 4 0x020e078c 0x00000030 |
||||
DATA 4 0x020e0798 0x000C0000 |
||||
|
||||
DATA 4 0x021b081c 0x33333333 |
||||
DATA 4 0x021b0820 0x33333333 |
||||
DATA 4 0x021b0824 0x33333333 |
||||
DATA 4 0x021b0828 0x33333333 |
||||
|
||||
DATA 4 0x021b481c 0x33333333 |
||||
DATA 4 0x021b4820 0x33333333 |
||||
DATA 4 0x021b4824 0x33333333 |
||||
DATA 4 0x021b4828 0x33333333 |
||||
|
||||
DATA 4 0x021b0018 0x00081740 |
||||
|
||||
DATA 4 0x021b001c 0x00008000 |
||||
DATA 4 0x021b000c 0x555A7974 |
||||
DATA 4 0x021b0010 0xDB538F64 |
||||
DATA 4 0x021b0014 0x01FF00DB |
||||
DATA 4 0x021b002c 0x000026D2 |
||||
|
||||
DATA 4 0x021b0030 0x005A1023 |
||||
DATA 4 0x021b0008 0x09444040 |
||||
DATA 4 0x021b0004 0x00025576 |
||||
DATA 4 0x021b0040 0x00000027 |
||||
DATA 4 0x021b0000 0x831A0000 |
||||
|
||||
DATA 4 0x021b001c 0x04088032 |
||||
DATA 4 0x021b001c 0x0408803A |
||||
DATA 4 0x021b001c 0x00008033 |
||||
DATA 4 0x021b001c 0x0000803B |
||||
DATA 4 0x021b001c 0x00428031 |
||||
DATA 4 0x021b001c 0x00428039 |
||||
DATA 4 0x021b001c 0x19308030 |
||||
DATA 4 0x021b001c 0x19308038 |
||||
|
||||
DATA 4 0x021b001c 0x04008040 |
||||
DATA 4 0x021b001c 0x04008048 |
||||
DATA 4 0x021b0800 0xA1380003 |
||||
DATA 4 0x021b4800 0xA1380003 |
||||
DATA 4 0x021b0020 0x00005800 |
||||
DATA 4 0x021b0818 0x00022227 |
||||
DATA 4 0x021b4818 0x00022227 |
||||
|
||||
DATA 4 0x021b083c 0x434B0350 |
||||
DATA 4 0x021b0840 0x034C0359 |
||||
DATA 4 0x021b483c 0x434B0350 |
||||
DATA 4 0x021b4840 0x03650348 |
||||
DATA 4 0x021b0848 0x4436383B |
||||
DATA 4 0x021b4848 0x39393341 |
||||
DATA 4 0x021b0850 0x35373933 |
||||
DATA 4 0x021b4850 0x48254A36 |
||||
|
||||
DATA 4 0x021b080c 0x001F001F |
||||
DATA 4 0x021b0810 0x001F001F |
||||
|
||||
DATA 4 0x021b480c 0x00440044 |
||||
DATA 4 0x021b4810 0x00440044 |
||||
|
||||
DATA 4 0x021b08b8 0x00000800 |
||||
DATA 4 0x021b48b8 0x00000800 |
||||
|
||||
DATA 4 0x021b001c 0x00000000 |
||||
DATA 4 0x021b0404 0x00011006 |
||||
|
||||
/* set the default clock gate to save power */ |
||||
DATA 4 0x020c4068 0x00C03F3F |
||||
DATA 4 0x020c406c 0x0030FC03 |
||||
DATA 4 0x020c4070 0x0FFFC000 |
||||
DATA 4 0x020c4074 0x3FF00000 |
||||
DATA 4 0x020c4078 0x00FFF300 |
||||
DATA 4 0x020c407c 0x0F0000C3 |
||||
DATA 4 0x020c4080 0x000003FF |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
DATA 4 0x020e0010 0xF00000CF |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
DATA 4 0x020e0018 0x007F007F |
||||
DATA 4 0x020e001c 0x007F007F |
||||
|
||||
/* |
||||
* Setup CCM_CCOSR register as follows: |
||||
* |
||||
* cko1_en = 1 --> CKO1 enabled |
||||
* cko1_div = 111 --> divide by 8 |
||||
* cko1_sel = 1011 --> ahb_clk_root |
||||
* |
||||
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz |
||||
*/ |
||||
DATA 4 0x020c4060 0x000000fb |
||||
@ -1,44 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_MX6Q_ICORE=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_VIDEO=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_SIGNATURE=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_EXT_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="icorem6qdl> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
# CONFIG_BLK is not set |
||||
CONFIG_SYS_I2C_MXC=y |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_IMX_THERMAL=y |
||||
CONFIG_VIDEO_IPUV3=y |
||||
@ -1,45 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_MX6Q_ICORE=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_VIDEO=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_SIGNATURE=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_DMA_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="icorem6qdl> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_NAND=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_CMD_UBI=y |
||||
# CONFIG_BLK is not set |
||||
CONFIG_SYS_I2C_MXC=y |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_NAND_MXS=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_IMX_THERMAL=y |
||||
CONFIG_VIDEO_IPUV3=y |
||||
@ -1,41 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_MX6Q_ICORE_RQS=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_SIGNATURE=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_EXT_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="icorem6qdl-rqs> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
# CONFIG_BLK is not set |
||||
CONFIG_SYS_I2C_MXC=y |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_MXC_UART=y |
||||
@ -1,45 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_TARGET_MX6Q_ICORE=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
# CONFIG_CMD_BMODE is not set |
||||
CONFIG_VIDEO=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_SIGNATURE=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_DMA_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="icorem6qdl> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_NAND=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_CMD_UBI=y |
||||
# CONFIG_BLK is not set |
||||
CONFIG_SYS_I2C_MXC=y |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_NAND_MXS=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_IMX_THERMAL=y |
||||
CONFIG_VIDEO_IPUV3=y |
||||
@ -1,44 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_MX6SABRESD=y |
||||
CONFIG_VIDEO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" |
||||
CONFIG_BOOTDELAY=3 |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_DFU_MMC=y |
||||
CONFIG_DFU_SF=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_PCI=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="FSL" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x0525 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 |
||||
# CONFIG_VIDEO_SW_CURSOR is not set |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -1,44 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_MX6SABRESD=y |
||||
CONFIG_VIDEO=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" |
||||
CONFIG_BOOTDELAY=3 |
||||
# CONFIG_CONSOLE_MUX is not set |
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_DFU_MMC=y |
||||
CONFIG_DFU_SF=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_PCI=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="FSL" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x0525 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 |
||||
# CONFIG_VIDEO_SW_CURSOR is not set |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -0,0 +1,454 @@ |
||||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX7D_H |
||||
#define __DT_BINDINGS_CLOCK_IMX7D_H |
||||
|
||||
#define IMX7D_OSC_24M_CLK 0 |
||||
#define IMX7D_PLL_ARM_MAIN 1 |
||||
#define IMX7D_PLL_ARM_MAIN_CLK 2 |
||||
#define IMX7D_PLL_ARM_MAIN_SRC 3 |
||||
#define IMX7D_PLL_ARM_MAIN_BYPASS 4 |
||||
#define IMX7D_PLL_SYS_MAIN 5 |
||||
#define IMX7D_PLL_SYS_MAIN_CLK 6 |
||||
#define IMX7D_PLL_SYS_MAIN_SRC 7 |
||||
#define IMX7D_PLL_SYS_MAIN_BYPASS 8 |
||||
#define IMX7D_PLL_SYS_MAIN_480M 9 |
||||
#define IMX7D_PLL_SYS_MAIN_240M 10 |
||||
#define IMX7D_PLL_SYS_MAIN_120M 11 |
||||
#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 |
||||
#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 |
||||
#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 |
||||
#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 |
||||
#define IMX7D_PLL_SYS_PFD0_196M 16 |
||||
#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 |
||||
#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 |
||||
#define IMX7D_PLL_SYS_PFD1_166M 19 |
||||
#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 |
||||
#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 |
||||
#define IMX7D_PLL_SYS_PFD2_135M 22 |
||||
#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 |
||||
#define IMX7D_PLL_SYS_PFD3_CLK 24 |
||||
#define IMX7D_PLL_SYS_PFD4_CLK 25 |
||||
#define IMX7D_PLL_SYS_PFD5_CLK 26 |
||||
#define IMX7D_PLL_SYS_PFD6_CLK 27 |
||||
#define IMX7D_PLL_SYS_PFD7_CLK 28 |
||||
#define IMX7D_PLL_ENET_MAIN 29 |
||||
#define IMX7D_PLL_ENET_MAIN_CLK 30 |
||||
#define IMX7D_PLL_ENET_MAIN_SRC 31 |
||||
#define IMX7D_PLL_ENET_MAIN_BYPASS 32 |
||||
#define IMX7D_PLL_ENET_MAIN_500M 33 |
||||
#define IMX7D_PLL_ENET_MAIN_250M 34 |
||||
#define IMX7D_PLL_ENET_MAIN_125M 35 |
||||
#define IMX7D_PLL_ENET_MAIN_100M 36 |
||||
#define IMX7D_PLL_ENET_MAIN_50M 37 |
||||
#define IMX7D_PLL_ENET_MAIN_40M 38 |
||||
#define IMX7D_PLL_ENET_MAIN_25M 39 |
||||
#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 |
||||
#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 |
||||
#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 |
||||
#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 |
||||
#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 |
||||
#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 |
||||
#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 |
||||
#define IMX7D_PLL_DRAM_MAIN 47 |
||||
#define IMX7D_PLL_DRAM_MAIN_CLK 48 |
||||
#define IMX7D_PLL_DRAM_MAIN_SRC 49 |
||||
#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 |
||||
#define IMX7D_PLL_DRAM_MAIN_533M 51 |
||||
#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 |
||||
#define IMX7D_PLL_AUDIO_MAIN 53 |
||||
#define IMX7D_PLL_AUDIO_MAIN_CLK 54 |
||||
#define IMX7D_PLL_AUDIO_MAIN_SRC 55 |
||||
#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 |
||||
#define IMX7D_PLL_VIDEO_MAIN_CLK 57 |
||||
#define IMX7D_PLL_VIDEO_MAIN 58 |
||||
#define IMX7D_PLL_VIDEO_MAIN_SRC 59 |
||||
#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 |
||||
#define IMX7D_USB_MAIN_480M_CLK 61 |
||||
#define IMX7D_ARM_A7_ROOT_CLK 62 |
||||
#define IMX7D_ARM_A7_ROOT_SRC 63 |
||||
#define IMX7D_ARM_A7_ROOT_CG 64 |
||||
#define IMX7D_ARM_A7_ROOT_DIV 65 |
||||
#define IMX7D_ARM_M4_ROOT_CLK 66 |
||||
#define IMX7D_ARM_M4_ROOT_SRC 67 |
||||
#define IMX7D_ARM_M4_ROOT_CG 68 |
||||
#define IMX7D_ARM_M4_ROOT_DIV 69 |
||||
#define IMX7D_ARM_M0_ROOT_CLK 70 |
||||
#define IMX7D_ARM_M0_ROOT_SRC 71 |
||||
#define IMX7D_ARM_M0_ROOT_CG 72 |
||||
#define IMX7D_ARM_M0_ROOT_DIV 73 |
||||
#define IMX7D_MAIN_AXI_ROOT_CLK 74 |
||||
#define IMX7D_MAIN_AXI_ROOT_SRC 75 |
||||
#define IMX7D_MAIN_AXI_ROOT_CG 76 |
||||
#define IMX7D_MAIN_AXI_ROOT_DIV 77 |
||||
#define IMX7D_DISP_AXI_ROOT_CLK 78 |
||||
#define IMX7D_DISP_AXI_ROOT_SRC 79 |
||||
#define IMX7D_DISP_AXI_ROOT_CG 80 |
||||
#define IMX7D_DISP_AXI_ROOT_DIV 81 |
||||
#define IMX7D_ENET_AXI_ROOT_CLK 82 |
||||
#define IMX7D_ENET_AXI_ROOT_SRC 83 |
||||
#define IMX7D_ENET_AXI_ROOT_CG 84 |
||||
#define IMX7D_ENET_AXI_ROOT_DIV 85 |
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 |
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 |
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 |
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 |
||||
#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 |
||||
#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 |
||||
#define IMX7D_AHB_CHANNEL_ROOT_CG 92 |
||||
#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 |
||||
#define IMX7D_DRAM_PHYM_ROOT_CLK 94 |
||||
#define IMX7D_DRAM_PHYM_ROOT_SRC 95 |
||||
#define IMX7D_DRAM_PHYM_ROOT_CG 96 |
||||
#define IMX7D_DRAM_PHYM_ROOT_DIV 97 |
||||
#define IMX7D_DRAM_ROOT_CLK 98 |
||||
#define IMX7D_DRAM_ROOT_SRC 99 |
||||
#define IMX7D_DRAM_ROOT_CG 100 |
||||
#define IMX7D_DRAM_ROOT_DIV 101 |
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 |
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 |
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 |
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 |
||||
#define IMX7D_DRAM_ALT_ROOT_CLK 106 |
||||
#define IMX7D_DRAM_ALT_ROOT_SRC 107 |
||||
#define IMX7D_DRAM_ALT_ROOT_CG 108 |
||||
#define IMX7D_DRAM_ALT_ROOT_DIV 109 |
||||
#define IMX7D_USB_HSIC_ROOT_CLK 110 |
||||
#define IMX7D_USB_HSIC_ROOT_SRC 111 |
||||
#define IMX7D_USB_HSIC_ROOT_CG 112 |
||||
#define IMX7D_USB_HSIC_ROOT_DIV 113 |
||||
#define IMX7D_PCIE_CTRL_ROOT_CLK 114 |
||||
#define IMX7D_PCIE_CTRL_ROOT_SRC 115 |
||||
#define IMX7D_PCIE_CTRL_ROOT_CG 116 |
||||
#define IMX7D_PCIE_CTRL_ROOT_DIV 117 |
||||
#define IMX7D_PCIE_PHY_ROOT_CLK 118 |
||||
#define IMX7D_PCIE_PHY_ROOT_SRC 119 |
||||
#define IMX7D_PCIE_PHY_ROOT_CG 120 |
||||
#define IMX7D_PCIE_PHY_ROOT_DIV 121 |
||||
#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 |
||||
#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 |
||||
#define IMX7D_EPDC_PIXEL_ROOT_CG 124 |
||||
#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 |
||||
#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 |
||||
#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 |
||||
#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 |
||||
#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 |
||||
#define IMX7D_MIPI_DSI_ROOT_CLK 130 |
||||
#define IMX7D_MIPI_DSI_ROOT_SRC 131 |
||||
#define IMX7D_MIPI_DSI_ROOT_CG 132 |
||||
#define IMX7D_MIPI_DSI_ROOT_DIV 133 |
||||
#define IMX7D_MIPI_CSI_ROOT_CLK 134 |
||||
#define IMX7D_MIPI_CSI_ROOT_SRC 135 |
||||
#define IMX7D_MIPI_CSI_ROOT_CG 136 |
||||
#define IMX7D_MIPI_CSI_ROOT_DIV 137 |
||||
#define IMX7D_MIPI_DPHY_ROOT_CLK 138 |
||||
#define IMX7D_MIPI_DPHY_ROOT_SRC 139 |
||||
#define IMX7D_MIPI_DPHY_ROOT_CG 140 |
||||
#define IMX7D_MIPI_DPHY_ROOT_DIV 141 |
||||
#define IMX7D_SAI1_ROOT_CLK 142 |
||||
#define IMX7D_SAI1_ROOT_SRC 143 |
||||
#define IMX7D_SAI1_ROOT_CG 144 |
||||
#define IMX7D_SAI1_ROOT_DIV 145 |
||||
#define IMX7D_SAI2_ROOT_CLK 146 |
||||
#define IMX7D_SAI2_ROOT_SRC 147 |
||||
#define IMX7D_SAI2_ROOT_CG 148 |
||||
#define IMX7D_SAI2_ROOT_DIV 149 |
||||
#define IMX7D_SAI3_ROOT_CLK 150 |
||||
#define IMX7D_SAI3_ROOT_SRC 151 |
||||
#define IMX7D_SAI3_ROOT_CG 152 |
||||
#define IMX7D_SAI3_ROOT_DIV 153 |
||||
#define IMX7D_SPDIF_ROOT_CLK 154 |
||||
#define IMX7D_SPDIF_ROOT_SRC 155 |
||||
#define IMX7D_SPDIF_ROOT_CG 156 |
||||
#define IMX7D_SPDIF_ROOT_DIV 157 |
||||
#define IMX7D_ENET1_REF_ROOT_CLK 158 |
||||
#define IMX7D_ENET1_REF_ROOT_SRC 159 |
||||
#define IMX7D_ENET1_REF_ROOT_CG 160 |
||||
#define IMX7D_ENET1_REF_ROOT_DIV 161 |
||||
#define IMX7D_ENET1_TIME_ROOT_CLK 162 |
||||
#define IMX7D_ENET1_TIME_ROOT_SRC 163 |
||||
#define IMX7D_ENET1_TIME_ROOT_CG 164 |
||||
#define IMX7D_ENET1_TIME_ROOT_DIV 165 |
||||
#define IMX7D_ENET2_REF_ROOT_CLK 166 |
||||
#define IMX7D_ENET2_REF_ROOT_SRC 167 |
||||
#define IMX7D_ENET2_REF_ROOT_CG 168 |
||||
#define IMX7D_ENET2_REF_ROOT_DIV 169 |
||||
#define IMX7D_ENET2_TIME_ROOT_CLK 170 |
||||
#define IMX7D_ENET2_TIME_ROOT_SRC 171 |
||||
#define IMX7D_ENET2_TIME_ROOT_CG 172 |
||||
#define IMX7D_ENET2_TIME_ROOT_DIV 173 |
||||
#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 |
||||
#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 |
||||
#define IMX7D_ENET_PHY_REF_ROOT_CG 176 |
||||
#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 |
||||
#define IMX7D_EIM_ROOT_CLK 178 |
||||
#define IMX7D_EIM_ROOT_SRC 179 |
||||
#define IMX7D_EIM_ROOT_CG 180 |
||||
#define IMX7D_EIM_ROOT_DIV 181 |
||||
#define IMX7D_NAND_ROOT_CLK 182 |
||||
#define IMX7D_NAND_ROOT_SRC 183 |
||||
#define IMX7D_NAND_ROOT_CG 184 |
||||
#define IMX7D_NAND_ROOT_DIV 185 |
||||
#define IMX7D_QSPI_ROOT_CLK 186 |
||||
#define IMX7D_QSPI_ROOT_SRC 187 |
||||
#define IMX7D_QSPI_ROOT_CG 188 |
||||
#define IMX7D_QSPI_ROOT_DIV 189 |
||||
#define IMX7D_USDHC1_ROOT_CLK 190 |
||||
#define IMX7D_USDHC1_ROOT_SRC 191 |
||||
#define IMX7D_USDHC1_ROOT_CG 192 |
||||
#define IMX7D_USDHC1_ROOT_DIV 193 |
||||
#define IMX7D_USDHC2_ROOT_CLK 194 |
||||
#define IMX7D_USDHC2_ROOT_SRC 195 |
||||
#define IMX7D_USDHC2_ROOT_CG 196 |
||||
#define IMX7D_USDHC2_ROOT_DIV 197 |
||||
#define IMX7D_USDHC3_ROOT_CLK 198 |
||||
#define IMX7D_USDHC3_ROOT_SRC 199 |
||||
#define IMX7D_USDHC3_ROOT_CG 200 |
||||
#define IMX7D_USDHC3_ROOT_DIV 201 |
||||
#define IMX7D_CAN1_ROOT_CLK 202 |
||||
#define IMX7D_CAN1_ROOT_SRC 203 |
||||
#define IMX7D_CAN1_ROOT_CG 204 |
||||
#define IMX7D_CAN1_ROOT_DIV 205 |
||||
#define IMX7D_CAN2_ROOT_CLK 206 |
||||
#define IMX7D_CAN2_ROOT_SRC 207 |
||||
#define IMX7D_CAN2_ROOT_CG 208 |
||||
#define IMX7D_CAN2_ROOT_DIV 209 |
||||
#define IMX7D_I2C1_ROOT_CLK 210 |
||||
#define IMX7D_I2C1_ROOT_SRC 211 |
||||
#define IMX7D_I2C1_ROOT_CG 212 |
||||
#define IMX7D_I2C1_ROOT_DIV 213 |
||||
#define IMX7D_I2C2_ROOT_CLK 214 |
||||
#define IMX7D_I2C2_ROOT_SRC 215 |
||||
#define IMX7D_I2C2_ROOT_CG 216 |
||||
#define IMX7D_I2C2_ROOT_DIV 217 |
||||
#define IMX7D_I2C3_ROOT_CLK 218 |
||||
#define IMX7D_I2C3_ROOT_SRC 219 |
||||
#define IMX7D_I2C3_ROOT_CG 220 |
||||
#define IMX7D_I2C3_ROOT_DIV 221 |
||||
#define IMX7D_I2C4_ROOT_CLK 222 |
||||
#define IMX7D_I2C4_ROOT_SRC 223 |
||||
#define IMX7D_I2C4_ROOT_CG 224 |
||||
#define IMX7D_I2C4_ROOT_DIV 225 |
||||
#define IMX7D_UART1_ROOT_CLK 226 |
||||
#define IMX7D_UART1_ROOT_SRC 227 |
||||
#define IMX7D_UART1_ROOT_CG 228 |
||||
#define IMX7D_UART1_ROOT_DIV 229 |
||||
#define IMX7D_UART2_ROOT_CLK 230 |
||||
#define IMX7D_UART2_ROOT_SRC 231 |
||||
#define IMX7D_UART2_ROOT_CG 232 |
||||
#define IMX7D_UART2_ROOT_DIV 233 |
||||
#define IMX7D_UART3_ROOT_CLK 234 |
||||
#define IMX7D_UART3_ROOT_SRC 235 |
||||
#define IMX7D_UART3_ROOT_CG 236 |
||||
#define IMX7D_UART3_ROOT_DIV 237 |
||||
#define IMX7D_UART4_ROOT_CLK 238 |
||||
#define IMX7D_UART4_ROOT_SRC 239 |
||||
#define IMX7D_UART4_ROOT_CG 240 |
||||
#define IMX7D_UART4_ROOT_DIV 241 |
||||
#define IMX7D_UART5_ROOT_CLK 242 |
||||
#define IMX7D_UART5_ROOT_SRC 243 |
||||
#define IMX7D_UART5_ROOT_CG 244 |
||||
#define IMX7D_UART5_ROOT_DIV 245 |
||||
#define IMX7D_UART6_ROOT_CLK 246 |
||||
#define IMX7D_UART6_ROOT_SRC 247 |
||||
#define IMX7D_UART6_ROOT_CG 248 |
||||
#define IMX7D_UART6_ROOT_DIV 249 |
||||
#define IMX7D_UART7_ROOT_CLK 250 |
||||
#define IMX7D_UART7_ROOT_SRC 251 |
||||
#define IMX7D_UART7_ROOT_CG 252 |
||||
#define IMX7D_UART7_ROOT_DIV 253 |
||||
#define IMX7D_ECSPI1_ROOT_CLK 254 |
||||
#define IMX7D_ECSPI1_ROOT_SRC 255 |
||||
#define IMX7D_ECSPI1_ROOT_CG 256 |
||||
#define IMX7D_ECSPI1_ROOT_DIV 257 |
||||
#define IMX7D_ECSPI2_ROOT_CLK 258 |
||||
#define IMX7D_ECSPI2_ROOT_SRC 259 |
||||
#define IMX7D_ECSPI2_ROOT_CG 260 |
||||
#define IMX7D_ECSPI2_ROOT_DIV 261 |
||||
#define IMX7D_ECSPI3_ROOT_CLK 262 |
||||
#define IMX7D_ECSPI3_ROOT_SRC 263 |
||||
#define IMX7D_ECSPI3_ROOT_CG 264 |
||||
#define IMX7D_ECSPI3_ROOT_DIV 265 |
||||
#define IMX7D_ECSPI4_ROOT_CLK 266 |
||||
#define IMX7D_ECSPI4_ROOT_SRC 267 |
||||
#define IMX7D_ECSPI4_ROOT_CG 268 |
||||
#define IMX7D_ECSPI4_ROOT_DIV 269 |
||||
#define IMX7D_PWM1_ROOT_CLK 270 |
||||
#define IMX7D_PWM1_ROOT_SRC 271 |
||||
#define IMX7D_PWM1_ROOT_CG 272 |
||||
#define IMX7D_PWM1_ROOT_DIV 273 |
||||
#define IMX7D_PWM2_ROOT_CLK 274 |
||||
#define IMX7D_PWM2_ROOT_SRC 275 |
||||
#define IMX7D_PWM2_ROOT_CG 276 |
||||
#define IMX7D_PWM2_ROOT_DIV 277 |
||||
#define IMX7D_PWM3_ROOT_CLK 278 |
||||
#define IMX7D_PWM3_ROOT_SRC 279 |
||||
#define IMX7D_PWM3_ROOT_CG 280 |
||||
#define IMX7D_PWM3_ROOT_DIV 281 |
||||
#define IMX7D_PWM4_ROOT_CLK 282 |
||||
#define IMX7D_PWM4_ROOT_SRC 283 |
||||
#define IMX7D_PWM4_ROOT_CG 284 |
||||
#define IMX7D_PWM4_ROOT_DIV 285 |
||||
#define IMX7D_FLEXTIMER1_ROOT_CLK 286 |
||||
#define IMX7D_FLEXTIMER1_ROOT_SRC 287 |
||||
#define IMX7D_FLEXTIMER1_ROOT_CG 288 |
||||
#define IMX7D_FLEXTIMER1_ROOT_DIV 289 |
||||
#define IMX7D_FLEXTIMER2_ROOT_CLK 290 |
||||
#define IMX7D_FLEXTIMER2_ROOT_SRC 291 |
||||
#define IMX7D_FLEXTIMER2_ROOT_CG 292 |
||||
#define IMX7D_FLEXTIMER2_ROOT_DIV 293 |
||||
#define IMX7D_SIM1_ROOT_CLK 294 |
||||
#define IMX7D_SIM1_ROOT_SRC 295 |
||||
#define IMX7D_SIM1_ROOT_CG 296 |
||||
#define IMX7D_SIM1_ROOT_DIV 297 |
||||
#define IMX7D_SIM2_ROOT_CLK 298 |
||||
#define IMX7D_SIM2_ROOT_SRC 299 |
||||
#define IMX7D_SIM2_ROOT_CG 300 |
||||
#define IMX7D_SIM2_ROOT_DIV 301 |
||||
#define IMX7D_GPT1_ROOT_CLK 302 |
||||
#define IMX7D_GPT1_ROOT_SRC 303 |
||||
#define IMX7D_GPT1_ROOT_CG 304 |
||||
#define IMX7D_GPT1_ROOT_DIV 305 |
||||
#define IMX7D_GPT2_ROOT_CLK 306 |
||||
#define IMX7D_GPT2_ROOT_SRC 307 |
||||
#define IMX7D_GPT2_ROOT_CG 308 |
||||
#define IMX7D_GPT2_ROOT_DIV 309 |
||||
#define IMX7D_GPT3_ROOT_CLK 310 |
||||
#define IMX7D_GPT3_ROOT_SRC 311 |
||||
#define IMX7D_GPT3_ROOT_CG 312 |
||||
#define IMX7D_GPT3_ROOT_DIV 313 |
||||
#define IMX7D_GPT4_ROOT_CLK 314 |
||||
#define IMX7D_GPT4_ROOT_SRC 315 |
||||
#define IMX7D_GPT4_ROOT_CG 316 |
||||
#define IMX7D_GPT4_ROOT_DIV 317 |
||||
#define IMX7D_TRACE_ROOT_CLK 318 |
||||
#define IMX7D_TRACE_ROOT_SRC 319 |
||||
#define IMX7D_TRACE_ROOT_CG 320 |
||||
#define IMX7D_TRACE_ROOT_DIV 321 |
||||
#define IMX7D_WDOG1_ROOT_CLK 322 |
||||
#define IMX7D_WDOG_ROOT_SRC 323 |
||||
#define IMX7D_WDOG_ROOT_CG 324 |
||||
#define IMX7D_WDOG_ROOT_DIV 325 |
||||
#define IMX7D_CSI_MCLK_ROOT_CLK 326 |
||||
#define IMX7D_CSI_MCLK_ROOT_SRC 327 |
||||
#define IMX7D_CSI_MCLK_ROOT_CG 328 |
||||
#define IMX7D_CSI_MCLK_ROOT_DIV 329 |
||||
#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 |
||||
#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 |
||||
#define IMX7D_AUDIO_MCLK_ROOT_CG 332 |
||||
#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 |
||||
#define IMX7D_WRCLK_ROOT_CLK 334 |
||||
#define IMX7D_WRCLK_ROOT_SRC 335 |
||||
#define IMX7D_WRCLK_ROOT_CG 336 |
||||
#define IMX7D_WRCLK_ROOT_DIV 337 |
||||
#define IMX7D_CLKO1_ROOT_SRC 338 |
||||
#define IMX7D_CLKO1_ROOT_CG 339 |
||||
#define IMX7D_CLKO1_ROOT_DIV 340 |
||||
#define IMX7D_CLKO2_ROOT_SRC 341 |
||||
#define IMX7D_CLKO2_ROOT_CG 342 |
||||
#define IMX7D_CLKO2_ROOT_DIV 343 |
||||
#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 |
||||
#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 |
||||
#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 |
||||
#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 |
||||
#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 |
||||
#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 |
||||
#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 |
||||
#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 |
||||
#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 |
||||
#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 |
||||
#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 |
||||
#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 |
||||
#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 |
||||
#define IMX7D_SAI1_ROOT_PRE_DIV 357 |
||||
#define IMX7D_SAI2_ROOT_PRE_DIV 358 |
||||
#define IMX7D_SAI3_ROOT_PRE_DIV 359 |
||||
#define IMX7D_SPDIF_ROOT_PRE_DIV 360 |
||||
#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 |
||||
#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 |
||||
#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 |
||||
#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 |
||||
#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 |
||||
#define IMX7D_EIM_ROOT_PRE_DIV 366 |
||||
#define IMX7D_NAND_ROOT_PRE_DIV 367 |
||||
#define IMX7D_QSPI_ROOT_PRE_DIV 368 |
||||
#define IMX7D_USDHC1_ROOT_PRE_DIV 369 |
||||
#define IMX7D_USDHC2_ROOT_PRE_DIV 370 |
||||
#define IMX7D_USDHC3_ROOT_PRE_DIV 371 |
||||
#define IMX7D_CAN1_ROOT_PRE_DIV 372 |
||||
#define IMX7D_CAN2_ROOT_PRE_DIV 373 |
||||
#define IMX7D_I2C1_ROOT_PRE_DIV 374 |
||||
#define IMX7D_I2C2_ROOT_PRE_DIV 375 |
||||
#define IMX7D_I2C3_ROOT_PRE_DIV 376 |
||||
#define IMX7D_I2C4_ROOT_PRE_DIV 377 |
||||
#define IMX7D_UART1_ROOT_PRE_DIV 378 |
||||
#define IMX7D_UART2_ROOT_PRE_DIV 379 |
||||
#define IMX7D_UART3_ROOT_PRE_DIV 380 |
||||
#define IMX7D_UART4_ROOT_PRE_DIV 381 |
||||
#define IMX7D_UART5_ROOT_PRE_DIV 382 |
||||
#define IMX7D_UART6_ROOT_PRE_DIV 383 |
||||
#define IMX7D_UART7_ROOT_PRE_DIV 384 |
||||
#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 |
||||
#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 |
||||
#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 |
||||
#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 |
||||
#define IMX7D_PWM1_ROOT_PRE_DIV 389 |
||||
#define IMX7D_PWM2_ROOT_PRE_DIV 390 |
||||
#define IMX7D_PWM3_ROOT_PRE_DIV 391 |
||||
#define IMX7D_PWM4_ROOT_PRE_DIV 392 |
||||
#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 |
||||
#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 |
||||
#define IMX7D_SIM1_ROOT_PRE_DIV 395 |
||||
#define IMX7D_SIM2_ROOT_PRE_DIV 396 |
||||
#define IMX7D_GPT1_ROOT_PRE_DIV 397 |
||||
#define IMX7D_GPT2_ROOT_PRE_DIV 398 |
||||
#define IMX7D_GPT3_ROOT_PRE_DIV 399 |
||||
#define IMX7D_GPT4_ROOT_PRE_DIV 400 |
||||
#define IMX7D_TRACE_ROOT_PRE_DIV 401 |
||||
#define IMX7D_WDOG_ROOT_PRE_DIV 402 |
||||
#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 |
||||
#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 |
||||
#define IMX7D_WRCLK_ROOT_PRE_DIV 405 |
||||
#define IMX7D_CLKO1_ROOT_PRE_DIV 406 |
||||
#define IMX7D_CLKO2_ROOT_PRE_DIV 407 |
||||
#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 |
||||
#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 |
||||
#define IMX7D_LVDS1_IN_CLK 410 |
||||
#define IMX7D_LVDS1_OUT_SEL 411 |
||||
#define IMX7D_LVDS1_OUT_CLK 412 |
||||
#define IMX7D_CLK_DUMMY 413 |
||||
#define IMX7D_GPT_3M_CLK 414 |
||||
#define IMX7D_OCRAM_CLK 415 |
||||
#define IMX7D_OCRAM_S_CLK 416 |
||||
#define IMX7D_WDOG2_ROOT_CLK 417 |
||||
#define IMX7D_WDOG3_ROOT_CLK 418 |
||||
#define IMX7D_WDOG4_ROOT_CLK 419 |
||||
#define IMX7D_SDMA_CORE_CLK 420 |
||||
#define IMX7D_USB1_MAIN_480M_CLK 421 |
||||
#define IMX7D_USB_CTRL_CLK 422 |
||||
#define IMX7D_USB_PHY1_CLK 423 |
||||
#define IMX7D_USB_PHY2_CLK 424 |
||||
#define IMX7D_IPG_ROOT_CLK 425 |
||||
#define IMX7D_SAI1_IPG_CLK 426 |
||||
#define IMX7D_SAI2_IPG_CLK 427 |
||||
#define IMX7D_SAI3_IPG_CLK 428 |
||||
#define IMX7D_PLL_AUDIO_TEST_DIV 429 |
||||
#define IMX7D_PLL_AUDIO_POST_DIV 430 |
||||
#define IMX7D_PLL_VIDEO_TEST_DIV 431 |
||||
#define IMX7D_PLL_VIDEO_POST_DIV 432 |
||||
#define IMX7D_MU_ROOT_CLK 433 |
||||
#define IMX7D_SEMA4_HS_ROOT_CLK 434 |
||||
#define IMX7D_PLL_DRAM_TEST_DIV 435 |
||||
#define IMX7D_ADC_ROOT_CLK 436 |
||||
#define IMX7D_CLK_ARM 437 |
||||
#define IMX7D_CKIL 438 |
||||
#define IMX7D_OCOTP_CLK 439 |
||||
#define IMX7D_CLK_END 440 |
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ |
||||
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Reference in new issue