Tom Rini
6 years ago
commit
a376702f76
@ -0,0 +1,90 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Designware APB Timer driver |
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* |
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* Copyright (C) 2018 Marek Vasut <marex@denx.de> |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <clk.h> |
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#include <timer.h> |
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#include <asm/io.h> |
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#include <asm/arch/timer.h> |
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#define DW_APB_LOAD_VAL 0x0 |
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#define DW_APB_CURR_VAL 0x4 |
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#define DW_APB_CTRL 0x8 |
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DECLARE_GLOBAL_DATA_PTR; |
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struct dw_apb_timer_priv { |
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fdt_addr_t regs; |
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}; |
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static int dw_apb_timer_get_count(struct udevice *dev, u64 *count) |
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{ |
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struct dw_apb_timer_priv *priv = dev_get_priv(dev); |
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/*
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* The DW APB counter counts down, but this function |
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* requires the count to be incrementing. Invert the |
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* result. |
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*/ |
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*count = ~readl(priv->regs + DW_APB_CURR_VAL); |
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return 0; |
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} |
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static int dw_apb_timer_probe(struct udevice *dev) |
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{ |
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct dw_apb_timer_priv *priv = dev_get_priv(dev); |
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struct clk clk; |
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int ret; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret) |
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return ret; |
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uc_priv->clock_rate = clk_get_rate(&clk); |
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clk_free(&clk); |
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/* init timer */ |
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writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); |
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writel(0xffffffff, priv->regs + DW_APB_CURR_VAL); |
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setbits_le32(priv->regs + DW_APB_CTRL, 0x3); |
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return 0; |
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} |
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static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct dw_apb_timer_priv *priv = dev_get_priv(dev); |
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priv->regs = dev_read_addr(dev); |
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return 0; |
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} |
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static const struct timer_ops dw_apb_timer_ops = { |
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.get_count = dw_apb_timer_get_count, |
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}; |
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static const struct udevice_id dw_apb_timer_ids[] = { |
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{ .compatible = "snps,dw-apb-timer" }, |
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{} |
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}; |
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U_BOOT_DRIVER(dw_apb_timer) = { |
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.name = "dw_apb_timer", |
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.id = UCLASS_TIMER, |
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.ops = &dw_apb_timer_ops, |
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.probe = dw_apb_timer_probe, |
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.flags = DM_FLAG_PRE_RELOC, |
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.of_match = dw_apb_timer_ids, |
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.ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata, |
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.priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv), |
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}; |
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