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rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

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There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
master
Philipp Tomsich 7 years ago
parent abcde4751e
commit a49773d6cf
2 changed files with 366 additions and 376 deletions
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  1. 376
      arch/arm/include/asm/arch-rockchip/grf_rk3368.h
  2. 366
      drivers/pinctrl/rockchip/pinctrl_rk3368.c

376
arch/arm/include/asm/arch-rockchip/grf_rk3368.h
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@ -100,382 +100,6 @@ struct rk3368_pmu_grf {
check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
check_member(rk3368_pmu_grf, os_reg[0], 0x200);
/*GRF_GPIO0C_IOMUX*/
enum {
GPIO0C7_SHIFT = 14,
GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
GPIO0C7_GPIO = 0,
GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
GPIO0C6_SHIFT = 12,
GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
GPIO0C6_GPIO = 0,
GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
GPIO0C5_SHIFT = 10,
GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
GPIO0C5_GPIO = 0,
GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
GPIO0C4_SHIFT = 8,
GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
GPIO0C4_GPIO = 0,
GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
GPIO0C3_SHIFT = 6,
GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
GPIO0C3_GPIO = 0,
GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
GPIO0C2_SHIFT = 4,
GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
GPIO0C2_GPIO = 0,
GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
GPIO0C1_SHIFT = 2,
GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
GPIO0C1_GPIO = 0,
GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
GPIO0C0_SHIFT = 0,
GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
GPIO0C0_GPIO = 0,
GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
};
/*GRF_GPIO0D_IOMUX*/
enum {
GPIO0D7_SHIFT = 14,
GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
GPIO0D7_GPIO = 0,
GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
GPIO0D6_SHIFT = 12,
GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
GPIO0D6_GPIO = 0,
GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
GPIO0D5_SHIFT = 10,
GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
GPIO0D5_GPIO = 0,
GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
GPIO0D4_SHIFT = 8,
GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
GPIO0D4_GPIO = 0,
GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
GPIO0D3_SHIFT = 6,
GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
GPIO0D3_GPIO = 0,
GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
GPIO0D2_SHIFT = 4,
GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
GPIO0D2_GPIO = 0,
GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
GPIO0D1_SHIFT = 2,
GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
GPIO0D1_GPIO = 0,
GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
GPIO0D0_SHIFT = 0,
GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
GPIO0D0_GPIO = 0,
GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
};
/*GRF_GPIO2A_IOMUX*/
enum {
GPIO2A7_SHIFT = 14,
GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
GPIO2A7_GPIO = 0,
GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
GPIO2A6_SHIFT = 12,
GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
GPIO2A6_GPIO = 0,
GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
GPIO2A5_SHIFT = 10,
GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
GPIO2A5_GPIO = 0,
GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
GPIO2A4_SHIFT = 8,
GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
GPIO2A4_GPIO = 0,
GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
GPIO2A3_SHIFT = 6,
GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
GPIO2A3_GPIO = 0,
GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
GPIO2A2_SHIFT = 4,
GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
GPIO2A2_GPIO = 0,
GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
GPIO2A1_SHIFT = 2,
GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
GPIO2A1_GPIO = 0,
GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
GPIO2A0_SHIFT = 0,
GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
GPIO2A0_GPIO = 0,
GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
};
/*GRF_GPIO2D_IOMUX*/
enum {
GPIO2D7_SHIFT = 14,
GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
GPIO2D7_GPIO = 0,
GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
GPIO2D6_SHIFT = 12,
GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
GPIO2D6_GPIO = 0,
GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
GPIO2D5_SHIFT = 10,
GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
GPIO2D5_GPIO = 0,
GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
GPIO2D4_SHIFT = 8,
GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
GPIO2D4_GPIO = 0,
GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
GPIO2D3_SHIFT = 6,
GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
GPIO2D3_GPIO = 0,
GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
GPIO2D2_SHIFT = 4,
GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
GPIO2D2_GPIO = 0,
GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
GPIO2D1_SHIFT = 2,
GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
GPIO2D1_GPIO = 0,
GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
GPIO2D0_SHIFT = 0,
GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
GPIO2D0_GPIO = 0,
GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
};
/* GRF_GPIO1C_IOMUX */
enum {
GPIO1C7_SHIFT = 14,
GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
GPIO1C7_GPIO = 0,
GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
GPIO1C6_SHIFT = 12,
GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
GPIO1C6_GPIO = 0,
GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
GPIO1C5_SHIFT = 10,
GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
GPIO1C5_GPIO = 0,
GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
GPIO1C4_SHIFT = 8,
GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
GPIO1C4_GPIO = 0,
GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
GPIO1C3_SHIFT = 6,
GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
GPIO1C3_GPIO = 0,
GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
GPIO1C2_SHIFT = 4,
GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
GPIO1C2_GPIO = 0,
GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
};
/* GRF_GPIO1D_IOMUX*/
enum {
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
GPIO1D3_GPIO = 0,
GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
GPIO1D2_GPIO = 0,
GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
GPIO1D1_GPIO = 0,
GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
GPIO1D0_GPIO = 0,
GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
};
/*GRF_GPIO3B_IOMUX*/
enum {
GPIO3B7_SHIFT = 14,
GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
GPIO3B7_GPIO = 0,
GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
GPIO3B6_SHIFT = 12,
GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
GPIO3B6_GPIO = 0,
GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
GPIO3B5_SHIFT = 10,
GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
GPIO3B5_GPIO = 0,
GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
GPIO3B4_SHIFT = 8,
GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
GPIO3B4_GPIO = 0,
GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
GPIO3B3_SHIFT = 6,
GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
GPIO3B3_GPIO = 0,
GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
GPIO3B2_SHIFT = 4,
GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
GPIO3B2_GPIO = 0,
GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
GPIO3B1_SHIFT = 2,
GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
GPIO3B1_GPIO = 0,
GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
GPIO3B0_SHIFT = 0,
GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
GPIO3B0_GPIO = 0,
GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
};
/*GRF_GPIO3C_IOMUX*/
enum {
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
GPIO3C6_GPIO = 0,
GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
GPIO3C5_GPIO = 0,
GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
GPIO3C4_SHIFT = 8,
GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
GPIO3C4_GPIO = 0,
GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
GPIO3C3_SHIFT = 6,
GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
GPIO3C3_GPIO = 0,
GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
GPIO3C2_SHIFT = 4,
GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
GPIO3C2_GPIO = 0,
GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
GPIO3C1_SHIFT = 2,
GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
GPIO3C1_GPIO = 0,
GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
GPIO3C0_SHIFT = 0,
GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
GPIO3C0_GPIO = 0,
GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
};
/*GRF_GPIO3D_IOMUX*/
enum {
GPIO3D4_SHIFT = 8,
GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
GPIO3D4_GPIO = 0,
GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
GPIO3D1_SHIFT = 2,
GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
GPIO3D1_GPIO = 0,
GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
GPIO3D0_SHIFT = 0,
GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
GPIO3D0_GPIO = 0,
GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
};
/* GRF_SOC_CON0 */
enum {
NOC_RSP_ERR_STALL = BIT(9),
MOBILE_DDR_SEL = BIT(4),
DDR0_16BIT_EN = BIT(3),
MSCH0_MAINDDR3_DDR3 = BIT(2),
MSCH0_MAINPARTIALPOP = BIT(1),
UPCTL_C_ACTIVE = BIT(0),
};
/*GRF_SOC_CON11/12/13*/
enum {
MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,

366
drivers/pinctrl/rockchip/pinctrl_rk3368.c
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@ -16,6 +16,372 @@
DECLARE_GLOBAL_DATA_PTR;
/*GRF_GPIO0C_IOMUX*/
enum {
GPIO0C7_SHIFT = 14,
GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
GPIO0C7_GPIO = 0,
GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
GPIO0C6_SHIFT = 12,
GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
GPIO0C6_GPIO = 0,
GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
GPIO0C5_SHIFT = 10,
GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
GPIO0C5_GPIO = 0,
GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
GPIO0C4_SHIFT = 8,
GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
GPIO0C4_GPIO = 0,
GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
GPIO0C3_SHIFT = 6,
GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
GPIO0C3_GPIO = 0,
GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
GPIO0C2_SHIFT = 4,
GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
GPIO0C2_GPIO = 0,
GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
GPIO0C1_SHIFT = 2,
GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
GPIO0C1_GPIO = 0,
GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
GPIO0C0_SHIFT = 0,
GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
GPIO0C0_GPIO = 0,
GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
};
/*GRF_GPIO0D_IOMUX*/
enum {
GPIO0D7_SHIFT = 14,
GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
GPIO0D7_GPIO = 0,
GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
GPIO0D6_SHIFT = 12,
GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
GPIO0D6_GPIO = 0,
GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
GPIO0D5_SHIFT = 10,
GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
GPIO0D5_GPIO = 0,
GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
GPIO0D4_SHIFT = 8,
GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
GPIO0D4_GPIO = 0,
GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
GPIO0D3_SHIFT = 6,
GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
GPIO0D3_GPIO = 0,
GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
GPIO0D2_SHIFT = 4,
GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
GPIO0D2_GPIO = 0,
GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
GPIO0D1_SHIFT = 2,
GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
GPIO0D1_GPIO = 0,
GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
GPIO0D0_SHIFT = 0,
GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
GPIO0D0_GPIO = 0,
GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
};
/*GRF_GPIO2A_IOMUX*/
enum {
GPIO2A7_SHIFT = 14,
GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
GPIO2A7_GPIO = 0,
GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
GPIO2A6_SHIFT = 12,
GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
GPIO2A6_GPIO = 0,
GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
GPIO2A5_SHIFT = 10,
GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
GPIO2A5_GPIO = 0,
GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
GPIO2A4_SHIFT = 8,
GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
GPIO2A4_GPIO = 0,
GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
GPIO2A3_SHIFT = 6,
GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
GPIO2A3_GPIO = 0,
GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
GPIO2A2_SHIFT = 4,
GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
GPIO2A2_GPIO = 0,
GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
GPIO2A1_SHIFT = 2,
GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
GPIO2A1_GPIO = 0,
GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
GPIO2A0_SHIFT = 0,
GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
GPIO2A0_GPIO = 0,
GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
};
/*GRF_GPIO2D_IOMUX*/
enum {
GPIO2D7_SHIFT = 14,
GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
GPIO2D7_GPIO = 0,
GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
GPIO2D6_SHIFT = 12,
GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
GPIO2D6_GPIO = 0,
GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
GPIO2D5_SHIFT = 10,
GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
GPIO2D5_GPIO = 0,
GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
GPIO2D4_SHIFT = 8,
GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
GPIO2D4_GPIO = 0,
GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
GPIO2D3_SHIFT = 6,
GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
GPIO2D3_GPIO = 0,
GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
GPIO2D2_SHIFT = 4,
GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
GPIO2D2_GPIO = 0,
GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
GPIO2D1_SHIFT = 2,
GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
GPIO2D1_GPIO = 0,
GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
GPIO2D0_SHIFT = 0,
GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
GPIO2D0_GPIO = 0,
GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
};
/* GRF_GPIO1C_IOMUX */
enum {
GPIO1C7_SHIFT = 14,
GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
GPIO1C7_GPIO = 0,
GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
GPIO1C6_SHIFT = 12,
GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
GPIO1C6_GPIO = 0,
GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
GPIO1C5_SHIFT = 10,
GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
GPIO1C5_GPIO = 0,
GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
GPIO1C4_SHIFT = 8,
GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
GPIO1C4_GPIO = 0,
GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
GPIO1C3_SHIFT = 6,
GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
GPIO1C3_GPIO = 0,
GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
GPIO1C2_SHIFT = 4,
GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
GPIO1C2_GPIO = 0,
GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
};
/* GRF_GPIO1D_IOMUX*/
enum {
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
GPIO1D3_GPIO = 0,
GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
GPIO1D2_GPIO = 0,
GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
GPIO1D1_GPIO = 0,
GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
GPIO1D0_GPIO = 0,
GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
};
/*GRF_GPIO3B_IOMUX*/
enum {
GPIO3B7_SHIFT = 14,
GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
GPIO3B7_GPIO = 0,
GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
GPIO3B6_SHIFT = 12,
GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
GPIO3B6_GPIO = 0,
GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
GPIO3B5_SHIFT = 10,
GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
GPIO3B5_GPIO = 0,
GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
GPIO3B4_SHIFT = 8,
GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
GPIO3B4_GPIO = 0,
GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
GPIO3B3_SHIFT = 6,
GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
GPIO3B3_GPIO = 0,
GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
GPIO3B2_SHIFT = 4,
GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
GPIO3B2_GPIO = 0,
GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
GPIO3B1_SHIFT = 2,
GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
GPIO3B1_GPIO = 0,
GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
GPIO3B0_SHIFT = 0,
GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
GPIO3B0_GPIO = 0,
GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
};
/*GRF_GPIO3C_IOMUX*/
enum {
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
GPIO3C6_GPIO = 0,
GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
GPIO3C5_GPIO = 0,
GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
GPIO3C4_SHIFT = 8,
GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
GPIO3C4_GPIO = 0,
GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
GPIO3C3_SHIFT = 6,
GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
GPIO3C3_GPIO = 0,
GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
GPIO3C2_SHIFT = 4,
GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
GPIO3C2_GPIO = 0,
GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
GPIO3C1_SHIFT = 2,
GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
GPIO3C1_GPIO = 0,
GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
GPIO3C0_SHIFT = 0,
GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
GPIO3C0_GPIO = 0,
GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
};
/*GRF_GPIO3D_IOMUX*/
enum {
GPIO3D4_SHIFT = 8,
GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
GPIO3D4_GPIO = 0,
GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
GPIO3D1_SHIFT = 2,
GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
GPIO3D1_GPIO = 0,
GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
GPIO3D0_SHIFT = 0,
GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
GPIO3D0_GPIO = 0,
GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
};
struct rk3368_pinctrl_priv {
struct rk3368_grf *grf;
struct rk3368_pmu_grf *pmugrf;

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