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@@ -9,6 +9,8 @@
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9
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9
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#include <common.h>
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#include <linux/bitops.h>
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11
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#include <phy.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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15
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#define PHY_RTL8211x_FORCE_MASTER BIT(1)
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#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
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@@ -78,6 +80,9 @@ static int rtl8211e_probe(struct phy_device *phydev)
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/* RealTek RTL8211x */
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static int rtl8211x_config(struct phy_device *phydev)
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{
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+ struct sunxi_ccm_reg *const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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86
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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87
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88
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/* mask interrupt at init; if the interrupt is
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@@ -86,6 +91,27 @@ static int rtl8211x_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
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MIIM_RTL8211x_PHY_INTR_DIS);
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93
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+ /* Check if device is RTL8211CL or RTL8211E */
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95
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+ if(phydev->drv->uid == 0x1cc912) {
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96
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+ /* On RTL8211E TX delay must be 0 and
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+ * phy must be forced to be master
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98
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+ */
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+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(0));
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+
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+ unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
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102
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+ /* force manual master/slave configuration */
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+ reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
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104
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+ /* force master mode */
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105
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+ reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
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106
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+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
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+
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+ } else {
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+ if(phydev->drv->uid == 0x1cc915) {
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+ /* On RTL8211E make GMAC_TX_CLK_DELAY 2 */
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111
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+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2));
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+ }
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+ }
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+
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if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
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unsigned int reg;
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91
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117
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@@ -112,6 +138,7 @@ static int rtl8211x_config(struct phy_device *phydev)
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138
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
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0);
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}
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+
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/* read interrupt status just to clear it */
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143
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phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
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