Forward port OLIMEX LIME2 Gbit ethernet patch

Required for ethernet to work on some LIME2 revisions.
lime2-spi
Merlijn Wajer 6 years ago
parent aaa9a82581
commit a7944dcc11
  1. 2
      board/sunxi/gmac.c
  2. 11
      drivers/net/phy/micrel_ksz90x1.c
  3. 27
      drivers/net/phy/realtek.c
  4. 35
      drivers/net/phy/smsc.c
  5. 3
      include/configs/sunxi-common.h

@ -24,8 +24,6 @@ void eth_init_board(void)
#ifdef CONFIG_RGMII #ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII); CCM_GMAC_CTRL_GPIT_RGMII);
setbits_le32(&ccm->gmac_clk_cfg,
CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
#else #else
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII); CCM_GMAC_CTRL_GPIT_MII);

@ -13,6 +13,8 @@
#include <errno.h> #include <errno.h>
#include <micrel.h> #include <micrel.h>
#include <phy.h> #include <phy.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
/* /*
* KSZ9021 - KSZ9031 common * KSZ9021 - KSZ9031 common
@ -98,7 +100,7 @@ static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
}; };
static const struct ksz90x1_reg_field ksz9031_clk_grp[] = { static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } { "rxc-skew-ps", 5, 0, 0x7 }, { "txc-skew-ps", 5, 5, 0x17 }
}; };
static int ksz90x1_of_config_group(struct phy_device *phydev, static int ksz90x1_of_config_group(struct phy_device *phydev,
@ -329,6 +331,13 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
static int ksz9031_config(struct phy_device *phydev) static int ksz9031_config(struct phy_device *phydev)
{ {
int ret; int ret;
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg,
CCM_GMAC_CTRL_TX_CLK_DELAY(4));
#endif
ret = ksz9031_of_config(phydev); ret = ksz9031_of_config(phydev);
if (ret) if (ret)

@ -9,6 +9,8 @@
#include <common.h> #include <common.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <phy.h> #include <phy.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#define PHY_RTL8211x_FORCE_MASTER BIT(1) #define PHY_RTL8211x_FORCE_MASTER BIT(1)
#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
@ -78,6 +80,9 @@ static int rtl8211e_probe(struct phy_device *phydev)
/* RealTek RTL8211x */ /* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev) static int rtl8211x_config(struct phy_device *phydev)
{ {
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
/* mask interrupt at init; if the interrupt is /* mask interrupt at init; if the interrupt is
@ -86,6 +91,27 @@ static int rtl8211x_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
MIIM_RTL8211x_PHY_INTR_DIS); MIIM_RTL8211x_PHY_INTR_DIS);
/* Check if device is RTL8211CL or RTL8211E */
if(phydev->drv->uid == 0x1cc912) {
/* On RTL8211E TX delay must be 0 and
* phy must be forced to be master
*/
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(0));
unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
/* force manual master/slave configuration */
reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
/* force master mode */
reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
} else {
if(phydev->drv->uid == 0x1cc915) {
/* On RTL8211E make GMAC_TX_CLK_DELAY 2 */
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2));
}
}
if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
unsigned int reg; unsigned int reg;
@ -112,6 +138,7 @@ static int rtl8211x_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
0); 0);
} }
/* read interrupt status just to clear it */ /* read interrupt status just to clear it */
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);

@ -11,6 +11,8 @@
*/ */
#include <common.h> #include <common.h>
#include <miiphy.h> #include <miiphy.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
/* This code does not check the partner abilities. */ /* This code does not check the partner abilities. */
static int smsc_parse_status(struct phy_device *phydev) static int smsc_parse_status(struct phy_device *phydev)
@ -43,6 +45,30 @@ static int smsc_startup(struct phy_device *phydev)
return smsc_parse_status(phydev); return smsc_parse_status(phydev);
} }
#if 1
static int olinuxino_smsc_startup(struct phy_device *phydev)
{
int ret;
ret = gpio_request(SUNXI_GPA(17), "lan8710-txerr");
if(ret)
return ret;
gpio_direction_output(SUNXI_GPA(17), 0);
ret = genphy_update_link(phydev);
if (ret)
return ret;
return genphy_parse_link(phydev);
}
static int olinuxino_smsc_shutdown(struct phy_device *phydev)
{
sunxi_gpio_set_cfgpin(SUNXI_GPA(17), SUNXI_GPIO_INPUT);
return 0;
}
#endif
static struct phy_driver lan8700_driver = { static struct phy_driver lan8700_driver = {
.name = "SMSC LAN8700", .name = "SMSC LAN8700",
.uid = 0x0007c0c0, .uid = 0x0007c0c0,
@ -69,8 +95,13 @@ static struct phy_driver lan8710_driver = {
.mask = 0xffff0, .mask = 0xffff0,
.features = PHY_BASIC_FEATURES, .features = PHY_BASIC_FEATURES,
.config = &genphy_config_aneg, .config = &genphy_config_aneg,
.startup = &genphy_startup, #if 1
.shutdown = &genphy_shutdown, .startup = &olinuxino_smsc_startup,
.shutdown = &olinuxino_smsc_shutdown,
#else
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
#endif
}; };
static struct phy_driver lan8740_driver = { static struct phy_driver lan8740_driver = {

@ -291,6 +291,9 @@ extern int soft_i2c_gpio_scl;
#ifdef CONFIG_SUN7I_GMAC #ifdef CONFIG_SUN7I_GMAC
#define CONFIG_PHY_REALTEK #define CONFIG_PHY_REALTEK
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
#define CONFIG_PHY_SMSC
#endif #endif
#ifdef CONFIG_USB_EHCI_HCD #ifdef CONFIG_USB_EHCI_HCD

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