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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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master
Tom Rini 9 years ago
parent f5bcfe151e a80a999c9b
commit a85670e40d
15 changed files with 689 additions and 273 deletions
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  1. 4
      arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
  2. 3
      arch/arm/cpu/armv7/mx6/Kconfig
  3. 12
      arch/arm/cpu/armv7/mx6/clock.c
  4. 2
      arch/arm/include/asm/imx-common/iomux-v3.h
  5. 78
      board/congatec/cgtqmx6eval/README
  6. 599
      board/congatec/cgtqmx6eval/cgtqmx6eval.c
  7. 143
      board/congatec/cgtqmx6eval/imximage.cfg
  8. 2
      board/gateworks/gw_ventana/common.c
  9. 2
      board/kosagi/novena/novena.c
  10. 33
      board/toradex/colibri_vf/colibri_vf.c
  11. 5
      configs/cgtqmx6eval_defconfig
  12. 4
      drivers/video/ipu_disp.c
  13. 68
      include/configs/cgtqmx6eval.h
  14. 6
      include/configs/imx6_spl.h
  15. 1
      include/configs/novena.h

4
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
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@ -1221,8 +1221,8 @@ void mxs_power_init(void)
debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315);
#ifdef CONFIG_MX23
debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);

3
arch/arm/cpu/armv7/mx6/Kconfig
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@ -46,6 +46,9 @@ config TARGET_ARISTAINETOS2B
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_CM_FX6
bool "CM-FX6"

12
arch/arm/cpu/armv7/mx6/clock.c
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@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
#if defined(CONFIG_MX6SX)
clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
cfg);
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg)
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |

2
arch/arm/include/asm/imx-common/iomux-v3.h
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@ -236,7 +236,7 @@ void imx_iomux_gpio_get_function(unsigned int gpio,
#if defined(CONFIG_MX6QDL)
#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
#define SETUP_IOMUX_PAD(def) \
if (is_cpu_type(MXC_CPU_MX6Q)) { \
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
imx_iomux_v3_setup_pad(MX6Q_##def); \
} else { \
imx_iomux_v3_setup_pad(MX6DL_##def); \

78
board/congatec/cgtqmx6eval/README
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@ -1,28 +1,70 @@
U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
qmx6 quad module.
U-Boot for the Congatec QMX6 boards
This file contains information for the port of U-Boot to the Congatec
Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
QMX6 boards.
1. Boot source, boot from SD card
1. Building U-boot
------------------
- Build U-boot for Congatec QMX6 boards:
$ make mrproper
$ make cgtqmx6eval_defconfig
$ make
This will generate the following binaries:
- SPL
- u-boot.img
2. Flashing U-boot in the SPI NOR
---------------------------------
By default, the Congatec board can boot only from the SPI-NOR.
But, with the u-boot version provided with the board you can write boot
registers to force the board to reboot and boot from the SD slot. If
"bmode" command is not available from your pre-installed u-boot, these
instruction will produce the same effect:
Copy SPL and u-boot.img to the exported TFTP directory of the
host PC (/tftpboot , for example).
=> sf probe
=> tftp 0x12000000 SPL
=> sf erase 0x0 0x10000
=> sf write 0x12000000 0x400 0x100
=> tftp 0x12000000 u-boot.img
=> sf erase 0x10000 0x70000
=> sf write 0x12000000 0x10000 0x70000
Reboot the board and the new U-boot should come up.
3. Booting from the SD card
---------------------------
- Flash the SPL image into the SD card:
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- Flash the u-boot.img image into the SD card:
sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Insert the SD card into the big slot.
The boot medium of Congatec QMX6 boards is the SPI NOR flash, so boot
the board from SPI first.
conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
conga-QMX6 U-Boot > reset
resetting ...
It is also possible to boot from the SD card slot by using the 'bmode'
command:
The the board will reboot and, if you have written your SD correctly
the board will use u-boot that live into the SD
=> bmode esdhc4
To copy the resulting u-boot.imx to the SD card:
And then the U-boot from the big slot will boot.
dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
Note: If the "bmode" command is not available from your pre-installed U-boot,
these instruction will produce the same effect:
Note: Replace xxx with the device representing the SD card in your system.
=> mw.l 0x20d8040 0x3850
=> mw.l 0x020d8044 0x10000000
=> reset

599
board/congatec/cgtqmx6eval/cgtqmx6eval.c
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@ -18,6 +18,7 @@
#include <asm/imx-common/sata.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <mmc.h>
@ -31,6 +32,8 @@
#include <miiphy.h>
#include <netdev.h>
#include <micrel.h>
#include <spi_flash.h>
#include <spi.h>
DECLARE_GLOBAL_DATA_PTR;
@ -45,6 +48,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
@ -54,114 +61,134 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t enet_pads_ksz9031[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
};
static iomux_v3_cfg_t enet_pads_ar8035[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
};
static iomux_v3_cfg_t const ecspi1_pads[] = {
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
@ -230,13 +257,8 @@ int board_eth_init(bd_t *bis)
unsigned short id1, id2;
int ret;
iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 |
MUX_PAD_CTRL(NO_PAD_CTRL);
/* check whether KSZ9031 or AR8035 has to be configured */
imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035,
ARRAY_SIZE(enet_pads_ar8035));
imx_iomux_v3_setup_pad(enet_reset);
SETUP_IOMUX_PADS(enet_pads_ar8035);
/* phy reset */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
@ -270,13 +292,11 @@ int board_eth_init(bd_t *bis)
gpio_set_value(IMX_GPIO_NR(6, 27), 1);
gpio_set_value(IMX_GPIO_NR(6, 28), 1);
gpio_set_value(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031,
ARRAY_SIZE(enet_pads_ksz9031));
SETUP_IOMUX_PADS(enet_pads_ksz9031);
gpio_set_value(IMX_GPIO_NR(6, 24), 1);
udelay(500);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031,
ARRAY_SIZE(enet_pads_final_ksz9031));
SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
} else if ((id1 == 0x004d) && (id2 == 0xd072)) {
/* configure Atheros AR8035 - actually nothing to do */
printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
@ -378,9 +398,17 @@ int board_phy_config(struct phy_device *phydev)
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
SETUP_IOMUX_PADS(uart2_pads);
}
#ifdef CONFIG_MXC_SPI
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
}
#endif
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},
@ -414,6 +442,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
s32 status = 0;
int i;
@ -421,9 +450,9 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
SETUP_IOMUX_PADS(usdhc2_pads);
SETUP_IOMUX_PADS(usdhc3_pads);
SETUP_IOMUX_PADS(usdhc4_pads);
for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
@ -432,6 +461,14 @@ int board_mmc_init(bd_t *bis)
}
return 0;
#else
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#endif
@ -439,8 +476,7 @@ int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* set daisy chain for otg_pin_id on 6q.
* for 6dl, this bit is reserved
@ -642,11 +678,22 @@ int overwrite_console(void)
return 1;
}
static bool is_mx6q(void)
{
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
return true;
else
return false;
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_display();
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
return 0;
}
@ -655,7 +702,11 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
if (is_mx6q())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
#ifdef CONFIG_CMD_SATA
setup_sata();
@ -666,11 +717,29 @@ int board_init(void)
int checkboard(void)
{
puts("Board: Conga-QEVAL QMX6 Quad\n");
char *type = "unknown";
if (is_cpu_type(MXC_CPU_MX6Q))
type = "Quad";
else if (is_cpu_type(MXC_CPU_MX6D))
type = "Dual";
else if (is_cpu_type(MXC_CPU_MX6DL))
type = "Dual-Lite";
else if (is_cpu_type(MXC_CPU_MX6SOLO))
type = "Solo";
printf("Board: conga-QMX6 %s\n", type);
return 0;
}
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
}
#endif
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
@ -687,3 +756,347 @@ int misc_init_r(void)
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_mx6q())
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <spl.h>
#include <libfdt.h>
#include <spi_flash.h>
#include <spi.h>
const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
.dram_sdclk_1 = 0x00000030,
.dram_cas = 0x00000030,
.dram_ras = 0x00000030,
.dram_reset = 0x00000030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00000030,
.dram_sdodt1 = 0x00000030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_dqm2 = 0x00000030,
.dram_dqm3 = 0x00000030,
.dram_dqm4 = 0x00000030,
.dram_dqm5 = 0x00000030,
.dram_dqm6 = 0x00000030,
.dram_dqm7 = 0x00000030,
};
static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
.dram_sdclk_1 = 0x00000030,
.dram_cas = 0x00000030,
.dram_ras = 0x00000030,
.dram_reset = 0x00000030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00000030,
.dram_sdodt1 = 0x00000030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_dqm2 = 0x00000030,
.dram_dqm3 = 0x00000030,
.dram_dqm4 = 0x00000030,
.dram_dqm5 = 0x00000030,
.dram_dqm6 = 0x00000030,
.dram_dqm7 = 0x00000030,
};
const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
.grp_ddr_type = 0x000C0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
.p0_mpwldectrl0 = 0x0016001A,
.p0_mpwldectrl1 = 0x0023001C,
.p1_mpwldectrl0 = 0x0028003A,
.p1_mpwldectrl1 = 0x001F002C,
.p0_mpdgctrl0 = 0x43440354,
.p0_mpdgctrl1 = 0x033C033C,
.p1_mpdgctrl0 = 0x43300368,
.p1_mpdgctrl1 = 0x03500330,
.p0_mprddlctl = 0x3228242E,
.p1_mprddlctl = 0x2C2C2636,
.p0_mpwrdlctl = 0x36323A38,
.p1_mpwrdlctl = 0x42324440,
};
const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
.p0_mpwldectrl0 = 0x00080016,
.p0_mpwldectrl1 = 0x001D0016,
.p1_mpwldectrl0 = 0x0018002C,
.p1_mpwldectrl1 = 0x000D001D,
.p0_mpdgctrl0 = 0x43200334,
.p0_mpdgctrl1 = 0x0320031C,
.p1_mpdgctrl0 = 0x0344034C,
.p1_mpdgctrl1 = 0x03380314,
.p0_mprddlctl = 0x3E36383A,
.p1_mprddlctl = 0x38363240,
.p0_mpwrdlctl = 0x36364238,
.p1_mpwrdlctl = 0x4230423E,
};
static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
.p0_mpwldectrl0 = 0x00480049,
.p0_mpwldectrl1 = 0x00410044,
.p0_mpdgctrl0 = 0x42480248,
.p0_mpdgctrl1 = 0x023C023C,
.p0_mprddlctl = 0x40424644,
.p0_mpwrdlctl = 0x34323034,
};
const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
.p0_mpwldectrl0 = 0x0043004B,
.p0_mpwldectrl1 = 0x003A003E,
.p1_mpwldectrl0 = 0x0047004F,
.p1_mpwldectrl1 = 0x004E0061,
.p0_mpdgctrl0 = 0x42500250,
.p0_mpdgctrl1 = 0x0238023C,
.p1_mpdgctrl0 = 0x42640264,
.p1_mpdgctrl1 = 0x02500258,
.p0_mprddlctl = 0x40424846,
.p1_mprddlctl = 0x46484842,
.p0_mpwrdlctl = 0x38382C30,
.p1_mpwrdlctl = 0x34343430,
};
static struct mx6_ddr3_cfg mem_ddr_2g = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1310,
.trcmin = 4875,
.trasmin = 3500,
};
static struct mx6_ddr3_cfg mem_ddr_4g = {
.mem_speed = 1600,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1310,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* Define a minimal structure so that the part number can be read via SPL */
struct mfgdata {
unsigned char tsize;
/* size of checksummed part in bytes */
unsigned char ckcnt;
/* checksum corrected byte */
unsigned char cksum;
/* decimal serial number, packed BCD */
unsigned char serial[6];
/* part number, right justified, ASCII */
unsigned char pn[16];
};
static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
{
int remain = len;
unsigned char *sptr = src;
unsigned char *dptr = dst;
while (remain) {
if (*sptr) {
*dptr = *sptr;
dptr++;
}
sptr++;
remain--;
}
*dptr = 0x0;
}
#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
static bool is_2gb(void)
{
struct spi_flash *spi;
int ret;
char buf[sizeof(struct mfgdata)];
struct mfgdata *data = (struct mfgdata *)buf;
unsigned char outbuf[32];
spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
buf);
if (ret)
return false;
/* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
conv_ascii(outbuf, data->pn, sizeof(data->pn));
if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
return true;
else
return false;
}
static void spl_dram_init(int width)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 2,
.walat = 0,
.ralat = 5,
.mif3_mode = 3,
.bi_on = 1,
.sde_to_rst = 0x0d,
.rst_to_cke = 0x20,
};
if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
return;
}
if (is_mx6q()) {
mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
sysinfo.walat = 1;
mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
sysinfo.walat = 1;
mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
}
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Needed for malloc() to work in SPL prior to board_init_r() */
spl_init();
/* DDR initialization */
if (is_cpu_type(MXC_CPU_MX6SOLO))
spl_dram_init(32);
else
spl_dram_init(64);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

143
board/congatec/cgtqmx6eval/imximage.cfg
Unescape View File

@ -1,143 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e0798 0x000C0000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0588 0x00000030
DATA 4 0x020e0594 0x00000030
DATA 4 0x020e056c 0x00000030
DATA 4 0x020e0578 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e057c 0x000c0030
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e05ac 0x00000030
DATA 4 0x020e05b4 0x00000030
DATA 4 0x020e0528 0x00000030
DATA 4 0x020e0520 0x00000030
DATA 4 0x020e0514 0x00000030
DATA 4 0x020e0510 0x00000030
DATA 4 0x020e05bc 0x00000030
DATA 4 0x020e05c4 0x00000030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b4800 0xa1390003
DATA 4 0x021b080c 0x00110019
DATA 4 0x021b0810 0x00260019
DATA 4 0x021b480c 0x001A0031
DATA 4 0x021b4810 0x001A0021
DATA 4 0x021b083c 0x43100316
DATA 4 0x021b0840 0x0306027E
DATA 4 0x021b483c 0x43250330
DATA 4 0x021b4840 0x0322027B
DATA 4 0x021b0848 0x47414146
DATA 4 0x021b4848 0x41434048
DATA 4 0x021b0850 0x41444A44
DATA 4 0x021b4850 0x4B444C46
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b0004 0x00020036
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b000c 0x555A79A4
DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x005A0E21
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04888032
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x09308030
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00011117
DATA 4 0x021b4818 0x00011117
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0404 0x00011006
DATA 4 0x021b001c 0x00000000
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

2
board/gateworks/gw_ventana/common.c
Unescape View File

@ -806,7 +806,7 @@ void setup_pmic(void)
/* Set SWBST to 5.0V and enable */
pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
}
}

2
board/kosagi/novena/novena.c
Unescape View File

@ -216,7 +216,7 @@ int power_init_board(void)
/* Set SWBST to 5.0V and enable (for USB) */
pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
return 0;

33
board/toradex/colibri_vf/colibri_vf.c
Unescape View File

@ -21,6 +21,7 @@
#include <i2c.h>
#include <g_dnl.h>
#include <asm/gpio.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
@ -92,6 +94,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
VF610_PAD_PTC29__GPIO_102,
};
int dram_init(void)
@ -280,7 +283,6 @@ static void setup_iomux_gpio(void)
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
@ -509,6 +511,10 @@ int board_init(void)
setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
#ifdef CONFIG_USB_EHCI_VF
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
#endif
return 0;
}
@ -554,4 +560,29 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
int board_usb_phy_mode(int port)
{
switch (port) {
case 0:
/*
* Port 0 is used only in client mode on Colibri Vybrid modules
* Check for state of USB client gpio pin and accordingly return
* USB_INIT_DEVICE or USB_INIT_HOST.
*/
if (gpio_get_value(USB_CDET_GPIO))
return USB_INIT_DEVICE;
else
return USB_INIT_HOST;
case 1:
/* Port 1 is used only in host mode on Colibri Vybrid modules */
return USB_INIT_HOST;
default:
/*
* There are only two USB controllers on Vybrid. Ideally we will
* not reach here. However return USB_INIT_HOST if we do.
*/
return USB_INIT_HOST;
}
}
#endif

5
configs/cgtqmx6qeval_defconfig → configs/cgtqmx6eval_defconfig
Unescape View File

@ -1,10 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y

4
drivers/video/ipu_disp.c
Unescape View File

@ -611,11 +611,9 @@ void ipu_dp_dc_enable(ipu_channel_t channel)
uint32_t reg;
uint32_t dc_chan;
if (channel == MEM_FG_SYNC)
dc_chan = 5;
if (channel == MEM_DC_SYNC)
dc_chan = 1;
else if (channel == MEM_BG_SYNC)
else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
dc_chan = 5;
else
return;

68
include/configs/cgtqmx6eval.h
Unescape View File

@ -17,10 +17,21 @@
#define CONFIG_MACH_TYPE 4122
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_UART
@ -29,6 +40,16 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* SPI NOR */
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
@ -79,6 +100,18 @@
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "Congatec"
/* USB Device Firmware Update support */
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_DFU_SF
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
@ -128,14 +161,19 @@
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"fdtfile=imx6q-qmx6.dtb\0" \
"fdtfile=undefined\0" \
"fdt_addr_r=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
"dfu_alt_info_spl=spl raw 0x400\0" \
"dfu_alt_info_img=u-boot raw 0x10000\0" \
"dfu_alt_info=spl raw 0x400\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
@ -176,6 +214,13 @@
"else " \
"bootz; " \
"fi;\0" \
"findfdt="\
"if test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-qmx6.dtb; fi; " \
"if test $board_rev = MX6DL ; then " \
"setenv fdtfile imx6dl-qmx6.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; \0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
@ -200,8 +245,11 @@
"else " \
"bootz; " \
"fi;\0" \
"spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
#define CONFIG_BOOTCOMMAND \
"run spilock;" \
"run findfdt; " \
"mmc dev ${mmcdev};" \
"if mmc rescan; then " \
"if run loadbootscript; then " \
@ -233,11 +281,21 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#if defined (CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
#endif /* __CONFIG_CGTQMX6EVAL_H */

6
include/configs/imx6_spl.h
Unescape View File

@ -63,15 +63,15 @@
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_TEXT_BASE 0x87800000
#else
#define CONFIG_SPL_BSS_START_ADDR 0x18200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x18300000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_TEXT_BASE 0x17800000
#endif
#endif

1
include/configs/novena.h
Unescape View File

@ -82,6 +82,7 @@
/* SPL */
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_EXT_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h" /* common IMX6 SPL configuration */

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