* Disable "date" and "sntp" commands on TQM866M which has no RTCmaster
parent
51152c173d
commit
a87589da74
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,41 @@ |
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# INKA 4X0 board:
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#
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# Valid values for TEXT_BASE are:
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#
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# 0xFFE00000 boot high
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#
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# 0x00100000 boot from RAM (for testing only)
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#
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ifndef TEXT_BASE |
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## Standard: boot high
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TEXT_BASE = 0xFFF00000
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## For testing: boot from RAM
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#TEXT_BASE = 0x00100000
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endif |
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,172 @@ |
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/*
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* (C) Copyright 2003-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
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* |
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* (C) Copyright 2004 |
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include <pci.h> |
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#ifndef CFG_RAMBOOT |
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static void sdram_start (int hi_addr) |
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{ |
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long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
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/* unlock mode register */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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#if SDRAM_DDR |
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/* set mode register: extended mode */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
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__asm__ volatile ("sync"); |
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/* set mode register: reset DLL */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
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__asm__ volatile ("sync"); |
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#endif |
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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/* auto refresh */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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/* set mode register */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
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__asm__ volatile ("sync"); |
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/* normal operation */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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} |
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#endif |
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use |
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
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* is something else than 0x00000000. |
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*/ |
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long int initdram (int board_type) |
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{ |
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ulong dramsize = 0; |
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#ifndef CFG_RAMBOOT |
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ulong test1, test2; |
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/* setup SDRAM chip selects */ |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ |
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__asm__ volatile ("sync"); |
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/* setup config registers */ |
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
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__asm__ volatile ("sync"); |
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#if SDRAM_DDR |
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/* set tap delay */ |
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
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__asm__ volatile ("sync"); |
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#endif |
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/* find RAM size using SDRAM CS0 only */ |
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sdram_start(0); |
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
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sdram_start(1); |
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); |
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if (test1 > test2) { |
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sdram_start(0); |
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dramsize = test1; |
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} else { |
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dramsize = test2; |
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} |
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/* memory smaller than 1MB is impossible */ |
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if (dramsize < (1 << 20)) { |
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dramsize = 0; |
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} |
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/* set SDRAM CS0 size according to the amount of RAM found */ |
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if (dramsize > 0) { |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + |
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__builtin_ffs(dramsize >> 20) - 1; |
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} else { |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
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} |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
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#else /* CFG_RAMBOOT */ |
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/* retrieve size of memory connected to SDRAM CS0 */ |
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
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if (dramsize >= 0x13) { |
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dramsize = (1 << (dramsize - 0x13)) << 20; |
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} else { |
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dramsize = 0; |
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} |
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/* retrieve size of memory connected to SDRAM CS1 */ |
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
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if (dramsize2 >= 0x13) { |
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
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} else { |
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dramsize2 = 0; |
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} |
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#endif /* CFG_RAMBOOT */ |
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/* return dramsize + dramsize2; */ |
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return dramsize; |
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} |
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int checkboard (void) |
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{ |
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puts ("Board: HMI1001\n"); |
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return 0; |
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} |
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int misc_init_f (void) |
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{ |
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return 0; |
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} |
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int board_early_init_r (void) |
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{ |
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
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*(vu_long *)MPC5XXX_BOOTCS_START = |
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*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); |
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*(vu_long *)MPC5XXX_BOOTCS_STOP = |
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*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); |
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return 0; |
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} |
@ -0,0 +1,133 @@ |
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/* |
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* (C) Copyright 2003-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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cpu/mpc5xxx/start.o (.text) |
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cpu/mpc5xxx/traps.o (.text) |
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lib_generic/crc32.o (.text) |
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lib_ppc/cache.o (.text) |
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lib_ppc/time.o (.text) |
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. = DEFINED(env_offset) ? env_offset : .; |
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common/environment.o (.ppcenv) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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. = ALIGN(16); |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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|
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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|
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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|
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. = ALIGN(4096); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(4096); |
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__init_end = .; |
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|
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__bss_start = .; |
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.bss : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
@ -0,0 +1,251 @@ |
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/*
|
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* (C) Copyright 2003-2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
||||
#ifndef __CONFIG_H |
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#define __CONFIG_H |
||||
|
||||
/*
|
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* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
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|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ |
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#define CONFIG_HMI1001 1 /* HMI1001 board */ |
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|
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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|
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
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|
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
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|
||||
/*
|
||||
* Supported commands |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
||||
|
||||
#if (TEXT_BASE == 0xFFF00000) /* Boot low */ |
||||
# define CFG_LOWBOOT 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
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|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs" |
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
||||
|
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xFF800000 |
||||
|
||||
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks |
||||
(= chip selects) */ |
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
#define CFG_FLASH_CFI_AMD_RESET |
||||
#define CFG_FLASH_PROTECTION |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x4000 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_DDR 1 |
||||
#define SDRAM_MODE 0x018D0000 |
||||
#define SDRAM_EMODE 0x40090000 |
||||
#define SDRAM_CONTROL 0x714f0f00 |
||||
#define SDRAM_CONFIG1 0x73722930 |
||||
#define SDRAM_CONFIG2 0x47770000 |
||||
#define SDRAM_TAPDELAY 0x10000000 |
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */ |
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#ifdef CONFIG_POST |
||||
/* preserve space for the post_word at end of on-chip SRAM */ |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE |
||||
#else |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE |
||||
#endif |
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
*/ |
||||
#define CFG_GPS_PORT_CONFIG 0x01051004 |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
/* Enable an alternate, more extensive memory test */ |
||||
#define CFG_ALT_MEMTEST |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, |
||||
* which is normally part of the default commands (CFV_CMD_DFL) |
||||
*/ |
||||
#define CONFIG_LOOPW |
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#if defined(CONFIG_MPC5200) |
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CFG_HID0_FINAL HID0_ICE |
||||
#else |
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL 0 |
||||
#endif |
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE |
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
||||
#define CFG_BOOTCS_CFG 0x0004FB00 |
||||
#define CFG_CS0_START CFG_FLASH_BASE |
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE |
||||
|
||||
/* 8Mbit SRAM @0x80100000 */ |
||||
#define CFG_CS1_START 0x80100000 |
||||
#define CFG_CS1_SIZE 0x00100000 |
||||
#define CFG_CS1_CFG 0x19B00 |
||||
|
||||
/* FRAM 32Kbyte @0x80700000 */ |
||||
#define CFG_CS2_START 0x80700000 |
||||
#define CFG_CS2_SIZE 0x00008000 |
||||
#define CFG_CS2_CFG 0x19800 |
||||
|
||||
/* Display H1, Status Inputs, EPLD @0x80600000 */ |
||||
#define CFG_CS3_START 0x80600000 |
||||
#define CFG_CS3_SIZE 0x00000210 |
||||
#define CFG_CS3_CFG 0x9800 |
||||
|
||||
#define CFG_CS_BURST 0x00000000 |
||||
#define CFG_CS_DEADCYCLE 0x33333333 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue