Update max RAM size for debris board * Patch by Travis Sawyer, 08 Apr 2004: Add TLB entry for second DIMM slot on ocotea * Patch by Masami Komiya, 08 Apr 2004: add RTL8169 network drivermaster
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/*
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* rtl8169.c : U-Boot driver for the RealTek RTL8169 |
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* |
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* Masami Komiya (mkomiya@sonare.it) |
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* |
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* Most part is taken from r8169.c of etherboot |
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* |
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*/ |
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/**************************************************************************
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* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit |
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* Written 2003 by Timothy Legge <tlegge@rogers.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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* |
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* Portions of this code based on: |
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* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver |
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* for Linux kernel 2.4.x. |
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* |
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* Written 2002 ShuChen <shuchen@realtek.com.tw> |
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* See Linux Driver for full information |
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* |
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* Linux Driver Version 1.27a, 10.02.2002 |
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* |
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* Thanks to: |
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* Jean Chen of RealTek Semiconductor Corp. for |
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* providing the evaluation NIC used to develop |
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* this driver. RealTek's support for Etherboot |
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* is appreciated. |
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* |
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* REVISION HISTORY: |
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* ================ |
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* |
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* v1.0 11-26-2003 timlegge Initial port of Linux driver |
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* v1.5 01-17-2004 timlegge Initial driver output cleanup |
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* |
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* Indent Options: indent -kr -i8 |
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***************************************************************************/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <asm/io.h> |
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#include <pci.h> |
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ |
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defined(CONFIG_RTL8169) |
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#undef DEBUG_RTL8169 |
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#undef DEBUG_RTL8169_TX |
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#undef DEBUG_RTL8169_RX |
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#define drv_version "v1.5" |
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#define drv_date "01-17-2004" |
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static u32 ioaddr; |
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/* Condensed operations for readability. */ |
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#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) |
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#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) |
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#define currticks() get_timer(0) |
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#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) |
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) |
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/* media options */ |
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#define MAX_UNITS 8 |
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static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; |
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/* MAC address length*/ |
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#define MAC_ADDR_LEN 6 |
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/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ |
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#define MAX_ETH_FRAME_SIZE 1536 |
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#define TX_FIFO_THRESH 256 /* In bytes */ |
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#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ |
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ |
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#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ |
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#define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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#define RX_BUF_LEN 8192 |
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#define RTL_MIN_IO_SIZE 0x80 |
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#define TX_TIMEOUT (6*HZ) |
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/* write/read MMIO register */ |
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#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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#define RTL_R8(reg) readb (ioaddr + (reg)) |
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#define RTL_R16(reg) readw (ioaddr + (reg)) |
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#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
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#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE |
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#define ETH_ALEN MAC_ADDR_LEN |
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#define ETH_ZLEN 60 |
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enum RTL8169_registers { |
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MAC0 = 0, /* Ethernet hardware address. */ |
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MAR0 = 8, /* Multicast filter. */ |
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TxDescStartAddr = 0x20, |
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TxHDescStartAddr = 0x28, |
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FLASH = 0x30, |
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ERSR = 0x36, |
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ChipCmd = 0x37, |
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TxPoll = 0x38, |
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IntrMask = 0x3C, |
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IntrStatus = 0x3E, |
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TxConfig = 0x40, |
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RxConfig = 0x44, |
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RxMissed = 0x4C, |
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Cfg9346 = 0x50, |
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Config0 = 0x51, |
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Config1 = 0x52, |
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Config2 = 0x53, |
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Config3 = 0x54, |
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Config4 = 0x55, |
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Config5 = 0x56, |
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MultiIntr = 0x5C, |
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PHYAR = 0x60, |
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TBICSR = 0x64, |
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TBI_ANAR = 0x68, |
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TBI_LPAR = 0x6A, |
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PHYstatus = 0x6C, |
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RxMaxSize = 0xDA, |
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CPlusCmd = 0xE0, |
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RxDescStartAddr = 0xE4, |
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EarlyTxThres = 0xEC, |
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FuncEvent = 0xF0, |
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FuncEventMask = 0xF4, |
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FuncPresetState = 0xF8, |
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FuncForceEvent = 0xFC, |
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}; |
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enum RTL8169_register_content { |
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/*InterruptStatusBits */ |
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SYSErr = 0x8000, |
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PCSTimeout = 0x4000, |
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SWInt = 0x0100, |
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TxDescUnavail = 0x80, |
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RxFIFOOver = 0x40, |
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RxUnderrun = 0x20, |
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RxOverflow = 0x10, |
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TxErr = 0x08, |
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TxOK = 0x04, |
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RxErr = 0x02, |
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RxOK = 0x01, |
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/*RxStatusDesc */ |
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RxRES = 0x00200000, |
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RxCRC = 0x00080000, |
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RxRUNT = 0x00100000, |
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RxRWT = 0x00400000, |
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/*ChipCmdBits */ |
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CmdReset = 0x10, |
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CmdRxEnb = 0x08, |
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CmdTxEnb = 0x04, |
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RxBufEmpty = 0x01, |
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/*Cfg9346Bits */ |
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Cfg9346_Lock = 0x00, |
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Cfg9346_Unlock = 0xC0, |
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/*rx_mode_bits */ |
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AcceptErr = 0x20, |
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AcceptRunt = 0x10, |
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AcceptBroadcast = 0x08, |
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AcceptMulticast = 0x04, |
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AcceptMyPhys = 0x02, |
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AcceptAllPhys = 0x01, |
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/*RxConfigBits */ |
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RxCfgFIFOShift = 13, |
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RxCfgDMAShift = 8, |
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/*TxConfigBits */ |
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TxInterFrameGapShift = 24, |
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TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
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/*rtl8169_PHYstatus */ |
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TBI_Enable = 0x80, |
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TxFlowCtrl = 0x40, |
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RxFlowCtrl = 0x20, |
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_1000bpsF = 0x10, |
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_100bps = 0x08, |
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_10bps = 0x04, |
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LinkStatus = 0x02, |
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FullDup = 0x01, |
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/*GIGABIT_PHY_registers */ |
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PHY_CTRL_REG = 0, |
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PHY_STAT_REG = 1, |
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PHY_AUTO_NEGO_REG = 4, |
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PHY_1000_CTRL_REG = 9, |
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/*GIGABIT_PHY_REG_BIT */ |
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PHY_Restart_Auto_Nego = 0x0200, |
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PHY_Enable_Auto_Nego = 0x1000, |
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/* PHY_STAT_REG = 1; */ |
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PHY_Auto_Neco_Comp = 0x0020, |
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/* PHY_AUTO_NEGO_REG = 4; */ |
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PHY_Cap_10_Half = 0x0020, |
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PHY_Cap_10_Full = 0x0040, |
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PHY_Cap_100_Half = 0x0080, |
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PHY_Cap_100_Full = 0x0100, |
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/* PHY_1000_CTRL_REG = 9; */ |
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PHY_Cap_1000_Full = 0x0200, |
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PHY_Cap_Null = 0x0, |
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/*_MediaType*/ |
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_10_Half = 0x01, |
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_10_Full = 0x02, |
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_100_Half = 0x04, |
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_100_Full = 0x08, |
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_1000_Full = 0x10, |
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/*_TBICSRBit*/ |
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TBILinkOK = 0x02000000, |
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}; |
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static struct { |
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const char *name; |
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u8 version; /* depend on RTL8169 docs */ |
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u32 RxConfigMask; /* should clear the bits supported by this chip */ |
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} rtl_chip_info[] = { |
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{"RTL-8169", 0x00, 0xff7e1880,}, |
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{"RTL-8169", 0x04, 0xff7e1880,}, |
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}; |
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enum _DescStatusBit { |
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OWNbit = 0x80000000, |
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EORbit = 0x40000000, |
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FSbit = 0x20000000, |
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LSbit = 0x10000000, |
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}; |
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struct TxDesc { |
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u32 status; |
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u32 vlan_tag; |
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u32 buf_addr; |
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u32 buf_Haddr; |
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}; |
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struct RxDesc { |
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u32 status; |
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u32 vlan_tag; |
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u32 buf_addr; |
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u32 buf_Haddr; |
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}; |
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/* Define the TX Descriptor */ |
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static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; |
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/* __attribute__ ((aligned(256))); */ |
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/* Create a static buffer of size RX_BUF_SZ for each
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TX Descriptor. All descriptors point to a |
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part of this buffer */ |
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static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; |
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/* Define the RX Descriptor */ |
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static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; |
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/* __attribute__ ((aligned(256))); */ |
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/* Create a static buffer of size RX_BUF_SZ for each
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RX Descriptor All descriptors point to a |
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part of this buffer */ |
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static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; |
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struct rtl8169_private { |
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void *mmio_addr; /* memory map physical address */ |
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int chipset; |
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unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
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unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
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unsigned long dirty_tx; |
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unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ |
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unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ |
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struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ |
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struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ |
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unsigned char *RxBufferRings; /* Index of Rx Buffer */ |
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unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ |
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unsigned char *Tx_skbuff[NUM_TX_DESC]; |
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} tpx; |
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static struct rtl8169_private *tpc; |
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static const u16 rtl8169_intr_mask = |
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SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | |
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TxOK | RxErr | RxOK; |
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static const unsigned int rtl8169_rx_config = |
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(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
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static struct pci_device_id supported[] = { |
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{PCI_VENDOR_ID_REALTEK, 0x8169}, |
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{} |
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}; |
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void mdio_write(int RegAddr, int value) |
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{ |
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int i; |
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RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); |
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udelay(1000); |
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for (i = 2000; i > 0; i--) { |
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/* Check if the RTL8169 has completed writing to the specified MII register */ |
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if (!(RTL_R32(PHYAR) & 0x80000000)) { |
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break; |
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} else { |
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udelay(100); |
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} |
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} |
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} |
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int mdio_read(int RegAddr) |
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{ |
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int i, value = -1; |
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RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); |
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udelay(1000); |
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for (i = 2000; i > 0; i--) { |
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/* Check if the RTL8169 has completed retrieving data from the specified MII register */ |
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if (RTL_R32(PHYAR) & 0x80000000) { |
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value = (int) (RTL_R32(PHYAR) & 0xFFFF); |
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break; |
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} else { |
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udelay(100); |
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} |
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} |
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return value; |
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} |
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
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static int rtl8169_init_board(struct eth_device *dev) |
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{ |
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int i; |
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u32 tmp; |
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#ifdef DEBUG_RTL8169 |
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printf ("%s\n", __FUNCTION__); |
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#endif |
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ioaddr = dev->iobase; |
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/* Soft reset the chip. */ |
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RTL_W8(ChipCmd, CmdReset); |
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/* Check that the chip has finished the reset. */ |
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for (i = 1000; i > 0; i--) |
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if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
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break; |
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else |
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udelay(10); |
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/* identify chip attached to board */ |
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tmp = RTL_R32(TxConfig); |
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tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; |
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for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ |
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if (tmp == rtl_chip_info[i].version) { |
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tpc->chipset = i; |
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goto match; |
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} |
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} |
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/* if unknown chip, assume array element #0, original RTL-8169 in this case */ |
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printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); |
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printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); |
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tpc->chipset = 0; |
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match: |
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return 0; |
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} |
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/**************************************************************************
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RECV - Receive a frame |
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***************************************************************************/ |
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static int rtl_recv(struct eth_device *dev) |
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{ |
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/* return true if there's an ethernet packet ready to read */ |
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/* nic->packet should contain data on return */ |
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/* nic->packetlen should contain length of data */ |
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int cur_rx; |
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int length = 0; |
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#ifdef DEBUG_RTL8169_RX |
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printf ("%s\n", __FUNCTION__); |
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#endif |
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ioaddr = dev->iobase; |
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cur_rx = tpc->cur_rx; |
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if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { |
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if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { |
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unsigned char rxdata[RX_BUF_LEN]; |
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length = (int) (tpc->RxDescArray[cur_rx]. |
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status & 0x00001FFF) - 4; |
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memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); |
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NetReceive(rxdata, length); |
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if (cur_rx == NUM_RX_DESC - 1) |
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tpc->RxDescArray[cur_rx].status = |
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(OWNbit | EORbit) + RX_BUF_SIZE; |
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else |
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tpc->RxDescArray[cur_rx].status = |
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OWNbit + RX_BUF_SIZE; |
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tpc->RxDescArray[cur_rx].buf_addr = |
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virt_to_bus(tpc->RxBufferRing[cur_rx]); |
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} else { |
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puts("Error Rx"); |
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} |
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cur_rx = (cur_rx + 1) % NUM_RX_DESC; |
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tpc->cur_rx = cur_rx; |
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return 1; |
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} |
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tpc->cur_rx = cur_rx; |
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return (0); /* initially as this is called to flush the input */ |
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} |
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#define HZ 1000 |
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/**************************************************************************
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SEND - Transmit a frame |
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***************************************************************************/ |
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static int rtl_send(struct eth_device *dev, volatile void *packet, int length) |
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{ |
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/* send the packet to destination */ |
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u32 to; |
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u8 *ptxb; |
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int entry = tpc->cur_tx % NUM_TX_DESC; |
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u32 len = length; |
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#ifdef DEBUG_RTL8169_TX |
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int stime = currticks(); |
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printf ("%s\n", __FUNCTION__); |
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printf("sending %d bytes\n", len); |
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#endif |
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ioaddr = dev->iobase; |
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/* point to the current txb incase multiple tx_rings are used */ |
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ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; |
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memcpy(ptxb, (char *)packet, (int)length); |
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while (len < ETH_ZLEN) |
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ptxb[len++] = '\0'; |
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tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); |
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if (entry != (NUM_TX_DESC - 1)) { |
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tpc->TxDescArray[entry].status = |
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(OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? |
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len : ETH_ZLEN); |
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} else { |
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tpc->TxDescArray[entry].status = |
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(OWNbit | EORbit | FSbit | LSbit) | |
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((len > ETH_ZLEN) ? length : ETH_ZLEN); |
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} |
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RTL_W8(TxPoll, 0x40); /* set polling bit */ |
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tpc->cur_tx++; |
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to = currticks() + TX_TIMEOUT; |
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while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ |
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if (currticks() >= to) { |
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#ifdef DEBUG_RTL8169_TX |
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puts ("tx timeout/error\n"); |
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printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); |
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#endif |
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return 0; |
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} else { |
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#ifdef DEBUG_RTL8169_TX |
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puts("tx done\n"); |
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#endif |
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return length; |
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} |
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} |
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static void rtl8169_set_rx_mode(struct eth_device *dev) |
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{ |
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u32 mc_filter[2]; /* Multicast hash filter */ |
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int rx_mode; |
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u32 tmp = 0; |
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#ifdef DEBUG_RTL8169 |
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printf ("%s\n", __FUNCTION__); |
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#endif |
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/* IFF_ALLMULTI */ |
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/* Too many to filter perfectly -- accept all multicasts. */ |
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rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
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mc_filter[1] = mc_filter[0] = 0xffffffff; |
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tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & |
||||
rtl_chip_info[tpc->chipset].RxConfigMask); |
||||
|
||||
RTL_W32(RxConfig, tmp); |
||||
RTL_W32(MAR0 + 0, mc_filter[0]); |
||||
RTL_W32(MAR0 + 4, mc_filter[1]); |
||||
} |
||||
|
||||
static void rtl8169_hw_start(struct eth_device *dev) |
||||
{ |
||||
u32 i; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
int stime = currticks(); |
||||
printf ("%s\n", __FUNCTION__); |
||||
#endif |
||||
|
||||
#if 0 |
||||
/* Soft reset the chip. */ |
||||
RTL_W8(ChipCmd, CmdReset); |
||||
|
||||
/* Check that the chip has finished the reset. */ |
||||
for (i = 1000; i > 0; i--) { |
||||
if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
||||
break; |
||||
else |
||||
udelay(10); |
||||
} |
||||
#endif |
||||
|
||||
RTL_W8(Cfg9346, Cfg9346_Unlock); |
||||
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
||||
RTL_W8(EarlyTxThres, EarlyTxThld); |
||||
|
||||
/* For gigabit rtl8169 */ |
||||
RTL_W16(RxMaxSize, RxPacketMaxSize); |
||||
|
||||
/* Set Rx Config register */ |
||||
i = rtl8169_rx_config | (RTL_R32(RxConfig) & |
||||
rtl_chip_info[tpc->chipset].RxConfigMask); |
||||
RTL_W32(RxConfig, i); |
||||
|
||||
/* Set DMA burst size and Interframe Gap Time */ |
||||
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
||||
(InterFrameGap << TxInterFrameGapShift)); |
||||
|
||||
|
||||
tpc->cur_rx = 0; |
||||
|
||||
RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); |
||||
RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); |
||||
RTL_W8(Cfg9346, Cfg9346_Lock); |
||||
udelay(10); |
||||
|
||||
RTL_W32(RxMissed, 0); |
||||
|
||||
rtl8169_set_rx_mode(dev); |
||||
|
||||
/* no early-rx interrupts */ |
||||
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); |
||||
#endif |
||||
} |
||||
|
||||
static void rtl8169_init_ring(struct eth_device *dev) |
||||
{ |
||||
int i; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
int stime = currticks(); |
||||
printf ("%s\n", __FUNCTION__); |
||||
#endif |
||||
|
||||
tpc->cur_rx = 0; |
||||
tpc->cur_tx = 0; |
||||
tpc->dirty_tx = 0; |
||||
memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); |
||||
memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); |
||||
|
||||
for (i = 0; i < NUM_TX_DESC; i++) { |
||||
tpc->Tx_skbuff[i] = &txb[i]; |
||||
} |
||||
|
||||
for (i = 0; i < NUM_RX_DESC; i++) { |
||||
if (i == (NUM_RX_DESC - 1)) |
||||
tpc->RxDescArray[i].status = |
||||
(OWNbit | EORbit) + RX_BUF_SIZE; |
||||
else |
||||
tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; |
||||
|
||||
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; |
||||
tpc->RxDescArray[i].buf_addr = |
||||
virt_to_bus(tpc->RxBufferRing[i]); |
||||
} |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); |
||||
#endif |
||||
} |
||||
|
||||
/**************************************************************************
|
||||
RESET - Finish setting up the ethernet interface |
||||
***************************************************************************/ |
||||
static void rtl_reset(struct eth_device *dev, bd_t *bis) |
||||
{ |
||||
int i; |
||||
u8 diff; |
||||
u32 TxPhyAddr, RxPhyAddr; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
int stime = currticks(); |
||||
printf ("%s\n", __FUNCTION__); |
||||
#endif |
||||
|
||||
tpc->TxDescArrays = tx_ring; |
||||
if (tpc->TxDescArrays == 0) |
||||
puts("Allot Error"); |
||||
/* Tx Desscriptor needs 256 bytes alignment; */ |
||||
TxPhyAddr = virt_to_bus(tpc->TxDescArrays); |
||||
diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); |
||||
TxPhyAddr += diff; |
||||
tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); |
||||
|
||||
tpc->RxDescArrays = rx_ring; |
||||
/* Rx Desscriptor needs 256 bytes alignment; */ |
||||
RxPhyAddr = virt_to_bus(tpc->RxDescArrays); |
||||
diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); |
||||
RxPhyAddr += diff; |
||||
tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); |
||||
|
||||
if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { |
||||
puts("Allocate RxDescArray or TxDescArray failed\n"); |
||||
return; |
||||
} |
||||
|
||||
rtl8169_init_ring(dev); |
||||
rtl8169_hw_start(dev); |
||||
/* Construct a perfect filter frame with the mac address as first match
|
||||
* and broadcast for all others */ |
||||
for (i = 0; i < 192; i++) |
||||
txb[i] = 0xFF; |
||||
|
||||
txb[0] = dev->enetaddr[0]; |
||||
txb[1] = dev->enetaddr[1]; |
||||
txb[2] = dev->enetaddr[2]; |
||||
txb[3] = dev->enetaddr[3]; |
||||
txb[4] = dev->enetaddr[4]; |
||||
txb[5] = dev->enetaddr[5]; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); |
||||
#endif |
||||
} |
||||
|
||||
/**************************************************************************
|
||||
HALT - Turn off ethernet interface |
||||
***************************************************************************/ |
||||
static void rtl_halt(struct eth_device *dev) |
||||
{ |
||||
int i; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf ("%s\n", __FUNCTION__); |
||||
#endif |
||||
|
||||
ioaddr = dev->iobase; |
||||
|
||||
/* Stop the chip's Tx and Rx DMA processes. */ |
||||
RTL_W8(ChipCmd, 0x00); |
||||
|
||||
/* Disable interrupts by clearing the interrupt mask. */ |
||||
RTL_W16(IntrMask, 0x0000); |
||||
|
||||
RTL_W32(RxMissed, 0); |
||||
|
||||
tpc->TxDescArrays = NULL; |
||||
tpc->RxDescArrays = NULL; |
||||
tpc->TxDescArray = NULL; |
||||
tpc->RxDescArray = NULL; |
||||
for (i = 0; i < NUM_RX_DESC; i++) { |
||||
tpc->RxBufferRing[i] = NULL; |
||||
} |
||||
} |
||||
|
||||
/**************************************************************************
|
||||
INIT - Look for an adapter, this routine's visible to the outside |
||||
***************************************************************************/ |
||||
|
||||
#define board_found 1 |
||||
#define valid_link 0 |
||||
static int rtl_init(struct eth_device *dev, bd_t *bis) |
||||
{ |
||||
static int board_idx = -1; |
||||
static int printed_version = 0; |
||||
int i, rc; |
||||
int option = -1, Cap10_100 = 0, Cap1000 = 0; |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf ("%s\n", __FUNCTION__); |
||||
#endif |
||||
|
||||
ioaddr = dev->iobase; |
||||
|
||||
board_idx++; |
||||
|
||||
printed_version = 1; |
||||
|
||||
/* point to private storage */ |
||||
tpc = &tpx; |
||||
|
||||
rc = rtl8169_init_board(dev); |
||||
if (rc) |
||||
return rc; |
||||
|
||||
/* Get MAC address. FIXME: read EEPROM */ |
||||
for (i = 0; i < MAC_ADDR_LEN; i++) |
||||
dev->enetaddr[i] = RTL_R8(MAC0 + i); |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
printf("MAC Address"); |
||||
for (i = 0; i < MAC_ADDR_LEN; i++) |
||||
printf(":%02x", dev->enetaddr[i]); |
||||
putc('\n'); |
||||
#endif |
||||
|
||||
#ifdef DEBUG_RTL8169 |
||||
/* Print out some hardware info */ |
||||
printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); |
||||
#endif |
||||
|
||||
/* if TBI is not endbled */ |
||||
if (!(RTL_R8(PHYstatus) & TBI_Enable)) { |
||||
int val = mdio_read(PHY_AUTO_NEGO_REG); |
||||
|
||||
option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; |
||||
/* Force RTL8169 in 10/100/1000 Full/Half mode. */ |
||||
if (option > 0) { |
||||
#ifdef DEBUG_RTL8169 |
||||
printf("%s: Force-mode Enabled.\n", dev->name); |
||||
#endif |
||||
Cap10_100 = 0, Cap1000 = 0; |
||||
switch (option) { |
||||
case _10_Half: |
||||
Cap10_100 = PHY_Cap_10_Half; |
||||
Cap1000 = PHY_Cap_Null; |
||||
break; |
||||
case _10_Full: |
||||
Cap10_100 = PHY_Cap_10_Full; |
||||
Cap1000 = PHY_Cap_Null; |
||||
break; |
||||
case _100_Half: |
||||
Cap10_100 = PHY_Cap_100_Half; |
||||
Cap1000 = PHY_Cap_Null; |
||||
break; |
||||
case _100_Full: |
||||
Cap10_100 = PHY_Cap_100_Full; |
||||
Cap1000 = PHY_Cap_Null; |
||||
break; |
||||
case _1000_Full: |
||||
Cap10_100 = PHY_Cap_Null; |
||||
Cap1000 = PHY_Cap_1000_Full; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ |
||||
mdio_write(PHY_1000_CTRL_REG, Cap1000); |
||||
} else { |
||||
#ifdef DEBUG_RTL8169 |
||||
printf("%s: Auto-negotiation Enabled.\n", |
||||
dev->name); |
||||
#endif |
||||
/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ |
||||
mdio_write(PHY_AUTO_NEGO_REG, |
||||
PHY_Cap_10_Half | PHY_Cap_10_Full | |
||||
PHY_Cap_100_Half | PHY_Cap_100_Full | |
||||
(val & 0x1F)); |
||||
|
||||
/* enable 1000 Full Mode */ |
||||
mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); |
||||
|
||||
} |
||||
|
||||
/* Enable auto-negotiation and restart auto-nigotiation */ |
||||
mdio_write(PHY_CTRL_REG, |
||||
PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); |
||||
udelay(100); |
||||
|
||||
/* wait for auto-negotiation process */ |
||||
for (i = 10000; i > 0; i--) { |
||||
/* check if auto-negotiation complete */ |
||||
if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { |
||||
udelay(100); |
||||
option = RTL_R8(PHYstatus); |
||||
if (option & _1000bpsF) { |
||||
#ifdef DEBUG_RTL8169 |
||||
printf("%s: 1000Mbps Full-duplex operation.\n", |
||||
dev->name); |
||||
#endif |
||||
} else { |
||||
#ifdef DEBUG_RTL8169 |
||||
printf |
||||
("%s: %sMbps %s-duplex operation.\n", |
||||
dev->name, |
||||
(option & _100bps) ? "100" : |
||||
"10", |
||||
(option & FullDup) ? "Full" : |
||||
"Half"); |
||||
#endif |
||||
} |
||||
break; |
||||
} else { |
||||
udelay(100); |
||||
} |
||||
} /* end for-loop to wait for auto-negotiation process */ |
||||
|
||||
} else { |
||||
udelay(100); |
||||
#ifdef DEBUG_RTL8169 |
||||
printf |
||||
("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", |
||||
dev->name, |
||||
(RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); |
||||
#endif |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
int rtl8169_initialize(bd_t *bis) |
||||
{ |
||||
pci_dev_t devno; |
||||
int card_number = 0; |
||||
struct eth_device *dev; |
||||
u32 iobase; |
||||
int idx=0; |
||||
|
||||
while(1){ |
||||
/* Find RTL8169 */ |
||||
if ((devno = pci_find_devices(supported, idx++)) < 0) |
||||
break; |
||||
|
||||
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); |
||||
iobase &= ~0xf; |
||||
|
||||
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); |
||||
|
||||
dev = (struct eth_device *)malloc(sizeof *dev); |
||||
|
||||
sprintf (dev->name, "RTL8169#%d", card_number); |
||||
|
||||
dev->priv = (void *) devno; |
||||
dev->iobase = (int)bus_to_phys(iobase); |
||||
|
||||
dev->init = rtl_reset; |
||||
dev->halt = rtl_halt; |
||||
dev->send = rtl_send; |
||||
dev->recv = rtl_recv; |
||||
|
||||
eth_register (dev); |
||||
|
||||
rtl_init(dev, bis); |
||||
|
||||
card_number++; |
||||
} |
||||
return card_number; |
||||
} |
||||
|
||||
#endif |
Loading…
Reference in new issue