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/*
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* A collection of structures, addresses, and values associated with |
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* the Motorola 860 ADS board. Copied from the MBX stuff. |
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* Magnus Damm added defines for 8xxrom and extended bd_info. |
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* Helmut Buchsbaum added bitvalues for BCSRx |
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* |
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
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*/ |
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/* ------------------------------------------------------------------------- */ |
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#ifndef _CONFIG_ADS860_H |
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#define _CONFIG_ADS860_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#include <mpc8xx_irq.h> |
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#define CONFIG_MPC860 1 |
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#define CONFIG_ADS 1 |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 19200 /* console baudrate */ |
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#define CONFIG_PCMCIA 1 /* To enable PCMCIA support */ |
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ |
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#define CFG_I2C_SLAVE 0x7F |
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#define MPC8XX_XIN 32768 /* 32.768 kHz input frequency */ |
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#define MPC8XX_FACT 0x5F6 /* Multiply by 1526 */ |
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/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#if 0 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_BOOTCOMMAND \ |
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm" |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
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#if 0 /* private command defs */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C | \ |
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CFG_CMD_IDE | CFG_CMD_PCMCIA) |
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#endif |
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/* default command defs */ |
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#undef CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ |
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#define CFG_LOAD_ADDR 0x00100000 |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CFG_IMMR 0xfff00000 |
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#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR CFG_IMMR |
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#define CFG_SRAM_BASE 0x00000000 |
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#define CFG_FLASH_BASE 0xfe000000 |
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
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#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#undef CFG_ENV_IS_IN_NVRAM |
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#undef CFG_ENV_IS_IN_EEPROM |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x00040000 |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ |
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/* the other CS:s are determined by looking at parameters in BCSRx */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
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#else |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* set the PLL, the low-power modes and the reset control (15-29) |
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*/ |
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#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \ |
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ |
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SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
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SCCR_DFLCD000 | SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_DER 0 |
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller |
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* differently. Normally, you write the option register |
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* first, and then enable the chip select by writing the |
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* base register. For CS0, you must write the base register |
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* first, followed by the option register. |
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*/ |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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/* the other CS:s are determined by looking at parameters in BCSRx */ |
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#define BCSR_ADDR ((uint) 0xff010000) |
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#define BCSR_SIZE ((uint)(64 * 1024)) |
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#define FLASH_BASE0_PRELIM 0xfe000000 /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ |
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#define CFG_REMAP_OR_AM 0xff000000 /* OR addr mask */ |
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#define CFG_PRELIM_OR_AM 0xffe00000 /* OR addr mask */ |
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
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#ifdef USE_REAL_FLASH_VALUES |
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/*
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* These values fit our FADS860T ... |
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* The "default" behaviour with 1Mbyte initial doesn't work for us! |
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*/ |
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#define CFG_BR0_PRELIM 0x0fe000001 /* Real values for the board */ |
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#define CFG_OR0_PRELIM 0x0ffe00d34 |
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#define CFG_BR2_PRELIM 0x000000081 |
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#define CFG_OR2_PRELIM 0x0ff000800 |
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#else |
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
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#endif |
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/* BCSRx - Board Control and Status Registers */ |
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/* #define CFG_OR1_REMAP CFG_OR0_REMAP */ |
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#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
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#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
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/*
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* Memory Periodic Timer Prescaler |
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*/ |
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/* periodic timer for refresh */ |
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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/*
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* MAMR settings for SDRAM |
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*/ |
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/* 8 column SDRAM */ |
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#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/* 9 column SDRAM */ |
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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#define CFG_MAMR 0x13a01114 |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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/* values according to the manual */ |
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#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
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/*-----------------------------------------------------------------------
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* PCMCIA stuff |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
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#undef CONFIG_IDE_LED /* LED for ide supported */ |
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
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#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ |
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
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#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
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#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ |
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/* #define CFG_ATA_BASE_ADDR 0xFE100000 */ |
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
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#define CFG_ATA_IDE0_OFFSET 0x0000 |
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
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#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ |
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#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ |
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/* (F)ADS bitvalues by Helmut Buchsbaum
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* see MPC8xxADS User's Manual for a proper description |
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* of the following structures |
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*/ |
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#define BCSR0_ERB ((uint)0x80000000) |
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#define BCSR0_IP ((uint)0x40000000) |
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#define BCSR0_BDIS ((uint)0x10000000) |
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#define BCSR0_BPS_MASK ((uint)0x0C000000) |
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#define BCSR0_ISB_MASK ((uint)0x01800000) |
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#define BCSR0_DBGC_MASK ((uint)0x00600000) |
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#define BCSR0_DBPC_MASK ((uint)0x00180000) |
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#define BCSR0_EBDF_MASK ((uint)0x00060000) |
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#define BCSR1_FLASH_EN ((uint)0x80000000) |
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#define BCSR1_DRAM_EN ((uint)0x40000000) |
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#define BCSR1_ETHEN ((uint)0x20000000) |
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#define BCSR1_IRDEN ((uint)0x10000000) |
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
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#define BCSR1_BCSR_EN ((uint)0x02000000) |
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#define BCSR1_RS232EN_1 ((uint)0x01000000) |
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#define BCSR1_PCCEN ((uint)0x00800000) |
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#define BCSR1_PCCVCC0 ((uint)0x00400000) |
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#define BCSR1_PCCVCCON BCSR1_PCCVCC0 |
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
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#define BCSR1_RS232EN_2 ((uint)0x00040000) |
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#define BCSR1_SDRAM_EN ((uint)0x00020000) |
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#define BCSR1_PCCVCC1 ((uint)0x00010000) |
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
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#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
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#define BCSR2_DRAM_PD_SHIFT (23) |
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#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
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#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
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#define BCSR3_DBID_MASK ((ushort)0x3800) |
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#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
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#define BCSR3_BREVNR0 ((ushort)0x0080) |
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#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
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#define BCSR3_BREVN1 ((ushort)0x0008) |
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#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
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#define BCSR4_ETHLOOP ((uint)0x80000000) |
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#define BCSR4_TFPLDL ((uint)0x40000000) |
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#define BCSR4_TPSQEL ((uint)0x20000000) |
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_USB_EN ((uint)0x08000000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC860SAR |
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#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
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#endif /* CONFIG_MPC860SAR */ |
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#ifdef CONFIG_MPC860T |
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#define BCSR4_FETH_EN ((uint)0x08000000) |
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#endif /* CONFIG_MPC860T */ |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_USB_SPEED ((uint)0x04000000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC860T |
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#define BCSR4_FETHCFG0 ((uint)0x04000000) |
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#endif /* CONFIG_MPC860T */ |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_VCCO ((uint)0x02000000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC860T |
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#define BCSR4_FETHFDE ((uint)0x02000000) |
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#endif /* CONFIG_MPC860T */ |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_VIDEO_ON ((uint)0x00800000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC860T |
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#define BCSR4_FETHCFG1 ((uint)0x00400000) |
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#endif /* CONFIG_MPC860T */ |
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#ifdef CONFIG_MPC823 |
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#define BCSR4_VIDEO_RST ((uint)0x00200000) |
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#endif /* CONFIG_MPC823 */ |
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#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHRST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC850 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC850 */ |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/* Machine type
|
||||
*/ |
||||
#define _MACH_8xx (_MACH_ads) |
||||
|
||||
#if 0 |
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
#endif |
||||
#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ |
||||
|
||||
|
||||
/* PCMCIA configuration
|
||||
*/ |
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#endif /* _CONFIG_ADS860_H */ |
@ -0,0 +1,480 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T FADS board. Copied from the MBX stuff. |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/*
|
||||
* 1999-nov-26: The FADS is using the following physical memorymap: |
||||
* |
||||
* ff020000 -> ff02ffff : pcmcia |
||||
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom |
||||
* ff000000 -> ff00ffff : IMAP internal in the cpu |
||||
* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom |
||||
* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#include <mpc8xx_irq.h> |
||||
|
||||
#define CONFIG_MPC860 1 |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_FADS 1 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
|
||||
#if 0 |
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 5000000 /* 5 MHz in */ |
||||
#else |
||||
#define MPC8XX_FACT 12 /* Multiply by 12 */ |
||||
#define MPC8XX_XIN 4000000 /* 4 MHz in */ |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootm 2800100" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "" |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/* ATA / IDE and partition support */ |
||||
#define CONFIG_MAC_PARTITION 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
#define CONFIG_ISO_PARTITION 1 |
||||
#undef CONFIG_ATAPI |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
/* choose SCC1 ethernet (10BASET on motherboard)
|
||||
* or FEC ethernet (10/100 on daughterboard) |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ |
||||
#undef CONFIG_FEC_ENET /* disable FEC ethernet */ |
||||
#else |
||||
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ |
||||
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
||||
#define CFG_DISCOVER_PHY |
||||
#endif |
||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
||||
#endif |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=>" /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
|
||||
#define CFG_FLASH_BASE 0x02800000 |
||||
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
|
||||
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x00040000 |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set the PLL, the low-power modes and the reset control (15-29) |
||||
*/ |
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
#define BCSR_ADDR ((uint) 0xFF010000) |
||||
#define BCSR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES |
||||
/*
|
||||
* These values fit our FADS860T ... |
||||
* The "default" behaviour with 1Mbyte initial doesn't work for us! |
||||
*/ |
||||
#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ |
||||
#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ |
||||
#else |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) |
||||
#endif |
||||
|
||||
/* BCSRx - Board Control and Status Registers */ |
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CFG_MAMR 0x13a01114 |
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/* values according to the manual */ |
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description |
||||
* of the following structures |
||||
*/ |
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000) |
||||
#define BCSR0_IP ((uint)0x40000000) |
||||
#define BCSR0_BDIS ((uint)0x10000000) |
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000) |
||||
#define BCSR0_ISB_MASK ((uint)0x01800000) |
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000) |
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000) |
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000) |
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000) |
||||
#define BCSR1_DRAM_EN ((uint)0x40000000) |
||||
#define BCSR1_ETHEN ((uint)0x20000000) |
||||
#define BCSR1_IRDEN ((uint)0x10000000) |
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
||||
#define BCSR1_BCSR_EN ((uint)0x02000000) |
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000) |
||||
#define BCSR1_PCCEN ((uint)0x00800000) |
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000) |
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000) |
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000) |
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000) |
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT (23) |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHFDE ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHRST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC850 |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
#endif /* CONFIG_MPC850 */ |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/* Machine type
|
||||
*/ |
||||
#define _MACH_8xx (_MACH_fads) |
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */ |
||||
#define CFG_PCMCIA_MEM_ADDR (0x50000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0x54000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0x5C000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
/* we have 8 windows, we take everything up to 60000000 */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0000 |
||||
/*#define CFG_ATA_ALT_OFFSET 0x0100 */ |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
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Reference in new issue