@ -6,7 +6,20 @@
* by t h e F r e e S o f t w a r e F o u n d a t i o n .
* /
# include < c o n f i g . h >
# include < g t 6 4 1 2 0 . h >
# include < a s m / a d d r s p a c e . h >
# include < a s m / r e g d e f . h >
# include < a s m / m a l t a . h >
# ifdef C O N F I G _ S Y S _ B I G _ E N D I A N
# define C P U _ T O _ G T 3 2 ( _ x ) ( ( _ x ) )
# else
# define C P U _ T O _ G T 3 2 ( _ x ) ( \
( ( ( _ x) & 0 x f f ) < < 2 4 ) | ( ( ( _ x ) & 0 x f f00 ) < < 8 ) | \
( ( ( _ x) & 0 x f f00 0 0 ) > > 8 ) | ( ( ( _ x ) & 0 x f f00 0 0 0 0 ) > > 2 4 ) )
# endif
.text
.set noreorder
@ -15,5 +28,44 @@
.globl lowlevel_init
lowlevel_init :
/ *
* Load B A R r e g i s t e r s o f G T 6 4 1 2 0 a s d o n e b y Y A M O N
*
* based o n a p a t c h s e n t b y A n t o n y P a v l o v < a n t o n y n p a v l o v @gmail.com>
* to t h e b a r e b o x m a i l i n g l i s t .
* The s u b j e c t o f t h e o r i g i n a l p a t c h :
* ' MIPS : qemu- m a l t a : a d d Y A M O N - s t y l e G T 6 4 1 2 0 m e m o r y m a p '
* URL :
* http : / / www. m a i l - a r c h i v e . c o m / b a r e b o x @lists.infradead.org/msg06128.html
*
* based o n w r i t e _ b o o t l o a d e r ( ) i n q e m u . g i t / h w / m i p s _ m a l t a . c
* see G T 6 4 1 2 0 m a n u a l a n d q e m u . g i t / h w / g t 6 4 x x x . c f o r d e t a i l s
* /
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
li t 1 , K S E G 1 A D D R ( G T _ D E F _ B A S E )
li t 0 , C P U _ T O _ G T 3 2 ( 0 x d f00 0 0 0 0 )
sw t 0 , G T _ I S D _ O F S ( t 1 )
/* setup MEM-to-PCI0 mapping */
li t 1 , K S E G 1 A D D R ( M A L T A _ G T _ B A S E )
/* setup PCI0 io window to 0x18000000-0x181fffff */
li t 0 , C P U _ T O _ G T 3 2 ( 0 x c00 0 0 0 0 0 )
sw t 0 , G T _ P C I 0 I O L D _ O F S ( t 1 )
li t 0 , C P U _ T O _ G T 3 2 ( 0 x40 0 0 0 0 0 0 )
sw t 0 , G T _ P C I 0 I O H D _ O F S ( t 1 )
/* setup PCI0 mem windows */
li t 0 , C P U _ T O _ G T 3 2 ( 0 x80 0 0 0 0 0 0 )
sw t 0 , G T _ P C I 0 M 0 L D _ O F S ( t 1 )
li t 0 , C P U _ T O _ G T 3 2 ( 0 x3 f00 0 0 0 0 )
sw t 0 , G T _ P C I 0 M 0 H D _ O F S ( t 1 )
li t 0 , C P U _ T O _ G T 3 2 ( 0 x c10 0 0 0 0 0 )
sw t 0 , G T _ P C I 0 M 1 L D _ O F S ( t 1 )
li t 0 , C P U _ T O _ G T 3 2 ( 0 x5 e 0 0 0 0 0 0 )
sw t 0 , G T _ P C I 0 M 1 H D _ O F S ( t 1 )
jr r a
nop