Tom Rini
9 years ago
commit
ad608a21f8
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/*
|
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* Copyright (C) 2014 Free Electrons |
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* |
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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*/ |
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#include <common.h> |
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#include <linux/kernel.h> |
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#include <linux/mtd/nand.h> |
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|
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static const struct nand_sdr_timings onfi_sdr_timings[] = { |
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/* Mode 0 */ |
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{ |
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.tADL_min = 200000, |
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.tALH_min = 20000, |
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.tALS_min = 50000, |
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.tAR_min = 25000, |
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.tCEA_max = 100000, |
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.tCEH_min = 20000, |
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.tCH_min = 20000, |
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.tCHZ_max = 100000, |
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.tCLH_min = 20000, |
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.tCLR_min = 20000, |
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.tCLS_min = 50000, |
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.tCOH_min = 0, |
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.tCS_min = 70000, |
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.tDH_min = 20000, |
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.tDS_min = 40000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 10000, |
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.tITC_max = 1000000, |
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.tRC_min = 100000, |
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.tREA_max = 40000, |
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.tREH_min = 30000, |
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.tRHOH_min = 0, |
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.tRHW_min = 200000, |
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.tRHZ_max = 200000, |
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.tRLOH_min = 0, |
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.tRP_min = 50000, |
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.tRST_max = 250000000000ULL, |
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.tWB_max = 200000, |
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.tRR_min = 40000, |
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.tWC_min = 100000, |
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.tWH_min = 30000, |
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.tWHR_min = 120000, |
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.tWP_min = 50000, |
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.tWW_min = 100000, |
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}, |
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/* Mode 1 */ |
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{ |
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.tADL_min = 100000, |
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.tALH_min = 10000, |
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.tALS_min = 25000, |
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.tAR_min = 10000, |
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.tCEA_max = 45000, |
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.tCEH_min = 20000, |
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.tCH_min = 10000, |
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.tCHZ_max = 50000, |
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.tCLH_min = 10000, |
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.tCLR_min = 10000, |
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.tCLS_min = 25000, |
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.tCOH_min = 15000, |
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.tCS_min = 35000, |
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.tDH_min = 10000, |
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.tDS_min = 20000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 0, |
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.tITC_max = 1000000, |
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.tRC_min = 50000, |
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.tREA_max = 30000, |
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.tREH_min = 15000, |
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.tRHOH_min = 15000, |
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.tRHW_min = 100000, |
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.tRHZ_max = 100000, |
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.tRLOH_min = 0, |
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.tRP_min = 25000, |
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.tRR_min = 20000, |
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.tRST_max = 500000000, |
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.tWB_max = 100000, |
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.tWC_min = 45000, |
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.tWH_min = 15000, |
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.tWHR_min = 80000, |
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.tWP_min = 25000, |
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.tWW_min = 100000, |
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}, |
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/* Mode 2 */ |
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{ |
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.tADL_min = 100000, |
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.tALH_min = 10000, |
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.tALS_min = 15000, |
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.tAR_min = 10000, |
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.tCEA_max = 30000, |
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.tCEH_min = 20000, |
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.tCH_min = 10000, |
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.tCHZ_max = 50000, |
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.tCLH_min = 10000, |
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.tCLR_min = 10000, |
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.tCLS_min = 15000, |
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.tCOH_min = 15000, |
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.tCS_min = 25000, |
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.tDH_min = 5000, |
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.tDS_min = 15000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 0, |
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.tITC_max = 1000000, |
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.tRC_min = 35000, |
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.tREA_max = 25000, |
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.tREH_min = 15000, |
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.tRHOH_min = 15000, |
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.tRHW_min = 100000, |
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.tRHZ_max = 100000, |
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.tRLOH_min = 0, |
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.tRR_min = 20000, |
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.tRST_max = 500000000, |
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.tWB_max = 100000, |
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.tRP_min = 17000, |
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.tWC_min = 35000, |
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.tWH_min = 15000, |
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.tWHR_min = 80000, |
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.tWP_min = 17000, |
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.tWW_min = 100000, |
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}, |
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/* Mode 3 */ |
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{ |
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.tADL_min = 100000, |
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.tALH_min = 5000, |
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.tALS_min = 10000, |
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.tAR_min = 10000, |
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.tCEA_max = 25000, |
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.tCEH_min = 20000, |
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.tCH_min = 5000, |
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.tCHZ_max = 50000, |
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.tCLH_min = 5000, |
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.tCLR_min = 10000, |
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.tCLS_min = 10000, |
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.tCOH_min = 15000, |
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.tCS_min = 25000, |
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.tDH_min = 5000, |
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.tDS_min = 10000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 0, |
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.tITC_max = 1000000, |
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.tRC_min = 30000, |
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.tREA_max = 20000, |
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.tREH_min = 10000, |
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.tRHOH_min = 15000, |
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.tRHW_min = 100000, |
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.tRHZ_max = 100000, |
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.tRLOH_min = 0, |
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.tRP_min = 15000, |
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.tRR_min = 20000, |
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.tRST_max = 500000000, |
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.tWB_max = 100000, |
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.tWC_min = 30000, |
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.tWH_min = 10000, |
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.tWHR_min = 80000, |
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.tWP_min = 15000, |
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.tWW_min = 100000, |
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}, |
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/* Mode 4 */ |
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{ |
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.tADL_min = 70000, |
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.tALH_min = 5000, |
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.tALS_min = 10000, |
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.tAR_min = 10000, |
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.tCEA_max = 25000, |
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.tCEH_min = 20000, |
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.tCH_min = 5000, |
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.tCHZ_max = 30000, |
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.tCLH_min = 5000, |
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.tCLR_min = 10000, |
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.tCLS_min = 10000, |
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.tCOH_min = 15000, |
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.tCS_min = 20000, |
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.tDH_min = 5000, |
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.tDS_min = 10000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 0, |
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.tITC_max = 1000000, |
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.tRC_min = 25000, |
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.tREA_max = 20000, |
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.tREH_min = 10000, |
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.tRHOH_min = 15000, |
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.tRHW_min = 100000, |
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.tRHZ_max = 100000, |
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.tRLOH_min = 5000, |
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.tRP_min = 12000, |
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.tRR_min = 20000, |
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.tRST_max = 500000000, |
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.tWB_max = 100000, |
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.tWC_min = 25000, |
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.tWH_min = 10000, |
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.tWHR_min = 80000, |
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.tWP_min = 12000, |
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.tWW_min = 100000, |
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}, |
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/* Mode 5 */ |
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{ |
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.tADL_min = 70000, |
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.tALH_min = 5000, |
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.tALS_min = 10000, |
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.tAR_min = 10000, |
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.tCEA_max = 25000, |
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.tCEH_min = 20000, |
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.tCH_min = 5000, |
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.tCHZ_max = 30000, |
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.tCLH_min = 5000, |
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.tCLR_min = 10000, |
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.tCLS_min = 10000, |
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.tCOH_min = 15000, |
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.tCS_min = 15000, |
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.tDH_min = 5000, |
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.tDS_min = 7000, |
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.tFEAT_max = 1000000, |
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.tIR_min = 0, |
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.tITC_max = 1000000, |
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.tRC_min = 20000, |
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.tREA_max = 16000, |
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.tREH_min = 7000, |
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.tRHOH_min = 15000, |
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.tRHW_min = 100000, |
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.tRHZ_max = 100000, |
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.tRLOH_min = 5000, |
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.tRP_min = 10000, |
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.tRR_min = 20000, |
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.tRST_max = 500000000, |
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.tWB_max = 100000, |
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.tWC_min = 20000, |
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.tWH_min = 7000, |
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.tWHR_min = 80000, |
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.tWP_min = 10000, |
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.tWW_min = 100000, |
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}, |
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}; |
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|
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/**
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* onfi_async_timing_mode_to_sdr_timings - [NAND Interface] Retrieve NAND |
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* timings according to the given ONFI timing mode |
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* @mode: ONFI timing mode |
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*/ |
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const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode) |
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{ |
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if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings)) |
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return ERR_PTR(-EINVAL); |
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return &onfi_sdr_timings[mode]; |
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} |
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EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings); |
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#ifndef __ASM_ARCH_PXA3XX_NAND_H |
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#define __ASM_ARCH_PXA3XX_NAND_H |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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struct pxa3xx_nand_timing { |
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unsigned int tCH; /* Enable signal hold time */ |
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unsigned int tCS; /* Enable signal setup time */ |
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unsigned int tWH; /* ND_nWE high duration */ |
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unsigned int tWP; /* ND_nWE pulse time */ |
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unsigned int tRH; /* ND_nRE high duration */ |
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unsigned int tRP; /* ND_nRE pulse width */ |
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unsigned int tR; /* ND_nWE high to ND_nRE low for read */ |
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unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ |
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unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ |
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}; |
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struct pxa3xx_nand_flash { |
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uint32_t chip_id; |
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unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */ |
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unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */ |
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struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ |
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}; |
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/*
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* Current pxa3xx_nand controller has two chip select which |
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* both be workable. |
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* |
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* Notice should be taken that: |
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* When you want to use this feature, you should not enable the |
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* keep configuration feature, for two chip select could be |
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* attached with different nand chip. The different page size |
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* and timing requirement make the keep configuration impossible. |
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*/ |
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/* The max num of chip select current support */ |
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#define NUM_CHIP_SELECT (2) |
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struct pxa3xx_nand_platform_data { |
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/* the data flash bus is shared between the Static Memory
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* Controller and the Data Flash Controller, the arbiter |
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* controls the ownership of the bus |
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*/ |
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int enable_arbiter; |
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/* allow platform code to keep OBM/bootloader defined NFC config */ |
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int keep_config; |
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/* indicate how many chip selects will be used */ |
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int num_cs; |
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|
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/* use an flash-based bad block table */ |
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bool flash_bbt; |
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/* requested ECC strength and ECC step size */ |
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int ecc_strength, ecc_step_size; |
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const struct mtd_partition *parts[NUM_CHIP_SELECT]; |
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unsigned int nr_parts[NUM_CHIP_SELECT]; |
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const struct pxa3xx_nand_flash *flash; |
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size_t num_flash; |
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}; |
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#endif /* __ASM_ARCH_PXA3XX_NAND_H */ |
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