This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
Masahiro Yamada
10 years ago
committed by
Tom Rini
parent
5344cc1a82
commit
ad734f7dc2
@ -1,9 +0,0 @@ |
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if TARGET_TOTAL5200 |
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config SYS_BOARD |
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default "total5200" |
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config SYS_CONFIG_NAME |
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default "Total5200" |
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endif |
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@ -1,9 +0,0 @@ |
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TOTAL5200 BOARD |
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#M: - |
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S: Maintained |
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F: board/total5200/ |
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F: include/configs/Total5200.h |
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F: configs/Total5200_defconfig |
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F: configs/Total5200_lowboot_defconfig |
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F: configs/Total5200_Rev2_defconfig |
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F: configs/Total5200_Rev2_lowboot_defconfig |
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := total5200.o sdram.o
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@ -1,14 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#define SDRAM_DDR 0 /* is SDR */ |
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|
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/* Settings for XLB = 132 MHz */ |
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#define SDRAM_MODE 0x00CD0000 |
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#define SDRAM_CONTROL 0x504F0000 |
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#define SDRAM_CONFIG1 0xD2322800 |
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#define SDRAM_CONFIG2 0x8AD70000 |
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@ -1,19 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/*
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* Micron MT48LC32M16A2-75 is compatible to: |
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* - Infineon HYB39S512160AT-75 |
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*/ |
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#define SDRAM_DDR 0 /* is SDR */ |
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/* Settings for XLB = 132 MHz */ |
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#define SDRAM_MODE 0x00CD0000 |
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#define SDRAM_CONTROL 0x514F0000 |
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#define SDRAM_CONFIG1 0xD2322800 |
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#define SDRAM_CONFIG2 0x8AD70000 |
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@ -1,159 +0,0 @@ |
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/*
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* (C) Copyright 2003-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include "sdram.h" |
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#ifndef CONFIG_SYS_RAMBOOT |
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static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) |
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{ |
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long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
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|
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/* unlock mode register */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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|
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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if (sdram_conf->ddr) { |
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/* set mode register: extended mode */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode; |
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__asm__ volatile ("sync"); |
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|
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/* set mode register: reset DLL */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000; |
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__asm__ volatile ("sync"); |
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} |
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|
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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/* auto refresh */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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/* set mode register */ |
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*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode; |
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__asm__ volatile ("sync"); |
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/* normal operation */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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} |
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#endif |
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use |
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
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* is something else than 0x00000000. |
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*/ |
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long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) |
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{ |
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ulong dramsize = 0; |
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ulong dramsize2 = 0; |
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#ifndef CONFIG_SYS_RAMBOOT |
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ulong test1, test2; |
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/* setup SDRAM chip selects */ |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ |
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__asm__ volatile ("sync"); |
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/* setup config registers */ |
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; |
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; |
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__asm__ volatile ("sync"); |
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if (sdram_conf->ddr) { |
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/* set tap delay */ |
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*(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay; |
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__asm__ volatile ("sync"); |
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} |
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/* find RAM size using SDRAM CS0 only */ |
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mpc5xxx_sdram_start(sdram_conf, 0); |
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
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mpc5xxx_sdram_start(sdram_conf, 1); |
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
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if (test1 > test2) { |
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mpc5xxx_sdram_start(sdram_conf, 0); |
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dramsize = test1; |
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} else { |
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dramsize = test2; |
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} |
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/* memory smaller than 1MB is impossible */ |
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if (dramsize < (1 << 20)) { |
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dramsize = 0; |
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} |
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/* set SDRAM CS0 size according to the amount of RAM found */ |
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if (dramsize > 0) { |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
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} else { |
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
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} |
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/* let SDRAM CS1 start right after CS0 */ |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
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/* find RAM size using SDRAM CS1 only */ |
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mpc5xxx_sdram_start(sdram_conf, 0); |
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test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); |
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mpc5xxx_sdram_start(sdram_conf, 1); |
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test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); |
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if (test1 > test2) { |
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mpc5xxx_sdram_start(sdram_conf, 0); |
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dramsize2 = test1; |
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} else { |
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dramsize2 = test2; |
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} |
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/* memory smaller than 1MB is impossible */ |
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if (dramsize2 < (1 << 20)) { |
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dramsize2 = 0; |
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} |
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/* set SDRAM CS1 size according to the amount of RAM found */ |
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if (dramsize2 > 0) { |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
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| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
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} else { |
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
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} |
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#else /* CONFIG_SYS_RAMBOOT */ |
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/* retrieve size of memory connected to SDRAM CS0 */ |
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
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if (dramsize >= 0x13) { |
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dramsize = (1 << (dramsize - 0x13)) << 20; |
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} else { |
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dramsize = 0; |
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} |
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/* retrieve size of memory connected to SDRAM CS1 */ |
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
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if (dramsize2 >= 0x13) { |
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
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} else { |
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dramsize2 = 0; |
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} |
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#endif /* CONFIG_SYS_RAMBOOT */ |
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return dramsize + dramsize2; |
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} |
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@ -1,18 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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typedef struct { |
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ulong ddr; |
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ulong mode; |
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ulong emode; |
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ulong control; |
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ulong config1; |
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ulong config2; |
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ulong tapdelay; |
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} sdram_conf_t; |
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long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); |
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@ -1,276 +0,0 @@ |
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/*
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* (C) Copyright 2003-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include <pci.h> |
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#include <netdev.h> |
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#include "sdram.h" |
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#if CONFIG_TOTAL5200_REV==2 |
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#include "mt48lc32m16a2-75.h" |
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#else |
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#include "mt48lc16m16a2-75.h" |
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#endif |
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phys_size_t initdram (int board_type) |
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{ |
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sdram_conf_t sdram_conf; |
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sdram_conf.ddr = SDRAM_DDR; |
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sdram_conf.mode = SDRAM_MODE; |
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sdram_conf.emode = 0; |
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sdram_conf.control = SDRAM_CONTROL; |
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sdram_conf.config1 = SDRAM_CONFIG1; |
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sdram_conf.config2 = SDRAM_CONFIG2; |
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sdram_conf.tapdelay = 0; |
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return mpc5xxx_sdram_init (&sdram_conf); |
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} |
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int checkboard (void) |
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{ |
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#if CONFIG_TOTAL5200_REV==2 |
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puts ("Board: Total5200 Rev.2 "); |
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#else |
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puts ("Board: Total5200 "); |
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#endif |
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/*
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* Retrieve FPGA Revision. |
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*/ |
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printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400)); |
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/*
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* Take all peripherals in power-up mode. |
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*/ |
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#if CONFIG_TOTAL5200_REV==2 |
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*(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70; |
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#else |
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*(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70; |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_PCI |
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static struct pci_controller hose; |
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extern void pci_mpc5xxx_init(struct pci_controller *); |
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void pci_init_board(void) |
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{ |
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pci_mpc5xxx_init(&hose); |
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} |
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#endif |
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
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/* IRDA_1 aka PSC6_3 (pin C13) */ |
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#define GPIO_IRDA_1 0x20000000UL |
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void init_ide_reset (void) |
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{ |
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debug ("init_ide_reset\n"); |
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/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ |
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*(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; |
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*(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; |
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} |
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void ide_set_reset (int idereset) |
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{ |
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debug ("ide_reset(%d)\n", idereset); |
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if (idereset) { |
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*(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1; |
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} else { |
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*(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; |
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} |
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} |
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#endif |
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#ifdef CONFIG_VIDEO_SED13806 |
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#include <sed13806.h> |
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#define DISPLAY_WIDTH 640 |
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#define DISPLAY_HEIGHT 480 |
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#ifdef CONFIG_VIDEO_SED13806_8BPP |
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#error CONFIG_VIDEO_SED13806_8BPP not supported. |
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#endif /* CONFIG_VIDEO_SED13806_8BPP */ |
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#ifdef CONFIG_VIDEO_SED13806_16BPP |
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static const S1D_REGS init_regs [] = |
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{ |
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{0x0001,0x00}, /* Miscellaneous Register */ |
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{0x01FC,0x00}, /* Display Mode Register */ |
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{0x0004,0x00}, /* General IO Pins Configuration Register 0 */ |
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{0x0005,0x00}, /* General IO Pins Configuration Register 1 */ |
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{0x0008,0x00}, /* General IO Pins Control Register 0 */ |
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{0x0009,0x00}, /* General IO Pins Control Register 1 */ |
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{0x0010,0x02}, /* Memory Clock Configuration Register */ |
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{0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ |
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{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ |
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{0x001C,0x02}, /* MediaPlug Clock Configuration Register */ |
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{0x001E,0x01}, /* CPU To Memory Wait State Select Register */ |
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{0x0021,0x03}, /* DRAM Refresh Rate Register */ |
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{0x002A,0x00}, /* DRAM Timings Control Register 0 */ |
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{0x002B,0x01}, /* DRAM Timings Control Register 1 */ |
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{0x0020,0x80}, /* Memory Configuration Register */ |
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{0x0030,0x25}, /* Panel Type Register */ |
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{0x0031,0x00}, /* MOD Rate Register */ |
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{0x0032,0x4F}, /* LCD Horizontal Display Width Register */ |
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{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ |
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{0x0035,0x01}, /* TFT FPLINE Start Position Register */ |
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{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ |
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{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ |
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{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ |
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{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ |
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{0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ |
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{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ |
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{0x0040,0x05}, /* LCD Display Mode Register */ |
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{0x0041,0x00}, /* LCD Miscellaneous Register */ |
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{0x0042,0x00}, /* LCD Display Start Address Register 0 */ |
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{0x0043,0x00}, /* LCD Display Start Address Register 1 */ |
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{0x0044,0x00}, /* LCD Display Start Address Register 2 */ |
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{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ |
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{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ |
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{0x0048,0x00}, /* LCD Pixel Panning Register */ |
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{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ |
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{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ |
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{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ |
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{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ |
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{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ |
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{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ |
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{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ |
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{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ |
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{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ |
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{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ |
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{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ |
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{0x005B,0x10}, /* TV Output Control Register */ |
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{0x0060,0x05}, /* CRT/TV Display Mode Register */ |
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{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ |
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{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ |
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{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ |
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{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ |
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{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ |
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{0x0068,0x00}, /* CRT/TV Pixel Panning Register */ |
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{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ |
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{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ |
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{0x0070,0x00}, /* LCD Ink/Cursor Control Register */ |
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{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ |
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{0x0072,0x00}, /* LCD Cursor X Position Register 0 */ |
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{0x0073,0x00}, /* LCD Cursor X Position Register 1 */ |
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{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ |
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{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ |
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{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ |
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{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ |
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{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ |
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{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ |
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{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ |
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{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ |
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{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ |
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{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ |
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{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ |
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{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ |
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{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ |
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{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ |
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{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ |
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{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ |
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{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ |
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{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ |
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{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ |
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{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ |
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{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ |
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{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ |
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{0x0100,0x00}, /* BitBlt Control Register 0 */ |
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{0x0101,0x00}, /* BitBlt Control Register 1 */ |
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{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ |
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{0x0103,0x00}, /* BitBlt Operation Register */ |
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{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ |
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{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ |
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{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ |
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{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ |
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{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ |
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{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ |
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{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ |
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{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ |
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{0x0110,0x00}, /* BitBlt Width Register 0 */ |
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{0x0111,0x00}, /* BitBlt Width Register 1 */ |
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */ |
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */ |
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */ |
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */ |
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ |
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ |
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */ |
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */ |
||||
{0x01E4,0x00}, /* Look-Up Table Data Register */ |
||||
{0x01F0,0x00}, /* Power Save Configuration Register */ |
||||
{0x01F1,0x00}, /* Power Save Status Register */ |
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ |
||||
{0x01FC,0x01}, /* Display Mode Register */ |
||||
{0, 0} |
||||
}; |
||||
#endif /* CONFIG_VIDEO_SED13806_16BPP */ |
||||
|
||||
#ifdef CONFIG_CONSOLE_EXTRA_INFO |
||||
/* Return text to be printed besides the logo. */ |
||||
void video_get_info_str (int line_number, char *info) |
||||
{ |
||||
if (line_number == 1) { |
||||
#if CONFIG_TOTAL5200_REV==1 |
||||
strcpy (info, " Total5200"); |
||||
#elif CONFIG_TOTAL5200_REV==2 |
||||
strcpy (info, " Total5200 Rev.2"); |
||||
#else |
||||
#error CONFIG_TOTAL5200_REV must be 1 or 2. |
||||
#endif |
||||
} else { |
||||
info [0] = '\0'; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
/* Returns SED13806 base address. First thing called in the driver. */ |
||||
unsigned int board_video_init (void) |
||||
{ |
||||
return CONFIG_SYS_LCD_BASE; |
||||
} |
||||
|
||||
/* Called after initializing the SED13806 and before clearing the screen. */ |
||||
void board_validate_screen (unsigned int base) |
||||
{ |
||||
} |
||||
|
||||
/* Return a pointer to the initialization sequence. */ |
||||
const S1D_REGS *board_get_regs (void) |
||||
{ |
||||
return init_regs; |
||||
} |
||||
|
||||
int board_get_width (void) |
||||
{ |
||||
return DISPLAY_WIDTH; |
||||
} |
||||
|
||||
int board_get_height (void) |
||||
{ |
||||
return DISPLAY_HEIGHT; |
||||
} |
||||
|
||||
#endif /* CONFIG_VIDEO_SED13806 */ |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
cpu_eth_init(bis); /* Built in FEC comes first */ |
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC5xxx=y |
||||
CONFIG_TARGET_TOTAL5200=y |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC5xxx=y |
||||
CONFIG_TARGET_TOTAL5200=y |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC5xxx=y |
||||
CONFIG_TARGET_TOTAL5200=y |
||||
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC5xxx=y |
||||
CONFIG_TARGET_TOTAL5200=y |
||||
@ -1,386 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Check valid setting of revision define. |
||||
* Total5100 and Total5200 Rev.1 are identical except for the processor. |
||||
*/ |
||||
#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) |
||||
#error CONFIG_TOTAL5200_REV must be 1 or 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ |
||||
#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ |
||||
|
||||
/*
|
||||
* Valid values for CONFIG_SYS_TEXT_BASE are: |
||||
* 0xFFF00000 boot high (standard configuration) |
||||
* 0xFE000000 boot low |
||||
* 0x00100000 boot from RAM (for testing only) |
||||
*/ |
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ |
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* Video console |
||||
*/ |
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_VIDEO_SED13806 |
||||
#define CONFIG_VIDEO_SED13806_16BPP |
||||
|
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VIDEO_LOGO |
||||
/* #define CONFIG_VIDEO_BMP_LOGO */ |
||||
#define CONFIG_CONSOLE_EXTRA_INFO |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_VIDEO_SW_CURSOR |
||||
#define CONFIG_SPLASH_SCREEN |
||||
|
||||
|
||||
/*
|
||||
* PCI Mapping: |
||||
* 0x40000000 - 0x4fffffff - PCI Memory |
||||
* 0x50000000 - 0x50ffffff - PCI IO Space |
||||
*/ |
||||
#define CONFIG_PCI 1 |
||||
#define CONFIG_PCI_PNP 1 |
||||
#define CONFIG_PCI_SCAN_SHOW 1 |
||||
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0x01000000 |
||||
|
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_EEPRO100 1 |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
#define CONFIG_NS8382X 1 |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PCI |
||||
|
||||
#define CONFIG_CMD_BMP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_USB |
||||
|
||||
|
||||
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ |
||||
# define CONFIG_SYS_LOWBOOT 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT \ |
||||
"setenv stdout serial;setenv stderr serial;" \
|
||||
"echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/MPC5200/uImage\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
||||
|
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 |
||||
|
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#if CONFIG_TOTAL5200_REV==2 |
||||
# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ |
||||
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } |
||||
#else |
||||
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
||||
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
||||
#endif |
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#if CONFIG_TOTAL5200_REV==1 |
||||
# define CONFIG_SYS_FLASH_BASE 0xFE000000 |
||||
# define CONFIG_SYS_FLASH_SIZE 0x02000000 |
||||
#elif CONFIG_TOTAL5200_REV==2 |
||||
# define CONFIG_SYS_FLASH_BASE 0xFA000000 |
||||
# define CONFIG_SYS_FLASH_SIZE 0x06000000 |
||||
#endif /* CONFIG_TOTAL5200_REV */ |
||||
|
||||
#if defined(CONFIG_SYS_LOWBOOT) |
||||
# define CONFIG_ENV_ADDR 0xFE040000 |
||||
#else /* CONFIG_SYS_LOWBOOT */ |
||||
# define CONFIG_ENV_ADDR 0xFFF40000 |
||||
#endif /* CONFIG_SYS_LOWBOOT */ |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SIZE 0x40000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
||||
#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ |
||||
#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ |
||||
#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ |
||||
#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ |
||||
|
||||
/* Use SRAM until RAM will be available */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
||||
# define CONFIG_SYS_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
#define CONFIG_MPC5xxx_FEC_SEVENWIRE |
||||
/* dummy, 7-wire FEC does not have phy address */ |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
* |
||||
* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 |
||||
* Reserved 0 |
||||
* ALTs: CAN1/2 on PSC2, SPI on PSC3 00 |
||||
* CS7: Interrupt GPIO on PSC3_5 0 |
||||
* CS8: Interrupt GPIO on PSC3_4 0 |
||||
* ATA: reset default, changed in ATA driver 00 |
||||
* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 |
||||
* IRDA: reset default, changed in IrDA driver 000 |
||||
* ETHER: reset default, changed in Ethernet driver 0000 |
||||
* PCI_DIS: reset default, changed in PCI driver 0 |
||||
* USB_SE: reset default, changed in USB driver 0 |
||||
* USB: reset default, changed in USB driver 00 |
||||
* PSC3: SPI and UART functionality without CD 1100 |
||||
* Reserved 0 |
||||
* PSC2: CAN1/2 001 |
||||
* Reserved 0 |
||||
* PSC1: reset default, changed in AC'97 driver 000 |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE |
||||
|
||||
#if CONFIG_TOTAL5200_REV==1 |
||||
# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
||||
# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ |
||||
# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
||||
# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
||||
# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ |
||||
#else |
||||
# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) |
||||
# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ |
||||
# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
||||
# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) |
||||
# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ |
||||
# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
||||
# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE |
||||
# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ |
||||
# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE |
||||
#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ |
||||
#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ |
||||
|
||||
#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE |
||||
#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ |
||||
#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ |
||||
|
||||
#if CONFIG_TOTAL5200_REV==1 |
||||
# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
||||
# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ |
||||
# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ |
||||
#else |
||||
# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE |
||||
# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ |
||||
# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000 |
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_USB_CLOCK 0x0001BBBB |
||||
#define CONFIG_USB_CONFIG 0x00001000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */ |
||||
#define CONFIG_IDE_PREINIT |
||||
|
||||
#define CONFIG_SYS_ATA_CS_ON_I2C2 |
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
||||
|
||||
/* Interval between registers */ |
||||
#define CONFIG_SYS_ATA_STRIDE 4 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue