Tom Rini
6 years ago
commit
ad8c9f6146
@ -1,4 +1,4 @@ |
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# SPDX-License-Identifier: GPL-2.0
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spinand-objs := core.o macronix.o micron.o winbond.o
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spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o
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obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
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@ -0,0 +1,135 @@ |
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de> |
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* |
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* Derived from drivers/mtd/nand/spi/micron.c |
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* Copyright (c) 2016-2017 Micron Technology, Inc. |
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*/ |
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#ifndef __UBOOT__ |
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#include <linux/device.h> |
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#include <linux/kernel.h> |
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#endif |
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#include <linux/mtd/spinand.h> |
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#define SPINAND_MFR_GIGADEVICE 0xc8 |
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#define GIGADEVICE_STATUS_ECC_MASK GENMASK(5, 4) |
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#define GIGADEVICE_STATUS_ECC_NO_BITFLIPS (0 << 4) |
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#define GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS (1 << 4) |
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#define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4) |
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static SPINAND_OP_VARIANTS(read_cache_variants, |
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
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static SPINAND_OP_VARIANTS(write_cache_variants, |
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
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SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
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static SPINAND_OP_VARIANTS(update_cache_variants, |
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), |
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SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
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static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *region) |
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{ |
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if (section) |
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return -ERANGE; |
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region->offset = 64; |
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region->length = 64; |
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return 0; |
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} |
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static int gd5f1gq4u_ooblayout_free(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *region) |
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{ |
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if (section) |
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return -ERANGE; |
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/* Reserve 2 bytes for the BBM. */ |
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region->offset = 2; |
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region->length = 62; |
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return 0; |
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} |
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static const struct mtd_ooblayout_ops gd5f1gq4u_ooblayout = { |
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.ecc = gd5f1gq4u_ooblayout_ecc, |
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.free = gd5f1gq4u_ooblayout_free, |
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}; |
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static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand, |
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u8 status) |
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{ |
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if (status) |
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debug("%s (%d): status=%02x\n", __func__, __LINE__, status); |
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switch (status & GIGADEVICE_STATUS_ECC_MASK) { |
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case STATUS_ECC_NO_BITFLIPS: |
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return 0; |
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case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS: |
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return 7; |
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case GIGADEVICE_STATUS_ECC_8_BITFLIPS: |
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return 8; |
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case STATUS_ECC_UNCOR_ERROR: |
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return -EBADMSG; |
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default: |
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break; |
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} |
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return -EINVAL; |
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} |
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static const struct spinand_info gigadevice_spinand_table[] = { |
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SPINAND_INFO("GD5F1GQ4UC", 0xd1, |
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), |
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NAND_ECCREQ(8, 2048), |
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
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&write_cache_variants, |
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&update_cache_variants), |
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0, |
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SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, |
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gd5f1gq4u_ecc_get_status)), |
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}; |
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static int gigadevice_spinand_detect(struct spinand_device *spinand) |
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{ |
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u8 *id = spinand->id.data; |
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int ret; |
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/*
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* Gigadevice SPI NAND read ID need a dummy byte, |
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* so the first byte in raw_id is dummy. |
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*/ |
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if (id[1] != SPINAND_MFR_GIGADEVICE) |
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return 0; |
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ret = spinand_match_and_init(spinand, gigadevice_spinand_table, |
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ARRAY_SIZE(gigadevice_spinand_table), |
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id[2]); |
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if (ret) |
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return ret; |
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return 1; |
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} |
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static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |
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.detect = gigadevice_spinand_detect, |
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}; |
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const struct spinand_manufacturer gigadevice_spinand_manufacturer = { |
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.id = SPINAND_MFR_GIGADEVICE, |
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.name = "GigaDevice", |
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.ops = &gigadevice_spinand_manuf_ops, |
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}; |
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@ -0,0 +1,312 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de> |
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* |
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* Derived from the Linux driver version drivers/spi/spi-mt7621.c |
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* Copyright (C) 2011 Sergiy <piratfm@gmail.com> |
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name> |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <spi.h> |
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#include <wait_bit.h> |
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#include <linux/io.h> |
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#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ |
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/* Enough for SPI NAND page read / write with page size 2048 bytes */ |
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#define SPI_MSG_SIZE_OVERALL (2048 + 16) |
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#define MT7621_SPI_TRANS 0x00 |
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#define MT7621_SPI_TRANS_START BIT(8) |
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#define MT7621_SPI_TRANS_BUSY BIT(16) |
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#define MT7621_SPI_OPCODE 0x04 |
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#define MT7621_SPI_DATA0 0x08 |
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#define MT7621_SPI_DATA4 0x18 |
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#define MT7621_SPI_MASTER 0x28 |
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#define MT7621_SPI_MOREBUF 0x2c |
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#define MT7621_SPI_POLAR 0x38 |
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#define MT7621_LSB_FIRST BIT(3) |
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#define MT7621_CPOL BIT(4) |
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#define MT7621_CPHA BIT(5) |
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#define MASTER_MORE_BUFMODE BIT(2) |
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#define MASTER_RS_CLK_SEL GENMASK(27, 16) |
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#define MASTER_RS_CLK_SEL_SHIFT 16 |
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#define MASTER_RS_SLAVE_SEL GENMASK(31, 29) |
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struct mt7621_spi { |
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void __iomem *base; |
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unsigned int sys_freq; |
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u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; |
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int tx_len; |
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}; |
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static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) |
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{ |
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setbits_le32(rs->base + MT7621_SPI_MASTER, |
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MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); |
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} |
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static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) |
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{ |
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u32 val = 0; |
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debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); |
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if (enable) |
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val = BIT(cs); |
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iowrite32(val, rs->base + MT7621_SPI_POLAR); |
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} |
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static int mt7621_spi_set_mode(struct udevice *bus, uint mode) |
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{ |
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struct mt7621_spi *rs = dev_get_priv(bus); |
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u32 reg; |
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debug("%s: mode=0x%08x\n", __func__, mode); |
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reg = ioread32(rs->base + MT7621_SPI_MASTER); |
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reg &= ~MT7621_LSB_FIRST; |
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if (mode & SPI_LSB_FIRST) |
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reg |= MT7621_LSB_FIRST; |
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reg &= ~(MT7621_CPHA | MT7621_CPOL); |
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switch (mode & (SPI_CPOL | SPI_CPHA)) { |
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case SPI_MODE_0: |
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break; |
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case SPI_MODE_1: |
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reg |= MT7621_CPHA; |
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break; |
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case SPI_MODE_2: |
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reg |= MT7621_CPOL; |
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break; |
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case SPI_MODE_3: |
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reg |= MT7621_CPOL | MT7621_CPHA; |
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break; |
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} |
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iowrite32(reg, rs->base + MT7621_SPI_MASTER); |
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return 0; |
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} |
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static int mt7621_spi_set_speed(struct udevice *bus, uint speed) |
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{ |
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struct mt7621_spi *rs = dev_get_priv(bus); |
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u32 rate; |
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u32 reg; |
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debug("%s: speed=%d\n", __func__, speed); |
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rate = DIV_ROUND_UP(rs->sys_freq, speed); |
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debug("rate:%u\n", rate); |
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if (rate > 4097) |
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return -EINVAL; |
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if (rate < 2) |
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rate = 2; |
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reg = ioread32(rs->base + MT7621_SPI_MASTER); |
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reg &= ~MASTER_RS_CLK_SEL; |
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reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; |
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iowrite32(reg, rs->base + MT7621_SPI_MASTER); |
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return 0; |
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} |
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static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) |
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{ |
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int ret; |
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ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS, |
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MT7621_SPI_TRANS_BUSY, 0, 10, 0); |
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if (ret) |
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pr_err("Timeout in %s!\n", __func__); |
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return ret; |
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} |
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static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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const void *dout, void *din, unsigned long flags) |
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{ |
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struct udevice *bus = dev->parent; |
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struct mt7621_spi *rs = dev_get_priv(bus); |
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const u8 *tx_buf = dout; |
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u8 *ptr = (u8 *)dout; |
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u8 *rx_buf = din; |
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int total_size = bitlen >> 3; |
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int chunk_size; |
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int rx_len = 0; |
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u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; |
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u32 val; |
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int i; |
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debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, |
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total_size, flags); |
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/*
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* This driver only supports half-duplex, so complain and bail out |
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* upon full-duplex messages |
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*/ |
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if (dout && din) { |
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printf("Only half-duplex SPI transfer supported\n"); |
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return -EIO; |
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} |
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if (dout) { |
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debug("TX-DATA: "); |
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for (i = 0; i < total_size; i++) |
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debug("%02x ", *ptr++); |
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debug("\n"); |
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} |
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mt7621_spi_wait_till_ready(rs); |
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/*
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* Set CS active upon start of SPI message. This message can |
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* be split upon multiple calls to this xfer function |
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*/ |
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if (flags & SPI_XFER_BEGIN) |
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mt7621_spi_set_cs(rs, spi_chip_select(dev), 1); |
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while (total_size > 0) { |
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/* Don't exceed the max xfer size */ |
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chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); |
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/*
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* We might have some TX data buffered from the last xfer |
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* message. Make sure, that this does not exceed the max |
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* xfer size |
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*/ |
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if (rs->tx_len > 4) |
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chunk_size -= rs->tx_len; |
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if (din) |
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rx_len = chunk_size; |
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if (tx_buf) { |
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/* Check if this message does not exceed the buffer */ |
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if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { |
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printf("TX message size too big (%d)\n", |
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chunk_size + rs->tx_len); |
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return -EMSGSIZE; |
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} |
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/*
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* Write all TX data into internal buffer to collect |
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* all TX messages into one buffer (might be split into |
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* multiple calls to this function) |
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*/ |
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for (i = 0; i < chunk_size; i++, rs->tx_len++) { |
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rs->data[rs->tx_len / 4] |= |
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tx_buf[i] << (8 * (rs->tx_len & 3)); |
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} |
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} |
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if (flags & SPI_XFER_END) { |
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/* Write TX data into controller */ |
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if (rs->tx_len) { |
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rs->data[0] = swab32(rs->data[0]); |
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if (rs->tx_len < 4) |
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rs->data[0] >>= (4 - rs->tx_len) * 8; |
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for (i = 0; i < rs->tx_len; i += 4) { |
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iowrite32(rs->data[i / 4], rs->base + |
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MT7621_SPI_OPCODE + i); |
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} |
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} |
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/* Write length into controller */ |
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val = (min_t(int, rs->tx_len, 4) * 8) << 24; |
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if (rs->tx_len > 4) |
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val |= (rs->tx_len - 4) * 8; |
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val |= (rx_len * 8) << 12; |
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iowrite32(val, rs->base + MT7621_SPI_MOREBUF); |
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/* Start the xfer */ |
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setbits_le32(rs->base + MT7621_SPI_TRANS, |
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MT7621_SPI_TRANS_START); |
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/* Wait until xfer is finished on bus */ |
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mt7621_spi_wait_till_ready(rs); |
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/* Reset TX length and TX buffer for next xfer */ |
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rs->tx_len = 0; |
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memset(rs->data, 0, sizeof(rs->data)); |
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} |
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for (i = 0; i < rx_len; i += 4) |
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data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i); |
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if (rx_len) { |
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debug("RX-DATA: "); |
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for (i = 0; i < rx_len; i++) { |
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rx_buf[i] = data[i / 4] >> (8 * (i & 3)); |
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debug("%02x ", rx_buf[i]); |
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} |
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debug("\n"); |
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} |
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if (tx_buf) |
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tx_buf += chunk_size; |
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if (rx_buf) |
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rx_buf += chunk_size; |
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total_size -= chunk_size; |
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} |
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/* Wait until xfer is finished on bus and de-assert CS */ |
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mt7621_spi_wait_till_ready(rs); |
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if (flags & SPI_XFER_END) |
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mt7621_spi_set_cs(rs, spi_chip_select(dev), 0); |
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return 0; |
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} |
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static int mt7621_spi_probe(struct udevice *dev) |
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{ |
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struct mt7621_spi *rs = dev_get_priv(dev); |
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rs->base = dev_remap_addr(dev); |
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if (!rs->base) |
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return -EINVAL; |
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/*
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* Read input clock via DT for now. At some point this should be |
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* replaced by implementing a clock driver for this SoC and getting |
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* the SPI frequency via this clock driver. |
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*/ |
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rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); |
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if (!rs->sys_freq) { |
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printf("Please provide clock-frequency!\n"); |
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return -EINVAL; |
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} |
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mt7621_spi_reset(rs, 0); |
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return 0; |
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} |
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static const struct dm_spi_ops mt7621_spi_ops = { |
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.set_mode = mt7621_spi_set_mode, |
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.set_speed = mt7621_spi_set_speed, |
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.xfer = mt7621_spi_xfer, |
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/*
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* cs_info is not needed, since we require all chip selects to be |
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* in the device tree explicitly |
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*/ |
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}; |
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static const struct udevice_id mt7621_spi_ids[] = { |
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{ .compatible = "ralink,mt7621-spi" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(mt7621_spi) = { |
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.name = "mt7621_spi", |
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.id = UCLASS_SPI, |
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.of_match = mt7621_spi_ids, |
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.ops = &mt7621_spi_ops, |
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.priv_auto_alloc_size = sizeof(struct mt7621_spi), |
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.probe = mt7621_spi_probe, |
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}; |
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Reference in new issue