Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

imx: mx6q DDR3 init: Fix SDE_to_RST

Browse Source 
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
master
Benoît Thébaudeau 13 years ago committed by Stefano Babic
parent aa53149e11
commit ada02b8463
1 changed files with 1 additions and 1 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 2
      board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg

2
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
Unescape View File

@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A0E21
DATA 4 0x021b0030 0x005A1021
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027

Write Preview
Loading…
Cancel
Save