The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was released by Amazon back in 2011. It is using an OMAP4430 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>master
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@ -0,0 +1,12 @@ |
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if TARGET_KC1 |
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config SYS_BOARD |
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default "kc1" |
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config SYS_VENDOR |
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default "amazon" |
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config SYS_CONFIG_NAME |
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default "kc1" |
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endif |
@ -0,0 +1,6 @@ |
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KC1 BOARD |
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M: Paul Kocialkowski <contact@paulk.fr> |
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S: Maintained |
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F: board/amazon/kc1/ |
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F: include/configs/kc1.h |
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F: configs/kc1_defconfig |
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#
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# Amazon Kindle Fire (first generation) codename kc1 config
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#
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# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := kc1.o
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/*
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* Amazon Kindle Fire (first generation) codename kc1 config |
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* |
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* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/gpio.h> |
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#include <asm/emif.h> |
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#include <twl6030.h> |
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#include "kc1.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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const struct omap_sysinfo sysinfo = { |
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.board_string = "kc1" |
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}; |
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void set_muxconf_regs(void) |
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{ |
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do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array, |
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sizeof(core_padconf_array) / sizeof(struct pad_conf_entry)); |
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} |
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struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, |
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struct lpddr2_device_details *lpddr2_dev_details) |
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{ |
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if (cs == CS1) |
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return NULL; |
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*lpddr2_dev_details = elpida_2G_S4_details; |
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return lpddr2_dev_details; |
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} |
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void emif_get_device_timings(u32 emif_nr, |
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const struct lpddr2_device_timings **cs0_device_timings, |
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const struct lpddr2_device_timings **cs1_device_timings) |
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{ |
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*cs0_device_timings = &elpida_2G_S4_timings; |
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*cs1_device_timings = NULL; |
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} |
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int board_init(void) |
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{ |
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/* GPMC init */ |
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gpmc_init(); |
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/* MACH number */ |
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; |
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/* ATAGs location */ |
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gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100; |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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/* Serial number */ |
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omap_die_id_serial(); |
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return 0; |
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} |
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u32 get_board_rev(void) |
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{ |
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u32 value = 0; |
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gpio_request(KC1_GPIO_MBID0, "MBID0"); |
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gpio_request(KC1_GPIO_MBID1, "MBID1"); |
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gpio_request(KC1_GPIO_MBID2, "MBID2"); |
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gpio_request(KC1_GPIO_MBID3, "MBID3"); |
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gpio_direction_input(KC1_GPIO_MBID0); |
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gpio_direction_input(KC1_GPIO_MBID1); |
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gpio_direction_input(KC1_GPIO_MBID2); |
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gpio_direction_input(KC1_GPIO_MBID3); |
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value |= (gpio_get_value(KC1_GPIO_MBID0) << 0); |
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value |= (gpio_get_value(KC1_GPIO_MBID1) << 1); |
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value |= (gpio_get_value(KC1_GPIO_MBID2) << 2); |
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value |= (gpio_get_value(KC1_GPIO_MBID3) << 3); |
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return value; |
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} |
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void get_board_serial(struct tag_serialnr *serialnr) |
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{ |
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omap_die_id_get_board_serial(serialnr); |
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} |
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#ifndef CONFIG_SPL_BUILD |
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int board_mmc_init(bd_t *bis) |
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{ |
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return omap_mmc_init(1, 0, 0, -1, -1); |
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} |
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#endif |
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void board_mmc_power_init(void) |
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{ |
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twl6030_power_mmc_init(1); |
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} |
@ -0,0 +1,92 @@ |
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/*
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* Amazon Kindle Fire (first generation) codename kc1 config |
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* |
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* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _KC1_H_ |
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#define _KC1_H_ |
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#include <asm/arch/mux_omap4.h> |
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#define KC1_GPIO_MBID1 173 |
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#define KC1_GPIO_MBID0 174 |
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#define KC1_GPIO_MBID3 177 |
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#define KC1_GPIO_MBID2 178 |
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const struct pad_conf_entry core_padconf_array[] = { |
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/* GPMC */ |
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{ GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */ |
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{ GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */ |
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{ GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */ |
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{ GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */ |
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{ GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */ |
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{ GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */ |
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{ GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */ |
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{ GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */ |
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{ GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */ |
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{ GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */ |
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/* CAM */ |
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{ CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */ |
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/* HDQ */ |
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{ HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ |
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/* I2C1 */ |
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{ I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */ |
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{ I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */ |
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/* I2C2 */ |
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{ I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */ |
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{ I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */ |
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/* I2C3 */ |
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{ I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */ |
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{ I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */ |
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/* I2C4 */ |
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{ I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */ |
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{ I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */ |
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/* MCSPI1 */ |
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{ MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ |
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/* UART3 */ |
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{ UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */ |
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{ UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */ |
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/* SDMMC5 */ |
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{ SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */ |
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{ SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */ |
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{ SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */ |
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{ SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */ |
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{ SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */ |
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{ SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */ |
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/* MCSPI4 */ |
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{ MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */ |
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{ MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */ |
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{ MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */ |
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{ MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */ |
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/* UART4 */ |
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{ UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ |
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{ UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */ |
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/* UNIPRO */ |
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{ UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */ |
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{ UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */ |
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{ UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */ |
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{ UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */ |
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{ UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */ |
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{ UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */ |
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{ UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */ |
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{ UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */ |
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}; |
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#endif |
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CONFIG_ARM=y |
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CONFIG_OMAP44XX=y |
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CONFIG_TARGET_KC1=y |
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CONFIG_SPL=y |
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CONFIG_SYS_PROMPT="kc1 # " |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_FPGA is not set |
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CONFIG_CMD_GPIO=y |
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# CONFIG_CMD_SETEXPR is not set |
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# CONFIG_CMD_NFS is not set |
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CONFIG_SYS_NS16550=y |
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/*
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* Amazon Kindle Fire (first generation) codename kc1 config |
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* |
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* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/omap.h> |
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/*
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* Build |
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*/ |
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#define CONFIG_SYS_THUMB_BUILD |
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/*
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* CPU |
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*/ |
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#define CONFIG_SYS_L2_PL310 1 |
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#define CONFIG_SYS_PL310_BASE 0x48242000 |
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#define CONFIG_SYS_CACHELINE_SIZE 32 |
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/*
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* Platform |
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*/ |
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#define CONFIG_OMAP |
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#define CONFIG_OMAP4430 |
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#define CONFIG_OMAP_COMMON |
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/*
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* Board |
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*/ |
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#define CONFIG_MISC_INIT_R |
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/*
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* Clocks |
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*/ |
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#define CONFIG_SYS_TIMERBASE GPT2_BASE |
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#define CONFIG_SYS_PTV 2 |
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/*
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* DRAM |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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/*
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* Memory |
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*/ |
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#define CONFIG_SYS_TEXT_BASE 0x80100000 |
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 |
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#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) |
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/*
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* GPIO |
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*/ |
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#define CONFIG_OMAP_GPIO |
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/*
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* I2C |
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*/ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 |
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 |
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#define CONFIG_SYS_I2C_OMAP24XX |
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#define CONFIG_I2C_MULTI_BUS |
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#define CONFIG_CMD_I2C |
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/*
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* Flash |
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*/ |
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#define CONFIG_SYS_NO_FLASH |
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/*
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* MMC |
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*/ |
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#define CONFIG_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_OMAP_HSMMC |
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#define CONFIG_CMD_MMC |
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/*
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* Power |
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*/ |
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#define CONFIG_TWL6030_POWER |
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/*
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* Partitions |
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*/ |
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#define CONFIG_PARTITION_UUIDS |
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#define CONFIG_CMD_PART |
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/*
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* SPL |
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*/ |
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#define CONFIG_SPL_FRAMEWORK |
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#define CONFIG_SPL_TEXT_BASE 0x40300000 |
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#define CONFIG_SPL_MAX_SIZE (48 * 1024) |
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000 |
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#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) |
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 |
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#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) |
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
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#define CONFIG_SPL_BOARD_INIT |
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#define CONFIG_SPL_LIBGENERIC_SUPPORT |
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#define CONFIG_SPL_LIBCOMMON_SUPPORT |
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#define CONFIG_SPL_LIBDISK_SUPPORT |
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#define CONFIG_SPL_SERIAL_SUPPORT |
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#define CONFIG_SPL_POWER_SUPPORT |
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#define CONFIG_SPL_GPIO_SUPPORT |
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#define CONFIG_SPL_I2C_SUPPORT |
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#define CONFIG_SPL_MMC_SUPPORT |
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2 |
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/*
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* Console |
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*/ |
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_CBSIZE 512 |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \ |
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+ 16) |
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/*
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* Serial |
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*/ |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
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#define CONFIG_SYS_NS16550_CLK 48000000 |
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#define CONFIG_SYS_NS16550_COM3 UART3_BASE |
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#define CONFIG_CONS_INDEX 3 |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ |
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115200 } |
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/*
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* Environment |
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*/ |
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#define CONFIG_ENV_SIZE (128 * 1024) |
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#define CONFIG_ENV_IS_NOWHERE |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"kernel_addr_r=0x82000000\0" \
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"loadaddr=0x82000000\0" \
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"fdt_addr_r=0x88000000\0" \
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"fdtaddr=0x88000000\0" \
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"ramdisk_addr_r=0x88080000\0" \
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"pxefile_addr_r=0x80100000\0" \
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"scriptaddr=0x80000000\0" \
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"bootm_size=0x10000000\0" \
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"boot_mmc_dev=0\0" \
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"kernel_mmc_part=7\0" \
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"recovery_mmc_part=5\0" \
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"bootargs=mem=512M console=ttyO2\0" |
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/*
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* ATAGs |
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*/ |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_REVISION_TAG |
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#define CONFIG_SERIAL_TAG |
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/*
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* Boot |
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*/ |
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#define CONFIG_SYS_LOAD_ADDR 0x82000000 |
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#define CONFIG_ANDROID_BOOT_IMAGE |
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#define CONFIG_BOOTCOMMAND \ |
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"setenv boot_mmc_part ${kernel_mmc_part}; " \
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"part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
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"part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
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"mmc dev ${boot_mmc_dev}; " \
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"mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
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"bootm ${kernel_addr_r};" |
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/*
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* Defaults |
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*/ |
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#include <config_defaults.h> |
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#include <config_distro_defaults.h> |
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#endif |
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