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@ -29,6 +29,7 @@ |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#include <asm/fsl_law.h> |
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#include <asm/errno.h> |
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#include "fsl_corenet_serdes.h" |
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static u32 serdes_prtcl_map; |
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@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane) |
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return lanes[lane].idx; |
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} |
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int serdes_get_bank(int lane) |
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int serdes_get_bank_by_lane(int lane) |
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{ |
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return lanes[lane].bank; |
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} |
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@ -132,6 +133,125 @@ int is_serdes_configured(enum srds_prtcl device) |
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return (1 << device) & serdes_prtcl_map; |
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} |
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static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) |
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{ |
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int i; |
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for (i = 0; i < SRDS_MAX_LANES; i++) { |
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if (serdes_get_prtcl(prtcl, i) == device) |
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return i; |
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} |
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return -ENODEV; |
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} |
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/*
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* Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given |
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* device. This depends on the current SERDES protocol, as defined in the RCW. |
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* |
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* Returns a negative error code if SERDES is disabled or the given device is |
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* not supported in the current SERDES protocol. |
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*/ |
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int serdes_get_first_lane(enum srds_prtcl device) |
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{ |
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u32 prtcl; |
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const ccsr_gur_t *gur; |
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gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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/* Is serdes enabled at all? */ |
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if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) |
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return -ENODEV; |
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prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; |
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return __serdes_get_first_lane(prtcl, device); |
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} |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 |
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/*
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* Returns the SERDES bank (1, 2, or 3) that a given device is on for a given |
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* SERDES protocol. |
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* |
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* Returns a negative error code if the given device is not supported for the |
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* given SERDES protocol. |
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*/ |
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static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) |
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{ |
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int lane; |
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lane = __serdes_get_first_lane(prtcl, device); |
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if (unlikely(lane < 0)) |
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return lane; |
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return serdes_get_bank_by_lane(lane); |
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} |
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static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, |
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int first) |
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{ |
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int lane; |
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for (lane = first; lane < SRDS_MAX_LANES; lane++) { |
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if (serdes_get_prtcl(prtcl, lane) != device) |
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break; |
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} |
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return lane - first; |
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} |
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static void __serdes_reset_rx(serdes_corenet_t *regs, |
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uint32_t prtcl, |
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enum srds_prtcl device) |
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{ |
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int lane, idx, first, last; |
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lane = __serdes_get_first_lane(prtcl, device); |
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if (unlikely(lane < 0)) |
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return; |
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first = serdes_get_lane_idx(lane); |
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last = first + __serdes_get_lane_count(prtcl, device, lane); |
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/*
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* Set BnGCRy0[RRST] = 0 for each lane in the each bank that is |
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* selected as XAUI to place the lane into reset. |
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*/ |
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for (idx = first; idx < last; idx++) |
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clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); |
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/* Wait at least 250 ns */ |
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udelay(1); |
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/*
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* Set BnGCRy0[RRST] = 1 for each lane in the each bank that is |
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* selected as XAUI to bring the lane out of reset. |
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*/ |
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for (idx = first; idx < last; idx++) |
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setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); |
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} |
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void serdes_reset_rx(enum srds_prtcl device) |
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{ |
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u32 prtcl; |
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const ccsr_gur_t *gur; |
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serdes_corenet_t *regs; |
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if (unlikely(device == NONE)) |
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return; |
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gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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/* Is serdes enabled at all? */ |
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if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) |
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return; |
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regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
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prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; |
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__serdes_reset_rx(regs, prtcl, device); |
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} |
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#endif |
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#ifndef CONFIG_SYS_DCSRBAR_PHYS |
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#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ |
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#define CONFIG_SYS_DCSRBAR 0x80000000 |
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@ -266,6 +386,74 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, |
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} |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
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/*
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* If PCIe is not selected as a protocol for any lanes driven by a given PLL, |
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* that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. |
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*/ |
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static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) |
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{ |
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enum srds_prtcl device; |
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switch (cfg) { |
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case 0x13: |
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case 0x16: |
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/*
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* If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] |
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* to 0. |
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*/ |
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clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, |
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SRDS_PLLCR1_PLL_BWSEL); |
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break; |
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case 0x19: |
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/*
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* If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and |
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* SRDSB3PLLCR1[PLLBW_SEL] to 1. |
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*/ |
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clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, |
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SRDS_PLLCR1_PLL_BWSEL); |
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setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, |
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SRDS_PLLCR1_PLL_BWSEL); |
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break; |
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} |
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/*
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* Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI |
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* before XAUI is initialized. |
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*/ |
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for (device = XAUI_FM1; device <= XAUI_FM2; device++) { |
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if (is_serdes_configured(device)) { |
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int bank = serdes_get_bank_by_device(cfg, device); |
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clrbits_be32(®s->bank[bank].pllcr1, |
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SRDS_PLLCR1_PLL_BWSEL); |
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} |
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} |
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} |
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#endif |
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/*
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* Wait for the RSTDONE bit to get set, or a one-second timeout. |
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*/ |
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static void wait_for_rstdone(unsigned int bank) |
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{ |
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serdes_corenet_t *srds_regs = |
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
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unsigned long long end_tick; |
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u32 rstctl; |
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/* wait for reset complete or 1-second timeout */ |
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end_tick = usec2ticks(1000000) + get_ticks(); |
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do { |
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rstctl = in_be32(&srds_regs->bank[bank].rstctl); |
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if (rstctl & SRDS_RSTCTL_RSTDONE) |
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break; |
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} while (end_tick > get_ticks()); |
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if (!(rstctl & SRDS_RSTCTL_RSTDONE)) |
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printf("SERDES: timeout resetting bank %u\n", bank); |
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} |
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void fsl_serdes_init(void) |
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{ |
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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@ -273,7 +461,6 @@ void fsl_serdes_init(void) |
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serdes_corenet_t *srds_regs; |
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int lane, bank, idx; |
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enum srds_prtcl lane_prtcl; |
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long long end_tick; |
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int have_bank[SRDS_MAX_BANK] = {}; |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 |
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u32 serdes8_devdisr = 0; |
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@ -282,6 +469,12 @@ void fsl_serdes_init(void) |
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const char *srds_lpd_arg; |
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size_t arglen; |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 |
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enum srds_prtcl device; |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
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int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ |
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#endif |
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char buffer[HWCONFIG_BUFFER_SIZE]; |
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char *buf = NULL; |
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@ -307,6 +500,17 @@ void fsl_serdes_init(void) |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 |
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/*
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* Display a warning if banks two and three are not disabled in the RCW, |
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* since our work-around for SERDES8 depends on these banks being |
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* disabled at power-on. |
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*/ |
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#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) |
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if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { |
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printf("Warning: SERDES8 requires banks two and " |
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"three to be disabled in the RCW\n"); |
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} |
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/*
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* Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 |
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* hwconfig options into the srds_lpd_b[] array. See README.p4080ds |
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* for a description of these options. |
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@ -325,7 +529,7 @@ void fsl_serdes_init(void) |
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) { |
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); |
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if (serdes_lane_enabled(lane)) { |
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have_bank[serdes_get_bank(lane)] = 1; |
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have_bank[serdes_get_bank_by_lane(lane)] = 1; |
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serdes_prtcl_map |= (1 << lane_prtcl); |
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} |
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} |
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@ -339,11 +543,32 @@ void fsl_serdes_init(void) |
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have_bank[FSL_SRDS_BANK_3] = 1; |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
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/*
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* The work-aroud for erratum SERDES-A001 is needed only if bank two |
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* is disabled and bank three is enabled. |
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*/ |
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need_serdes_a001 = |
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!have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; |
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#endif |
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/* Power down the banks we're not interested in */ |
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for (bank = 0; bank < SRDS_MAX_BANK; bank++) { |
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if (!have_bank[bank]) { |
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printf("SERDES: bank %d disabled\n", bank + 1); |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
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/*
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* Erratum SERDES-A001 says bank two needs to be powered |
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* down after bank three is powered up, so don't power |
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* down bank two here. |
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*/ |
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if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) |
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setbits_be32(&srds_regs->bank[bank].rstctl, |
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SRDS_RSTCTL_SDPD); |
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#else |
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setbits_be32(&srds_regs->bank[bank].rstctl, |
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SRDS_RSTCTL_SDPD); |
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#endif |
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} |
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} |
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@ -369,6 +594,35 @@ void fsl_serdes_init(void) |
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printf("%s ", serdes_prtcl_str[lane_prtcl]); |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 |
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/*
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* Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for |
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* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or |
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* AURORA before the device is initialized. |
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*/ |
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switch (lane_prtcl) { |
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case SGMII_FM1_DTSEC1: |
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case SGMII_FM1_DTSEC2: |
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case SGMII_FM1_DTSEC3: |
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case SGMII_FM1_DTSEC4: |
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case SGMII_FM2_DTSEC1: |
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case SGMII_FM2_DTSEC2: |
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case SGMII_FM2_DTSEC3: |
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case SGMII_FM2_DTSEC4: |
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case XAUI_FM1: |
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case XAUI_FM2: |
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case SRIO1: |
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case SRIO2: |
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case AURORA: |
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clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, |
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SRDS_TTLCR0_FLT_SEL_MASK, |
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SRDS_TTLCR0_FLT_SEL_750PPM | |
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SRDS_TTLCR0_PM_DIS); |
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default: |
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break; |
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} |
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#endif |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 |
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switch (lane_prtcl) { |
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case PCIE1: |
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@ -415,13 +669,12 @@ void fsl_serdes_init(void) |
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FSL_CORENET_DEVDISR2_DTSEC2_4; |
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break; |
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case XAUI_FM1: |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | |
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FSL_CORENET_DEVDISR2_10GEC1; |
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break; |
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case XAUI_FM2: |
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if (lane_prtcl == XAUI_FM1) |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | |
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FSL_CORENET_DEVDISR2_10GEC1; |
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else |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | |
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FSL_CORENET_DEVDISR2_10GEC2; |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | |
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FSL_CORENET_DEVDISR2_10GEC2; |
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break; |
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case AURORA: |
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break; |
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@ -436,9 +689,11 @@ void fsl_serdes_init(void) |
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puts("\n"); |
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#endif |
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for (idx = 0; idx < SRDS_MAX_BANK; idx++) { |
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u32 rstctl; |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
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p4080_erratum_serdes_a005(srds_regs, cfg); |
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#endif |
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for (idx = 0; idx < SRDS_MAX_BANK; idx++) { |
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bank = idx; |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 |
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@ -477,18 +732,30 @@ void fsl_serdes_init(void) |
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/* reset banks for errata */ |
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setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); |
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/* wait for reset complete or 1-second timeout */ |
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end_tick = usec2ticks(1000000) + get_ticks(); |
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do { |
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rstctl = in_be32(&srds_regs->bank[bank].rstctl); |
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if (rstctl & SRDS_RSTCTL_RSTDONE) |
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break; |
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} while (end_tick > get_ticks()); |
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if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { |
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printf("SERDES: timeout resetting bank %d\n", |
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bank + 1); |
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continue; |
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} |
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|
wait_for_rstdone(bank); |
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} |
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
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|
|
if (need_serdes_a001) { |
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|
|
/*
|
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|
* Bank three has been enabled, so enable bank two and then |
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|
* disable it. |
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|
*/ |
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|
srds_lpd_b[FSL_SRDS_BANK_2] = 0; |
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|
enable_bank(gur, FSL_SRDS_BANK_2); |
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|
wait_for_rstdone(FSL_SRDS_BANK_2); |
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|
/* Disable bank 2 */ |
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|
|
setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, |
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|
|
SRDS_RSTCTL_SDPD); |
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|
} |
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|
#endif |
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|
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 |
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|
|
for (device = XAUI_FM1; device <= XAUI_FM2; device++) { |
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|
|
if (is_serdes_configured(device)) |
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|
|
__serdes_reset_rx(srds_regs, cfg, device); |
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|
|
} |
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|
#endif |
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|
|
} |
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Wolfgang Denk
14 years ago