Nowdays, there are plenty of mmc driver in uboot adopt the sd standard host design, aka as sdhci. It is better to centralize the common logic together to better maintenance. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>master
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/*
|
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* Copyright 2011, Marvell Semiconductor Inc. |
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* Lei Wen <leiwen@marvell.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Back ported to the 8xx platform (from the 8260 platform) by |
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <mmc.h> |
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#include <sdhci.h> |
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void *aligned_buffer; |
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static void sdhci_reset(struct sdhci_host *host, u8 mask) |
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{ |
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unsigned long timeout; |
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/* Wait max 100 ms */ |
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timeout = 100; |
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sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
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while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
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if (timeout == 0) { |
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printf("Reset 0x%x never completed.\n", (int)mask); |
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return; |
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} |
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timeout--; |
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udelay(1000); |
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} |
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} |
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static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) |
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{ |
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int i; |
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if (cmd->resp_type & MMC_RSP_136) { |
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/* CRC is stripped so we need to do some shifting. */ |
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for (i = 0; i < 4; i++) { |
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cmd->response[i] = sdhci_readl(host, |
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SDHCI_RESPONSE + (3-i)*4) << 8; |
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if (i != 3) |
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cmd->response[i] |= sdhci_readb(host, |
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SDHCI_RESPONSE + (3-i)*4-1); |
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} |
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} else { |
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cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); |
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} |
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} |
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static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) |
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{ |
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int i; |
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char *offs; |
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for (i = 0; i < data->blocksize; i += 4) { |
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offs = data->dest + i; |
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if (data->flags == MMC_DATA_READ) |
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*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); |
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else |
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sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); |
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} |
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} |
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|
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static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, |
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unsigned int start_addr) |
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{ |
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unsigned int stat, rdy, mask, block = 0; |
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rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; |
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mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; |
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do { |
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stat = sdhci_readl(host, SDHCI_INT_STATUS); |
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if (stat & SDHCI_INT_ERROR) { |
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printf("Error detected in status(0x%X)!\n", stat); |
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return -1; |
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} |
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if (stat & rdy) { |
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if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) |
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continue; |
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sdhci_writel(host, rdy, SDHCI_INT_STATUS); |
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sdhci_transfer_pio(host, data); |
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data->dest += data->blocksize; |
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if (++block >= data->blocks) |
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break; |
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} |
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#ifdef CONFIG_MMC_SDMA |
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if (stat & SDHCI_INT_DMA_END) { |
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sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); |
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start_addr &= SDHCI_DEFAULT_BOUNDARY_SIZE - 1; |
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start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; |
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sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); |
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} |
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#endif |
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} while (!(stat & SDHCI_INT_DATA_END)); |
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return 0; |
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} |
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int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct sdhci_host *host = (struct sdhci_host *)mmc->priv; |
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unsigned int stat = 0; |
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int ret = 0; |
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int trans_bytes = 0, is_aligned = 1; |
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u32 mask, flags, mode; |
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unsigned int timeout, start_addr = 0; |
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/* Wait max 10 ms */ |
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timeout = 10; |
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sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); |
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mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; |
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/* We shouldn't wait for data inihibit for stop commands, even
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though they might use busy signaling */ |
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
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mask &= ~SDHCI_DATA_INHIBIT; |
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while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
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if (timeout == 0) { |
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printf("Controller never released inhibit bit(s).\n"); |
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return COMM_ERR; |
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} |
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timeout--; |
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udelay(1000); |
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} |
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mask = SDHCI_INT_RESPONSE; |
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if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
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flags = SDHCI_CMD_RESP_NONE; |
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else if (cmd->resp_type & MMC_RSP_136) |
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flags = SDHCI_CMD_RESP_LONG; |
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else if (cmd->resp_type & MMC_RSP_BUSY) { |
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flags = SDHCI_CMD_RESP_SHORT_BUSY; |
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mask |= SDHCI_INT_DATA_END; |
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} else |
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flags = SDHCI_CMD_RESP_SHORT; |
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if (cmd->resp_type & MMC_RSP_CRC) |
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flags |= SDHCI_CMD_CRC; |
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if (cmd->resp_type & MMC_RSP_OPCODE) |
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flags |= SDHCI_CMD_INDEX; |
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if (data) |
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flags |= SDHCI_CMD_DATA; |
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/*Set Transfer mode regarding to data flag*/ |
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if (data != 0) { |
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sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); |
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mode = SDHCI_TRNS_BLK_CNT_EN; |
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trans_bytes = data->blocks * data->blocksize; |
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if (data->blocks > 1) |
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mode |= SDHCI_TRNS_MULTI; |
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if (data->flags == MMC_DATA_READ) |
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mode |= SDHCI_TRNS_READ; |
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#ifdef CONFIG_MMC_SDMA |
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if (data->flags == MMC_DATA_READ) |
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start_addr = (unsigned int)data->dest; |
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else |
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start_addr = (unsigned int)data->src; |
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && |
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(start_addr & 0x7) != 0x0) { |
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is_aligned = 0; |
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start_addr = (unsigned int)aligned_buffer; |
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if (data->flags != MMC_DATA_READ) |
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memcpy(aligned_buffer, data->src, trans_bytes); |
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} |
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sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); |
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mode |= SDHCI_TRNS_DMA; |
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#endif |
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sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
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data->blocksize), |
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SDHCI_BLOCK_SIZE); |
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sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
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sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
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} |
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sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); |
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#ifdef CONFIG_MMC_SDMA |
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flush_cache(0, ~0); |
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#endif |
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sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); |
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do { |
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stat = sdhci_readl(host, SDHCI_INT_STATUS); |
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if (stat & SDHCI_INT_ERROR) |
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break; |
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} while ((stat & mask) != mask); |
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if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { |
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sdhci_cmd_done(host, cmd); |
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sdhci_writel(host, mask, SDHCI_INT_STATUS); |
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} else |
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ret = -1; |
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if (!ret && data) |
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ret = sdhci_transfer_data(host, data, start_addr); |
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stat = sdhci_readl(host, SDHCI_INT_STATUS); |
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sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); |
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if (!ret) { |
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && |
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!is_aligned && (data->flags == MMC_DATA_READ)) |
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memcpy(data->dest, aligned_buffer, trans_bytes); |
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return 0; |
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} |
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sdhci_reset(host, SDHCI_RESET_CMD); |
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sdhci_reset(host, SDHCI_RESET_DATA); |
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if (stat & SDHCI_INT_TIMEOUT) |
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return TIMEOUT; |
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else |
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return COMM_ERR; |
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} |
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static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) |
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{ |
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struct sdhci_host *host = (struct sdhci_host *)mmc->priv; |
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unsigned int div, clk, timeout; |
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
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if (clock == 0) |
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return 0; |
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if (host->version >= SDHCI_SPEC_300) { |
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/* Version 3.00 divisors must be a multiple of 2. */ |
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if (mmc->f_max <= clock) |
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div = 1; |
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else { |
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for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
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if ((mmc->f_max / div) <= clock) |
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break; |
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} |
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} |
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} else { |
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/* Version 2.00 divisors must be a power of 2. */ |
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for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
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if ((mmc->f_max / div) <= clock) |
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break; |
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} |
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} |
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div >>= 1; |
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clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
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clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
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<< SDHCI_DIVIDER_HI_SHIFT; |
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clk |= SDHCI_CLOCK_INT_EN; |
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
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/* Wait max 20 ms */ |
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timeout = 20; |
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
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& SDHCI_CLOCK_INT_STABLE)) { |
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if (timeout == 0) { |
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printf("Internal clock never stabilised.\n"); |
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return -1; |
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} |
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timeout--; |
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udelay(1000); |
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} |
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clk |= SDHCI_CLOCK_CARD_EN; |
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
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return 0; |
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} |
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static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
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{ |
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u8 pwr = 0; |
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if (power != (unsigned short)-1) { |
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switch (1 << power) { |
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case MMC_VDD_165_195: |
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pwr = SDHCI_POWER_180; |
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break; |
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case MMC_VDD_29_30: |
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case MMC_VDD_30_31: |
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pwr = SDHCI_POWER_300; |
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break; |
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case MMC_VDD_32_33: |
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case MMC_VDD_33_34: |
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pwr = SDHCI_POWER_330; |
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break; |
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} |
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} |
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if (pwr == 0) { |
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sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
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return; |
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} |
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pwr |= SDHCI_POWER_ON; |
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sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
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} |
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void sdhci_set_ios(struct mmc *mmc) |
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{ |
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u32 ctrl; |
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struct sdhci_host *host = (struct sdhci_host *)mmc->priv; |
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if (mmc->clock != host->clock) |
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sdhci_set_clock(mmc, mmc->clock); |
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/* Set bus width */ |
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
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if (mmc->bus_width == 8) { |
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ctrl &= ~SDHCI_CTRL_4BITBUS; |
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if (host->version >= SDHCI_SPEC_300) |
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ctrl |= SDHCI_CTRL_8BITBUS; |
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} else { |
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if (host->version >= SDHCI_SPEC_300) |
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ctrl &= ~SDHCI_CTRL_8BITBUS; |
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if (mmc->bus_width == 4) |
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ctrl |= SDHCI_CTRL_4BITBUS; |
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else |
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ctrl &= ~SDHCI_CTRL_4BITBUS; |
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} |
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if (mmc->clock > 26000000) |
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ctrl |= SDHCI_CTRL_HISPD; |
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else |
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ctrl &= ~SDHCI_CTRL_HISPD; |
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
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} |
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int sdhci_init(struct mmc *mmc) |
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{ |
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struct sdhci_host *host = (struct sdhci_host *)mmc->priv; |
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { |
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aligned_buffer = memalign(8, 512*1024); |
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if (!aligned_buffer) { |
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printf("Aligned buffer alloc failed!!!"); |
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return -1; |
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} |
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} |
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/* Eable all state */ |
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sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE); |
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sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE); |
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sdhci_set_power(host, fls(mmc->voltages) - 1); |
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return 0; |
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} |
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int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) |
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{ |
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struct mmc *mmc; |
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unsigned int caps; |
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mmc = malloc(sizeof(struct mmc)); |
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if (!mmc) { |
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printf("mmc malloc fail!\n"); |
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return -1; |
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} |
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mmc->priv = host; |
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sprintf(mmc->name, "%s", host->name); |
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mmc->send_cmd = sdhci_send_command; |
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mmc->set_ios = sdhci_set_ios; |
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mmc->init = sdhci_init; |
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caps = sdhci_readl(host, SDHCI_CAPABILITIES); |
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#ifdef CONFIG_MMC_SDMA |
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if (!(caps & SDHCI_CAN_DO_SDMA)) { |
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printf("Your controller don't support sdma!!\n"); |
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return -1; |
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} |
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#endif |
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if (max_clk) |
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mmc->f_max = max_clk; |
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else { |
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if (host->version >= SDHCI_SPEC_300) |
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mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) |
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>> SDHCI_CLOCK_BASE_SHIFT; |
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else |
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mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) |
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>> SDHCI_CLOCK_BASE_SHIFT; |
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mmc->f_max *= 1000000; |
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} |
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if (mmc->f_max == 0) { |
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printf("Hardware doesn't specify base clock frequency\n"); |
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return -1; |
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} |
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if (min_clk) |
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mmc->f_min = min_clk; |
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else { |
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if (host->version >= SDHCI_SPEC_300) |
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mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; |
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else |
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mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; |
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} |
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mmc->voltages = 0; |
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if (caps & SDHCI_CAN_VDD_330) |
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mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
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if (caps & SDHCI_CAN_VDD_300) |
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mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
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if (caps & SDHCI_CAN_VDD_180) |
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mmc->voltages |= MMC_VDD_165_195; |
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mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; |
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if (caps & SDHCI_CAN_DO_8BIT) |
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mmc->host_caps |= MMC_MODE_8BIT; |
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sdhci_reset(host, SDHCI_RESET_ALL); |
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mmc_register(mmc); |
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return 0; |
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} |
@ -0,0 +1,325 @@ |
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/*
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* Copyright 2011, Marvell Semiconductor Inc. |
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* Lei Wen <leiwen@marvell.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Back ported to the 8xx platform (from the 8260 platform) by |
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
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*/ |
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#ifndef __SDHCI_HW_H |
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#define __SDHCI_HW_H |
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#include <asm/io.h> |
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/*
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* Controller registers |
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*/ |
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#define SDHCI_DMA_ADDRESS 0x00 |
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#define SDHCI_BLOCK_SIZE 0x04 |
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
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#define SDHCI_BLOCK_COUNT 0x06 |
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#define SDHCI_ARGUMENT 0x08 |
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#define SDHCI_TRANSFER_MODE 0x0C |
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#define SDHCI_TRNS_DMA 0x01 |
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#define SDHCI_TRNS_BLK_CNT_EN 0x02 |
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#define SDHCI_TRNS_ACMD12 0x04 |
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#define SDHCI_TRNS_READ 0x10 |
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#define SDHCI_TRNS_MULTI 0x20 |
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#define SDHCI_COMMAND 0x0E |
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#define SDHCI_CMD_RESP_MASK 0x03 |
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#define SDHCI_CMD_CRC 0x08 |
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#define SDHCI_CMD_INDEX 0x10 |
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#define SDHCI_CMD_DATA 0x20 |
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#define SDHCI_CMD_ABORTCMD 0xC0 |
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#define SDHCI_CMD_RESP_NONE 0x00 |
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#define SDHCI_CMD_RESP_LONG 0x01 |
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#define SDHCI_CMD_RESP_SHORT 0x02 |
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
||||
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
||||
|
||||
#define SDHCI_RESPONSE 0x10 |
||||
|
||||
#define SDHCI_BUFFER 0x20 |
||||
|
||||
#define SDHCI_PRESENT_STATE 0x24 |
||||
#define SDHCI_CMD_INHIBIT 0x00000001 |
||||
#define SDHCI_DATA_INHIBIT 0x00000002 |
||||
#define SDHCI_DOING_WRITE 0x00000100 |
||||
#define SDHCI_DOING_READ 0x00000200 |
||||
#define SDHCI_SPACE_AVAILABLE 0x00000400 |
||||
#define SDHCI_DATA_AVAILABLE 0x00000800 |
||||
#define SDHCI_CARD_PRESENT 0x00010000 |
||||
#define SDHCI_WRITE_PROTECT 0x00080000 |
||||
|
||||
#define SDHCI_HOST_CONTROL 0x28 |
||||
#define SDHCI_CTRL_LED 0x01 |
||||
#define SDHCI_CTRL_4BITBUS 0x02 |
||||
#define SDHCI_CTRL_HISPD 0x04 |
||||
#define SDHCI_CTRL_DMA_MASK 0x18 |
||||
#define SDHCI_CTRL_SDMA 0x00 |
||||
#define SDHCI_CTRL_ADMA1 0x08 |
||||
#define SDHCI_CTRL_ADMA32 0x10 |
||||
#define SDHCI_CTRL_ADMA64 0x18 |
||||
#define SDHCI_CTRL_8BITBUS 0x20 |
||||
|
||||
#define SDHCI_POWER_CONTROL 0x29 |
||||
#define SDHCI_POWER_ON 0x01 |
||||
#define SDHCI_POWER_180 0x0A |
||||
#define SDHCI_POWER_300 0x0C |
||||
#define SDHCI_POWER_330 0x0E |
||||
|
||||
#define SDHCI_BLOCK_GAP_CONTROL 0x2A |
||||
|
||||
#define SDHCI_WAKE_UP_CONTROL 0x2B |
||||
#define SDHCI_WAKE_ON_INT 0x01 |
||||
#define SDHCI_WAKE_ON_INSERT 0x02 |
||||
#define SDHCI_WAKE_ON_REMOVE 0x04 |
||||
|
||||
#define SDHCI_CLOCK_CONTROL 0x2C |
||||
#define SDHCI_DIVIDER_SHIFT 8 |
||||
#define SDHCI_DIVIDER_HI_SHIFT 6 |
||||
#define SDHCI_DIV_MASK 0xFF |
||||
#define SDHCI_DIV_MASK_LEN 8 |
||||
#define SDHCI_DIV_HI_MASK 0x300 |
||||
#define SDHCI_CLOCK_CARD_EN 0x0004 |
||||
#define SDHCI_CLOCK_INT_STABLE 0x0002 |
||||
#define SDHCI_CLOCK_INT_EN 0x0001 |
||||
|
||||
#define SDHCI_TIMEOUT_CONTROL 0x2E |
||||
|
||||
#define SDHCI_SOFTWARE_RESET 0x2F |
||||
#define SDHCI_RESET_ALL 0x01 |
||||
#define SDHCI_RESET_CMD 0x02 |
||||
#define SDHCI_RESET_DATA 0x04 |
||||
|
||||
#define SDHCI_INT_STATUS 0x30 |
||||
#define SDHCI_INT_ENABLE 0x34 |
||||
#define SDHCI_SIGNAL_ENABLE 0x38 |
||||
#define SDHCI_INT_RESPONSE 0x00000001 |
||||
#define SDHCI_INT_DATA_END 0x00000002 |
||||
#define SDHCI_INT_DMA_END 0x00000008 |
||||
#define SDHCI_INT_SPACE_AVAIL 0x00000010 |
||||
#define SDHCI_INT_DATA_AVAIL 0x00000020 |
||||
#define SDHCI_INT_CARD_INSERT 0x00000040 |
||||
#define SDHCI_INT_CARD_REMOVE 0x00000080 |
||||
#define SDHCI_INT_CARD_INT 0x00000100 |
||||
#define SDHCI_INT_ERROR 0x00008000 |
||||
#define SDHCI_INT_TIMEOUT 0x00010000 |
||||
#define SDHCI_INT_CRC 0x00020000 |
||||
#define SDHCI_INT_END_BIT 0x00040000 |
||||
#define SDHCI_INT_INDEX 0x00080000 |
||||
#define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
||||
#define SDHCI_INT_DATA_CRC 0x00200000 |
||||
#define SDHCI_INT_DATA_END_BIT 0x00400000 |
||||
#define SDHCI_INT_BUS_POWER 0x00800000 |
||||
#define SDHCI_INT_ACMD12ERR 0x01000000 |
||||
#define SDHCI_INT_ADMA_ERROR 0x02000000 |
||||
|
||||
#define SDHCI_INT_NORMAL_MASK 0x00007FFF |
||||
#define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
||||
|
||||
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
||||
SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
||||
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
||||
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
|
||||
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
|
||||
SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) |
||||
#define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
||||
|
||||
#define SDHCI_ACMD12_ERR 0x3C |
||||
|
||||
/* 3E-3F reserved */ |
||||
|
||||
#define SDHCI_CAPABILITIES 0x40 |
||||
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
||||
#define SDHCI_TIMEOUT_CLK_SHIFT 0 |
||||
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
||||
#define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
||||
#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
||||
#define SDHCI_CLOCK_BASE_SHIFT 8 |
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000 |
||||
#define SDHCI_MAX_BLOCK_SHIFT 16 |
||||
#define SDHCI_CAN_DO_8BIT 0x00040000 |
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000 |
||||
#define SDHCI_CAN_DO_ADMA1 0x00100000 |
||||
#define SDHCI_CAN_DO_HISPD 0x00200000 |
||||
#define SDHCI_CAN_DO_SDMA 0x00400000 |
||||
#define SDHCI_CAN_VDD_330 0x01000000 |
||||
#define SDHCI_CAN_VDD_300 0x02000000 |
||||
#define SDHCI_CAN_VDD_180 0x04000000 |
||||
#define SDHCI_CAN_64BIT 0x10000000 |
||||
|
||||
#define SDHCI_CAPABILITIES_1 0x44 |
||||
|
||||
#define SDHCI_MAX_CURRENT 0x48 |
||||
|
||||
/* 4C-4F reserved for more max current */ |
||||
|
||||
#define SDHCI_SET_ACMD12_ERROR 0x50 |
||||
#define SDHCI_SET_INT_ERROR 0x52 |
||||
|
||||
#define SDHCI_ADMA_ERROR 0x54 |
||||
|
||||
/* 55-57 reserved */ |
||||
|
||||
#define SDHCI_ADMA_ADDRESS 0x58 |
||||
|
||||
/* 60-FB reserved */ |
||||
|
||||
#define SDHCI_SLOT_INT_STATUS 0xFC |
||||
|
||||
#define SDHCI_HOST_VERSION 0xFE |
||||
#define SDHCI_VENDOR_VER_MASK 0xFF00 |
||||
#define SDHCI_VENDOR_VER_SHIFT 8 |
||||
#define SDHCI_SPEC_VER_MASK 0x00FF |
||||
#define SDHCI_SPEC_VER_SHIFT 0 |
||||
#define SDHCI_SPEC_100 0 |
||||
#define SDHCI_SPEC_200 1 |
||||
#define SDHCI_SPEC_300 2 |
||||
|
||||
/*
|
||||
* End of controller registers. |
||||
*/ |
||||
|
||||
#define SDHCI_MAX_DIV_SPEC_200 256 |
||||
#define SDHCI_MAX_DIV_SPEC_300 2046 |
||||
|
||||
/*
|
||||
* quirks |
||||
*/ |
||||
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) |
||||
|
||||
/*
|
||||
* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
||||
*/ |
||||
#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
||||
#define SDHCI_DEFAULT_BOUNDARY_ARG (7) |
||||
struct sdhci_ops { |
||||
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
||||
u32 (*read_l)(struct sdhci_host *host, int reg); |
||||
u16 (*read_w)(struct sdhci_host *host, int reg); |
||||
u8 (*read_b)(struct sdhci_host *host, int reg); |
||||
void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
||||
void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
||||
void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
||||
#endif |
||||
}; |
||||
|
||||
struct sdhci_host { |
||||
char *name; |
||||
void *ioaddr; |
||||
unsigned int quirks; |
||||
unsigned int version; |
||||
unsigned int clock; |
||||
const struct sdhci_ops *ops; |
||||
}; |
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
||||
|
||||
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
||||
{ |
||||
if (unlikely(host->ops->write_l)) |
||||
host->ops->write_l(host, val, reg); |
||||
else |
||||
writel(val, host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
||||
{ |
||||
if (unlikely(host->ops->write_w)) |
||||
host->ops->write_w(host, val, reg); |
||||
else |
||||
writew(val, host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
||||
{ |
||||
if (unlikely(host->ops->write_b)) |
||||
host->ops->write_b(host, val, reg); |
||||
else |
||||
writeb(val, host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
||||
{ |
||||
if (unlikely(host->ops->read_l)) |
||||
return host->ops->read_l(host, reg); |
||||
else |
||||
return readl(host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
||||
{ |
||||
if (unlikely(host->ops->read_w)) |
||||
return host->ops->read_w(host, reg); |
||||
else |
||||
return readw(host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
||||
{ |
||||
if (unlikely(host->ops->read_b)) |
||||
return host->ops->read_b(host, reg); |
||||
else |
||||
return readb(host->ioaddr + reg); |
||||
} |
||||
|
||||
#else |
||||
|
||||
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
||||
{ |
||||
writel(val, host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
||||
{ |
||||
writew(val, host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
||||
{ |
||||
writeb(val, host->ioaddr + reg); |
||||
} |
||||
static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
||||
{ |
||||
return readl(host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
||||
{ |
||||
return readw(host->ioaddr + reg); |
||||
} |
||||
|
||||
static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
||||
{ |
||||
return readb(host->ioaddr + reg); |
||||
} |
||||
#endif |
||||
|
||||
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); |
||||
#endif /* __SDHCI_HW_H */ |
Loading…
Reference in new issue