This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>master
parent
6f62f42071
commit
afad40299e
@ -1,45 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS-y += cache.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -1,86 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
void icache_enable (void) |
||||
{ |
||||
s32 i; |
||||
|
||||
/* disable all cache bits */ |
||||
CLR_REG( REG_SYSCFG, 0x3F); |
||||
|
||||
/* 8KB cache, write enable */ |
||||
SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); |
||||
|
||||
/* clear TAG RAM bits */ |
||||
for ( i = 0; i < 256; i++) |
||||
PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); |
||||
|
||||
/* clear SET0 RAM */ |
||||
for(i=0; i < 1024; i++) |
||||
PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); |
||||
|
||||
/* clear SET1 RAM */ |
||||
for(i=0; i < 1024; i++) |
||||
PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); |
||||
|
||||
/* enable cache */ |
||||
SET_REG( REG_SYSCFG, CACHE_ENABLE); |
||||
|
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
/* disable all cache bits */ |
||||
CLR_REG( REG_SYSCFG, 0x3F); |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
return GET_REG( REG_SYSCFG) & CACHE_ENABLE; |
||||
} |
||||
|
||||
void dcache_enable (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
icache_enable(); |
||||
} |
||||
|
||||
void dcache_disable (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
icache_disable(); |
||||
} |
||||
|
||||
int dcache_status (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
return icache_status(); |
||||
} |
@ -1,272 +0,0 @@ |
||||
#ifndef __HW_S3C4510_H |
||||
#define __HW_S3C4510_H |
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Description: Samsung S3C4510B register layout |
||||
*/ |
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* ASIC Address Definition |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
/* L1 8KB on chip SRAM base address */ |
||||
#define SRAM_BASE (0x03fe0000) |
||||
|
||||
/* Special Register Start Address After System Reset */ |
||||
#define REG_BASE (0x03ff0000) |
||||
#define SPSTR (REG_BASE) |
||||
|
||||
/* *********************** */ |
||||
/* System Manager Register */ |
||||
/* *********************** */ |
||||
#define REG_SYSCFG (REG_BASE+0x0000) |
||||
|
||||
#define REG_CLKCON (REG_BASE+0x3000) |
||||
#define REG_EXTACON0 (REG_BASE+0x3008) |
||||
#define REG_EXTACON1 (REG_BASE+0x300c) |
||||
#define REG_EXTDBWTH (REG_BASE+0x3010) |
||||
#define REG_ROMCON0 (REG_BASE+0x3014) |
||||
#define REG_ROMCON1 (REG_BASE+0x3018) |
||||
#define REG_ROMCON2 (REG_BASE+0x301c) |
||||
#define REG_ROMCON3 (REG_BASE+0x3020) |
||||
#define REG_ROMCON4 (REG_BASE+0x3024) |
||||
#define REG_ROMCON5 (REG_BASE+0x3028) |
||||
#define REG_DRAMCON0 (REG_BASE+0x302c) |
||||
#define REG_DRAMCON1 (REG_BASE+0x3030) |
||||
#define REG_DRAMCON2 (REG_BASE+0x3034) |
||||
#define REG_DRAMCON3 (REG_BASE+0x3038) |
||||
#define REG_REFEXTCON (REG_BASE+0x303c) |
||||
|
||||
/* *********************** */ |
||||
/* Ethernet BDMA Register */ |
||||
/* *********************** */ |
||||
#define REG_BDMATXCON (REG_BASE+0x9000) |
||||
#define REG_BDMARXCON (REG_BASE+0x9004) |
||||
#define REG_BDMATXPTR (REG_BASE+0x9008) |
||||
#define REG_BDMARXPTR (REG_BASE+0x900c) |
||||
#define REG_BDMARXLSZ (REG_BASE+0x9010) |
||||
#define REG_BDMASTAT (REG_BASE+0x9014) |
||||
|
||||
/* Content Address Memory */ |
||||
#define REG_CAM_BASE (REG_BASE+0x9100) |
||||
|
||||
#define REG_BDMATXBUF (REG_BASE+0x9200) |
||||
#define REG_BDMARXBUF (REG_BASE+0x9800) |
||||
|
||||
/* *********************** */ |
||||
/* Ethernet MAC Register */ |
||||
/* *********************** */ |
||||
#define REG_MACCON (REG_BASE+0xa000) |
||||
#define REG_CAMCON (REG_BASE+0xa004) |
||||
#define REG_MACTXCON (REG_BASE+0xa008) |
||||
#define REG_MACTXSTAT (REG_BASE+0xa00c) |
||||
#define REG_MACRXCON (REG_BASE+0xa010) |
||||
#define REG_MACRXSTAT (REG_BASE+0xa014) |
||||
#define REG_STADATA (REG_BASE+0xa018) |
||||
#define REG_STACON (REG_BASE+0xa01c) |
||||
#define REG_CAMEN (REG_BASE+0xa028) |
||||
#define REG_EMISSCNT (REG_BASE+0xa03c) |
||||
#define REG_EPZCNT (REG_BASE+0xa040) |
||||
#define REG_ERMPZCNT (REG_BASE+0xa044) |
||||
#define REG_ETXSTAT (REG_BASE+0x9040) |
||||
#define REG_MACRXDESTR (REG_BASE+0xa064) |
||||
#define REG_MACRXSTATEM (REG_BASE+0xa090) |
||||
#define REG_MACRXFIFO (REG_BASE+0xa200) |
||||
|
||||
/********************/ |
||||
/* I2C Bus Register */ |
||||
/********************/ |
||||
#define REG_I2C_CON (REG_BASE+0xf000) |
||||
#define REG_I2C_BUF (REG_BASE+0xf004) |
||||
#define REG_I2C_PS (REG_BASE+0xf008) |
||||
#define REG_I2C_COUNT (REG_BASE+0xf00c) |
||||
|
||||
/********************/ |
||||
/* GDMA 0 */ |
||||
/********************/ |
||||
#define REG_GDMACON0 (REG_BASE+0xb000) |
||||
#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) |
||||
#define REG_GDMASRC0 (REG_BASE+0xb004) |
||||
#define REG_GDMADST0 (REG_BASE+0xb008) |
||||
#define REG_GDMACNT0 (REG_BASE+0xb00c) |
||||
|
||||
/********************/ |
||||
/* GDMA 1 */ |
||||
/********************/ |
||||
#define REG_GDMACON1 (REG_BASE+0xc000) |
||||
#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) |
||||
#define REG_GDMASRC1 (REG_BASE+0xc004) |
||||
#define REG_GDMADST1 (REG_BASE+0xc008) |
||||
#define REG_GDMACNT1 (REG_BASE+0xc00c) |
||||
|
||||
/********************/ |
||||
/* UART 0 */ |
||||
/********************/ |
||||
#define UART0_BASE (REG_BASE+0xd000) |
||||
#define REG_UART0_LCON (REG_BASE+0xd000) |
||||
#define REG_UART0_CTRL (REG_BASE+0xd004) |
||||
#define REG_UART0_STAT (REG_BASE+0xd008) |
||||
#define REG_UART0_TXB (REG_BASE+0xd00c) |
||||
#define REG_UART0_RXB (REG_BASE+0xd010) |
||||
#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) |
||||
#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) |
||||
#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) |
||||
|
||||
/********************/ |
||||
/* UART 1 */ |
||||
/********************/ |
||||
#define UART1_BASE (REG_BASE+0xe000) |
||||
#define REG_UART1_LCON (REG_BASE+0xe000) |
||||
#define REG_UART1_CTRL (REG_BASE+0xe004) |
||||
#define REG_UART1_STAT (REG_BASE+0xe008) |
||||
#define REG_UART1_TXB (REG_BASE+0xe00c) |
||||
#define REG_UART1_RXB (REG_BASE+0xe010) |
||||
#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) |
||||
#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) |
||||
#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) |
||||
|
||||
/********************/ |
||||
/* Timer Register */ |
||||
/********************/ |
||||
#define REG_TMOD (REG_BASE+0x6000) |
||||
#define REG_TDATA0 (REG_BASE+0x6004) |
||||
#define REG_TDATA1 (REG_BASE+0x6008) |
||||
#define REG_TCNT0 (REG_BASE+0x600c) |
||||
#define REG_TCNT1 (REG_BASE+0x6010) |
||||
|
||||
/**********************/ |
||||
/* I/O Port Interface */ |
||||
/**********************/ |
||||
#define REG_IOPMODE (REG_BASE+0x5000) |
||||
#define REG_IOPCON (REG_BASE+0x5004) |
||||
#define REG_IOPDATA (REG_BASE+0x5008) |
||||
|
||||
/*********************************/ |
||||
/* Interrupt Controller Register */ |
||||
/*********************************/ |
||||
#define REG_INTMODE (REG_BASE+0x4000) |
||||
#define REG_INTPEND (REG_BASE+0x4004) |
||||
#define REG_INTMASK (REG_BASE+0x4008) |
||||
|
||||
#define REG_INTPRI0 (REG_BASE+0x400c) |
||||
#define REG_INTPRI1 (REG_BASE+0x4010) |
||||
#define REG_INTPRI2 (REG_BASE+0x4014) |
||||
#define REG_INTPRI3 (REG_BASE+0x4018) |
||||
#define REG_INTPRI4 (REG_BASE+0x401c) |
||||
#define REG_INTPRI5 (REG_BASE+0x4020) |
||||
#define REG_INTOFFSET (REG_BASE+0x4024) |
||||
#define REG_INTPNDPRI (REG_BASE+0x4028) |
||||
#define REG_INTPNDTST (REG_BASE+0x402C) |
||||
|
||||
/*********************************/ |
||||
/* CACHE CONTROL MASKS */ |
||||
/*********************************/ |
||||
#define CACHE_STALL (0x00000001) |
||||
#define CACHE_ENABLE (0x00000002) |
||||
#define CACHE_WRITE_BUFF (0x00000004) |
||||
#define CACHE_MODE (0x00000030) |
||||
#define CACHE_MODE_00 (0x00000000) |
||||
#define CACHE_MODE_01 (0x00000010) |
||||
#define CACHE_MODE_10 (0x00000020) |
||||
|
||||
/*********************************/ |
||||
/* CACHE RAM BASE ADDRESSES */ |
||||
/*********************************/ |
||||
#define CACHE_SET0_RAM (0x10000000) |
||||
#define CACHE_SET1_RAM (0x10800000) |
||||
#define CACHE_TAG_RAM (0x11000000) |
||||
|
||||
/*********************************/ |
||||
/* CACHE_DISABLE MASK */ |
||||
/*********************************/ |
||||
#define CACHE_DISABLE_MASK (0x04000000) |
||||
|
||||
#define GET_REG(reg) (*((volatile u32 *)(reg))) |
||||
#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) |
||||
#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) |
||||
#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) |
||||
#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) |
||||
#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) |
||||
#define GET__U8(reg) (*((volatile u8 *)(reg))) |
||||
|
||||
#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) |
||||
#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) |
||||
#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } |
||||
#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } |
||||
|
||||
/***********************************/ |
||||
/* CLOCK CONSTANTS -- 50 MHz Clock */ |
||||
/***********************************/ |
||||
|
||||
#define CLK_FREQ_MHZ (50) |
||||
#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ |
||||
#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ |
||||
|
||||
/*********************************************************/ |
||||
/* TIMER MODE REGISTER */ |
||||
/*********************************************************/ |
||||
#define TM0_RUN 0x01 /* Timer 0 enable */ |
||||
#define TM0_TOGGLE 0x02 /* 0, interval mode */ |
||||
#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ |
||||
#define TM1_RUN 0x08 /* Timer 1 enable */ |
||||
#define TM1_TOGGLE 0x10 /* 0, interval mode */ |
||||
#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ |
||||
|
||||
|
||||
/*********************************/ |
||||
/* INTERRUPT SOURCES */ |
||||
/*********************************/ |
||||
#define INT_EXTINT0 0 |
||||
#define INT_EXTINT1 1 |
||||
#define INT_EXTINT2 2 |
||||
#define INT_EXTINT3 3 |
||||
#define INT_UARTTX0 4 |
||||
#define INT_UARTRX0 5 |
||||
#define INT_UARTTX1 6 |
||||
#define INT_UARTRX1 7 |
||||
#define INT_GDMA0 8 |
||||
#define INT_GDMA1 9 |
||||
#define INT_TIMER0 10 |
||||
#define INT_TIMER1 11 |
||||
#define INT_HDLCTXA 12 |
||||
#define INT_HDLCRXA 13 |
||||
#define INT_HDLCTXB 14 |
||||
#define INT_HDLCRXB 15 |
||||
#define INT_BDMATX 16 |
||||
#define INT_BDMARX 17 |
||||
#define INT_MACTX 18 |
||||
#define INT_MACRX 19 |
||||
#define INT_IIC 20 |
||||
#define INT_GLOBAL 21 |
||||
#define N_IRQS (21) |
||||
|
||||
#ifndef __ASSEMBLER__ |
||||
struct _irq_handler { |
||||
void *m_data; |
||||
void (*m_func)( void *data); |
||||
}; |
||||
|
||||
#endif |
||||
|
||||
#endif /* __S3C4510_h */ |
@ -1,231 +0,0 @@ |
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
* MODULE: $Id:$ |
||||
* Description: UART/Serial interface for Samsung S3C4510B SoC |
||||
* Runtime Env: ARM7TDMI |
||||
* Change History: |
||||
* 03-02-04 Create (Curt Brune) curt@cucy.com |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include <asm/hardware.h> |
||||
#include "s3c4510b_uart.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static UART *uart; |
||||
|
||||
/* flush serial input queue. returns 0 on success or negative error
|
||||
* number otherwise |
||||
*/ |
||||
static int serial_flush_input(void) |
||||
{ |
||||
volatile u32 tmp; |
||||
|
||||
/* keep on reading as long as the receiver is not empty */ |
||||
while( uart->m_stat.bf.rxReady) { |
||||
tmp = uart->m_rx; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/* flush output queue. returns 0 on success or negative error number
|
||||
* otherwise |
||||
*/ |
||||
static int serial_flush_output(void) |
||||
{ |
||||
/* wait until the transmitter is no longer busy */ |
||||
while( !uart->m_stat.bf.txBufEmpty); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
static void s3c4510b_serial_setbrg(void) |
||||
{ |
||||
UART_LINE_CTRL ulctrl; |
||||
UART_CTRL uctrl; |
||||
UART_BAUD_DIV ubd; |
||||
|
||||
serial_flush_output(); |
||||
serial_flush_input(); |
||||
|
||||
/* control register */ |
||||
uctrl.ui = 0x0; |
||||
uctrl.bf.rxMode = 0x1; |
||||
uctrl.bf.rxIrq = 0x0; |
||||
uctrl.bf.txMode = 0x1; |
||||
uctrl.bf.DSR = 0x0; |
||||
uctrl.bf.sendBreak = 0x0; |
||||
uctrl.bf.loopBack = 0x0; |
||||
uart->m_ctrl.ui = uctrl.ui; |
||||
|
||||
/* line control register */ |
||||
ulctrl.ui = 0x0; |
||||
ulctrl.bf.wordLen = 0x3; /* 8 bit data */ |
||||
ulctrl.bf.nStop = 0x0; /* 1 stop bit */ |
||||
ulctrl.bf.parity = 0x0; /* no parity */ |
||||
ulctrl.bf.clk = 0x0; /* internal clock */ |
||||
ulctrl.bf.infra_red = 0x0; /* no infra_red */ |
||||
uart->m_lineCtrl.ui = ulctrl.ui; |
||||
|
||||
ubd.ui = 0x0; |
||||
|
||||
/* see table on page 10-15 in SAMSUNG S3C4510B manual */ |
||||
/* get correct divisor */ |
||||
switch(gd->baudrate) { |
||||
case 1200: ubd.bf.cnt0 = 1301; break; |
||||
case 2400: ubd.bf.cnt0 = 650; break; |
||||
case 4800: ubd.bf.cnt0 = 324; break; |
||||
case 9600: ubd.bf.cnt0 = 162; break; |
||||
case 19200: ubd.bf.cnt0 = 80; break; |
||||
case 38400: ubd.bf.cnt0 = 40; break; |
||||
case 57600: ubd.bf.cnt0 = 26; break; |
||||
case 115200: ubd.bf.cnt0 = 13; break; |
||||
} |
||||
|
||||
uart->m_baudDiv.ui = ubd.ui; |
||||
uart->m_baudCnt = 0x0; |
||||
uart->m_baudClk = 0x0; |
||||
|
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
* |
||||
*/ |
||||
static int s3c4510b_serial_init(void) |
||||
{ |
||||
|
||||
#if CONFIG_SERIAL1 == 1 |
||||
uart = (UART *)UART0_BASE; |
||||
#elif CONFIG_SERIAL1 == 2 |
||||
uart = (UART *)UART1_BASE; |
||||
#else |
||||
#error CONFIG_SERIAL1 not equal to 1 or 2 |
||||
#endif |
||||
|
||||
serial_setbrg (); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
static void s3c4510_serial_putc(const char c) |
||||
{ |
||||
/* wait for room in the transmit FIFO */ |
||||
while( !uart->m_stat.bf.txBufEmpty); |
||||
|
||||
uart->m_tx = c; |
||||
|
||||
/*
|
||||
to be polite with serial console add a line feed |
||||
to the carriage return character |
||||
*/ |
||||
if (c=='\n') |
||||
serial_putc('\r'); |
||||
} |
||||
|
||||
/*
|
||||
* Test if an input byte is ready from the serial port. Returns non-zero on |
||||
* success, 0 otherwise. |
||||
*/ |
||||
static int s3c4510b_serial_tstc(void) |
||||
{ |
||||
return uart->m_stat.bf.rxReady; |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
static int s3c4510b_serial_getc(void) |
||||
{ |
||||
int rv; |
||||
|
||||
for(;;) { |
||||
rv = serial_tstc(); |
||||
|
||||
if (rv) { |
||||
return uart->m_rx & 0xFF; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static void s3c4510b_serial_puts(const char *s) |
||||
{ |
||||
default_serial_puts(s); |
||||
|
||||
/* busy wait for tx complete */ |
||||
while (!uart->m_stat.bf.txComplete); |
||||
|
||||
/* clear break */ |
||||
uart->m_ctrl.bf.sendBreak = 0; |
||||
|
||||
} |
||||
|
||||
static struct serial_device s3c4510b_serial_drv = { |
||||
.name = "s3c4510b_serial", |
||||
.start = s3c4510b_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = s3c4510b_serial_setbrg, |
||||
.putc = s3c4510b_serial_putc, |
||||
.puts = s3c4510b_serial_puts, |
||||
.getc = s3c4510b_serial_getc, |
||||
.tstc = s3c4510b_serial_tstc, |
||||
}; |
||||
|
||||
void s3c4510b_serial_initialize(void) |
||||
{ |
||||
serial_register(&s3c4510b_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &s3c4510b_serial_drv; |
||||
} |
@ -1,109 +0,0 @@ |
||||
#ifndef __UART_H |
||||
#define __UART_H |
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Description: S3C4510B UART register layout |
||||
*/ |
||||
|
||||
/* UART LINE CONTROL register */ |
||||
typedef struct __BF_UART_LINE_CTRL { |
||||
u32 wordLen: 2; |
||||
u32 nStop: 1; |
||||
u32 parity: 3; |
||||
u32 clk: 1; |
||||
u32 infra_red: 1; |
||||
u32 unused:24; |
||||
} BF_UART_LINE_CTRL; |
||||
|
||||
typedef union _UART_LINE_CTRL { |
||||
u32 ui; |
||||
BF_UART_LINE_CTRL bf; |
||||
} UART_LINE_CTRL; |
||||
|
||||
/* UART CONTROL register */ |
||||
typedef struct __BF_UART_CTRL { |
||||
u32 rxMode: 2; |
||||
u32 rxIrq: 1; |
||||
u32 txMode: 2; |
||||
u32 DSR: 1; |
||||
u32 sendBreak: 1; |
||||
u32 loopBack: 1; |
||||
u32 unused:24; |
||||
} BF_UART_CTRL; |
||||
|
||||
typedef union _UART_CTRL { |
||||
u32 ui; |
||||
BF_UART_CTRL bf; |
||||
} UART_CTRL; |
||||
|
||||
/* UART STATUS register */ |
||||
typedef struct __BF_UART_STAT { |
||||
u32 overrun: 1; |
||||
u32 parity: 1; |
||||
u32 frame: 1; |
||||
u32 breakIrq: 1; |
||||
u32 DTR: 1; |
||||
u32 rxReady: 1; |
||||
u32 txBufEmpty: 1; |
||||
u32 txComplete: 1; |
||||
u32 unused:24; |
||||
} BF_UART_STAT; |
||||
|
||||
typedef union _UART_STAT { |
||||
u32 ui; |
||||
BF_UART_STAT bf; |
||||
} UART_STAT; |
||||
|
||||
/* UART BAUD_DIV register */ |
||||
typedef struct __BF_UART_BAUD_DIV { |
||||
u32 cnt1: 4; |
||||
u32 cnt0:12; |
||||
u32 unused:16; |
||||
} BF_UART_BAUD_DIV; |
||||
|
||||
typedef union _UART_BAUD_DIV { |
||||
u32 ui; |
||||
BF_UART_BAUD_DIV bf; |
||||
} UART_BAUD_DIV; |
||||
|
||||
/* UART register block */ |
||||
typedef struct __UART { |
||||
volatile UART_LINE_CTRL m_lineCtrl; |
||||
volatile UART_CTRL m_ctrl; |
||||
volatile UART_STAT m_stat; |
||||
volatile u32 m_tx; |
||||
volatile u32 m_rx; |
||||
volatile UART_BAUD_DIV m_baudDiv; |
||||
volatile u32 m_baudCnt; |
||||
volatile u32 m_baudClk; |
||||
} UART; |
||||
|
||||
#define NL 0x0A |
||||
#define CR 0x0D |
||||
#define BSP 0x08 |
||||
#define ESC 0x1B |
||||
#define CTRLZ 0x1A |
||||
#define RUBOUT 0x7F |
||||
|
||||
#endif |
Loading…
Reference in new issue