This was obtained from Linux 3.12 commit 5e01dc7b26. Signed-off-by: Simon Glass <sjg@chromium.org>master
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SPI (Serial Peripheral Interface) busses |
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SPI busses can be described with a node for the SPI master device |
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and a set of child nodes for each SPI slave on the bus. For this |
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discussion, it is assumed that the system's SPI controller is in |
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SPI master mode. This binding does not describe SPI controllers |
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in slave mode. |
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The SPI master node requires the following properties: |
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- #address-cells - number of cells required to define a chip select |
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address on the SPI bus. |
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- #size-cells - should be zero. |
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- compatible - name of SPI bus controller following generic names |
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recommended practice. |
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- cs-gpios - (optional) gpios chip select. |
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No other properties are required in the SPI bus node. It is assumed |
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that a driver for an SPI bus device will understand that it is an SPI bus. |
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However, the binding does not attempt to define the specific method for |
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assigning chip select numbers. Since SPI chip select configuration is |
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flexible and non-standardized, it is left out of this binding with the |
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assumption that board specific platform code will be used to manage |
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chip selects. Individual drivers can define additional properties to |
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support describing the chip select layout. |
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Optional property: |
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- num-cs : total number of chipselects |
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If cs-gpios is used the number of chip select will automatically increased |
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with max(cs-gpios > hw cs) |
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So if for example the controller has 2 CS lines, and the cs-gpios |
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property looks like this: |
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cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; |
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Then it should be configured so that num_chipselect = 4 with the |
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following mapping: |
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cs0 : &gpio1 0 0 |
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cs1 : native |
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cs2 : &gpio1 1 0 |
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cs3 : &gpio1 2 0 |
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SPI slave nodes must be children of the SPI master node and can |
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contain the following properties. |
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- reg - (required) chip select address of device. |
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- compatible - (required) name of SPI device following generic names |
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recommended practice |
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- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz |
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- spi-cpol - (optional) Empty property indicating device requires |
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inverse clock polarity (CPOL) mode |
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- spi-cpha - (optional) Empty property indicating device requires |
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shifted clock phase (CPHA) mode |
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- spi-cs-high - (optional) Empty property indicating device requires |
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chip select active high |
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- spi-3wire - (optional) Empty property indicating device requires |
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3-wire mode. |
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- spi-tx-bus-width - (optional) The bus width(number of data wires) that |
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used for MOSI. Defaults to 1 if not present. |
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- spi-rx-bus-width - (optional) The bus width(number of data wires) that |
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used for MISO. Defaults to 1 if not present. |
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Some SPI controllers and devices support Dual and Quad SPI transfer mode. |
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It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD). |
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Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is |
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only 1(SINGLE), 2(DUAL) and 4(QUAD). |
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Dual/Quad mode is not allowed when 3-wire mode is used. |
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If a gpio chipselect is used for the SPI slave the gpio number will be passed |
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via the cs_gpio |
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SPI example for an MPC5200 SPI bus: |
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spi@f00 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
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reg = <0xf00 0x20>; |
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interrupts = <2 13 0 2 14 0>; |
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interrupt-parent = <&mpc5200_pic>; |
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ethernet-switch@0 { |
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compatible = "micrel,ks8995m"; |
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spi-max-frequency = <1000000>; |
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reg = <0>; |
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}; |
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codec@1 { |
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compatible = "ti,tlv320aic26"; |
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spi-max-frequency = <100000>; |
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reg = <1>; |
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}; |
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}; |
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