Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini
10 years ago
commit
b1f7ecc9b5
@ -0,0 +1,280 @@ |
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/* |
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* Copyright (C) 2015 - Chen-Yu Tsai |
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* Author: Chen-Yu Tsai <wens@csie.org>
|
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* |
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* Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
|
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* |
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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#include <config.h> |
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#include <asm/gic.h> |
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#include <asm/macro.h> |
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#include <asm/psci.h> |
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#include <asm/arch/cpu.h> |
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|
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/* |
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* Memory layout: |
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* |
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* SECURE_RAM to text_end : |
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* ._secure_text section
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* text_end to ALIGN_PAGE(text_end): |
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* nothing |
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) |
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* 1kB of stack per CPU (4 CPUs max). |
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*/ |
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|
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.pushsection ._secure.text, "ax" |
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.arch_extension sec
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#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) |
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#define TEN_MS (10 * ONE_MS) |
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#define GICD_BASE 0x1c81000 |
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#define GICC_BASE 0x1c82000 |
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|
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.macro timer_wait reg, ticks |
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@ Program CNTP_TVAL
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movw \reg, #(\ticks & 0xffff) |
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movt \reg, #(\ticks >> 16) |
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mcr p15, 0, \reg, c14, c2, 0 |
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isb |
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@ Enable physical timer, mask interrupt
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mov \reg, #3 |
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mcr p15, 0, \reg, c14, c2, 1 |
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@ Poll physical timer until ISTATUS is on
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1: isb |
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mrc p15, 0, \reg, c14, c2, 1 |
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ands \reg, \reg, #4 |
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bne 1b |
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@ Disable timer
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mov \reg, #0 |
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mcr p15, 0, \reg, c14, c2, 1 |
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isb |
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.endm |
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|
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.globl psci_fiq_enter
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psci_fiq_enter: |
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push {r0-r12} |
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|
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@ Switch to secure
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mrc p15, 0, r7, c1, c1, 0 |
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bic r8, r7, #1 |
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mcr p15, 0, r8, c1, c1, 0 |
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isb |
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@ Validate reason based on IAR and acknowledge
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movw r8, #(GICC_BASE & 0xffff) |
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movt r8, #(GICC_BASE >> 16) |
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ldr r9, [r8, #GICC_IAR] |
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movw r10, #0x3ff |
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movt r10, #0 |
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cmp r9, r10 @ skip spurious interrupt 1023
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beq out |
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movw r10, #0x3fe @ ...and 1022
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cmp r9, r10 |
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beq out |
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str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt |
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dsb |
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@ Compute CPU number
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lsr r9, r9, #10 |
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and r9, r9, #0xf |
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff) |
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movt r8, #(SUN6I_CPUCFG_BASE >> 16) |
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@ Wait for the core to enter WFI
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lsl r11, r9, #6 @ x64
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add r11, r11, r8 |
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1: ldr r10, [r11, #0x48] |
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tst r10, #(1 << 2) |
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bne 2f |
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timer_wait r10, ONE_MS |
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b 1b |
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@ Reset CPU
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2: mov r10, #0 |
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str r10, [r11, #0x40] |
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@ Lock CPU
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mov r10, #1 |
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lsl r11, r10, r9 @ r11 is now CPU mask
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ldr r10, [r8, #0x1e4] |
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bic r10, r10, r11 |
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str r10, [r8, #0x1e4] |
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movw r8, #(SUNXI_PRCM_BASE & 0xffff) |
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movt r8, #(SUNXI_PRCM_BASE >> 16) |
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@ Set power gating
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ldr r10, [r8, #0x100] |
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orr r10, r10, r11 |
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str r10, [r8, #0x100] |
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timer_wait r10, ONE_MS |
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#ifdef CONFIG_MACH_SUN6I |
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@ Activate power clamp
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lsl r12, r9, #2 @ x4
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add r12, r12, r8 |
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mov r10, #0xff |
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str r10, [r12, #0x140] |
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#endif |
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff) |
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movt r8, #(SUN6I_CPUCFG_BASE >> 16) |
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@ Unlock CPU
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ldr r10, [r8, #0x1e4] |
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orr r10, r10, r11 |
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str r10, [r8, #0x1e4] |
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@ Restore security level
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out: mcr p15, 0, r7, c1, c1, 0 |
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pop {r0-r12} |
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subs pc, lr, #4 |
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on: |
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push {lr} |
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mov r0, r1 |
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bl psci_get_cpu_stack_top @ get stack top of target CPU
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str r2, [r0] @ store target PC at stack top
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dsb |
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) |
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movt r0, #(SUN6I_CPUCFG_BASE >> 16) |
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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mov r4, #1 |
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lsl r4, r4, r1 |
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ldr r6, =psci_cpu_entry |
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str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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@ Assert reset on target CPU
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mov r6, #0 |
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5] @ Reset CPU
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@ l1 invalidate
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ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
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bic r6, r6, r4 |
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str r6, [r0, #0x184] |
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@ Lock CPU (Disable external debug access)
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ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
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bic r6, r6, r4 |
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str r6, [r0, #0x1e4] |
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movw r0, #(SUNXI_PRCM_BASE & 0xffff) |
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movt r0, #(SUNXI_PRCM_BASE >> 16) |
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#ifdef CONFIG_MACH_SUN6I |
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@ Release power clamp
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lsl r5, r1, #2 @ 1 register per CPU
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add r5, r5, r0 @ PRCM
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movw r6, #0x1ff |
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movt r6, #0 |
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1: lsrs r6, r6, #1 |
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str r6, [r5, #0x140] @ CPUx_PWR_CLAMP
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bne 1b |
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#endif |
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timer_wait r6, TEN_MS |
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@ Clear power gating
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ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING
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bic r6, r6, r4 |
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str r6, [r0, #0x100] |
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@ re-calculate CPU control register address
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) |
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movt r0, #(SUN6I_CPUCFG_BASE >> 16) |
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@ Deassert reset on target CPU
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mov r6, #3 |
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5] |
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@ Unlock CPU (Enable external debug access)
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ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
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orr r6, r6, r4 |
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str r6, [r0, #0x1e4] |
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS |
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pop {pc} |
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.globl psci_cpu_off
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psci_cpu_off: |
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bl psci_cpu_off_common |
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@ Ask CPU0 to pull the rug...
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movw r0, #(GICD_BASE & 0xffff) |
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movt r0, #(GICD_BASE >> 16) |
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movw r1, #15 @ SGI15
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movt r1, #1 @ Target is CPU0
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str r1, [r0, #GICD_SGIR] |
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dsb |
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1: wfi |
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b 1b |
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.globl psci_arch_init
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psci_arch_init: |
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mov r6, lr |
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movw r4, #(GICD_BASE & 0xffff) |
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movt r4, #(GICD_BASE >> 16) |
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ldr r5, [r4, #GICD_IGROUPRn] |
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bic r5, r5, #(1 << 15) @ SGI15 as Group-0
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str r5, [r4, #GICD_IGROUPRn] |
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mov r5, #0 @ Set SGI15 priority to 0
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strb r5, [r4, #(GICD_IPRIORITYRn + 15)] |
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add r4, r4, #0x1000 @ GICC address
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mov r5, #0xff |
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str r5, [r4, #GICC_PMR] @ Be cool with non-secure |
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ldr r5, [r4, #GICC_CTLR] |
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orr r5, r5, #(1 << 3) @ Switch FIQEn on
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str r5, [r4, #GICC_CTLR] |
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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orr r5, r5, #4 @ Enable FIQ in monitor mode
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb |
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bl psci_get_cpu_id @ CPU ID => r0
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bl psci_get_cpu_stack_top @ stack top => r0
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mov sp, r0 |
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bx r6 |
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.globl psci_text_end
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psci_text_end: |
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.popsection |
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@ -0,0 +1,16 @@ |
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/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SUNXI_DMA_H |
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#define _SUNXI_DMA_H |
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) |
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#include <asm/arch/dma_sun4i.h> |
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#else |
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#error "DMA definition not available for this architecture" |
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#endif |
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#endif /* _SUNXI_DMA_H */ |
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@ -0,0 +1,68 @@ |
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/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SUNXI_DMA_SUN4I_H |
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#define _SUNXI_DMA_SUN4I_H |
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struct sunxi_dma_cfg |
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{ |
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u32 ctl; /* 0x00 Control */ |
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u32 src_addr; /* 0x04 Source address */ |
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u32 dst_addr; /* 0x08 Destination address */ |
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u32 bc; /* 0x0C Byte counter */ |
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u32 res0[2]; |
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u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ |
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u32 res1; |
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}; |
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struct sunxi_dma |
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{ |
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u32 irq_en; /* 0x000 IRQ enable */ |
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u32 irq_pend; /* 0x004 IRQ pending */ |
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u32 auto_gate; /* 0x008 auto gating */ |
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u32 res0[61]; |
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struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ |
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u32 res1[64]; |
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struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ |
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}; |
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enum ddma_drq_type { |
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DDMA_DST_DRQ_SRAM = 0, |
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DDMA_SRC_DRQ_SRAM = 0, |
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DDMA_DST_DRQ_SDRAM = 1, |
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DDMA_SRC_DRQ_SDRAM = 1, |
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DDMA_DST_DRQ_PATA = 2, |
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DDMA_SRC_DRQ_PATA = 2, |
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DDMA_DST_DRQ_NAND = 3, |
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DDMA_SRC_DRQ_NAND = 3, |
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DDMA_DST_DRQ_USB0 = 4, |
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DDMA_SRC_DRQ_USB0 = 4, |
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DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, |
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DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, |
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DDMA_DST_DRQ_SPI1_TX = 8, |
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DDMA_SRC_DRQ_SPI1_RX = 9, |
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DDMA_DST_DRQ_SECURITY_SYS_TX = 10, |
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DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, |
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DDMA_DST_DRQ_TCON0 = 14, |
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DDMA_DST_DRQ_TCON1 = 15, |
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DDMA_DST_DRQ_MSC = 23, |
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DDMA_SRC_DRQ_MSC = 23, |
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DDMA_DST_DRQ_SPI0_TX = 26, |
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DDMA_SRC_DRQ_SPI0_RX = 27, |
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DDMA_DST_DRQ_SPI2_TX = 28, |
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DDMA_SRC_DRQ_SPI2_RX = 29, |
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DDMA_DST_DRQ_SPI3_TX = 30, |
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DDMA_SRC_DRQ_SPI3_RX = 31, |
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}; |
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#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) |
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#define SUNXI_DMA_CTL_MODE_IO (1 << 5) |
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#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) |
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#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) |
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#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) |
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#define SUNXI_DMA_CTL_TRIGGER (1 << 31) |
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#endif /* _SUNXI_DMA_SUN4I_H */ |
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@ -0,0 +1,67 @@ |
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/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SUNXI_NAND_H |
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#define _SUNXI_NAND_H |
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|
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#include <linux/types.h> |
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|
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struct sunxi_nand |
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{ |
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u32 ctl; /* 0x000 Configure and control */ |
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u32 st; /* 0x004 Status information */ |
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u32 intr; /* 0x008 Interrupt control */ |
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u32 timing_ctl; /* 0x00C Timing control */ |
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u32 timing_cfg; /* 0x010 Timing configure */ |
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u32 addr_low; /* 0x014 Low word address */ |
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u32 addr_high; /* 0x018 High word address */ |
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u32 block_num; /* 0x01C Data block number */ |
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u32 data_cnt; /* 0x020 Data counter for transfer */ |
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u32 cmd; /* 0x024 NDFC commands */ |
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u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */ |
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u32 wcmd_set; /* 0x02C Write command set */ |
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u32 io_data; /* 0x030 IO data */ |
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u32 ecc_ctl; /* 0x034 ECC configure and control */ |
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u32 ecc_st; /* 0x038 ECC status and operation info */ |
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u32 efr; /* 0x03C Enhanced feature */ |
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u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */ |
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u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */ |
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u32 user_data[16]; /* 0x050[16] User data field */ |
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u32 efnand_st; /* 0x090 EFNAND status */ |
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u32 res0[3]; |
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u32 spare_area; /* 0x0A0 Spare area configure */ |
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u32 pat_id; /* 0x0A4 Pattern ID register */ |
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u32 rdata_sta_ctl; /* 0x0A8 Read data status control */ |
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u32 rdata_sta_0; /* 0x0AC Read data status 0 */ |
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u32 rdata_sta_1; /* 0x0B0 Read data status 1 */ |
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u32 res1[3]; |
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u32 mdma_addr; /* 0x0C0 MBUS DMA Address */ |
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u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */ |
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}; |
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|
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#define SUNXI_NAND_CTL_EN (1 << 0) |
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#define SUNXI_NAND_CTL_RST (1 << 1) |
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#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8) |
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#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14) |
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|
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#define SUNXI_NAND_ST_CMD_INT (1 << 1) |
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#define SUNXI_NAND_ST_DMA_INT (1 << 2) |
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#define SUNXI_NAND_ST_FIFO_FULL (1 << 3) |
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|
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#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16); |
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#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22) |
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#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23) |
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#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0 |
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#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25) |
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|
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#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0) |
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#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3) |
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#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5) |
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#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9) |
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#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12) |
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#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16) |
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|
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#endif /* _SUNXI_NAND_H */ |
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@ -0,0 +1,11 @@ |
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CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" |
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CONFIG_VIDEO=n |
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CONFIG_USB_KEYBOARD=n |
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CONFIG_MMC0_CD_PIN="PH18" |
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CONFIG_ARM=y |
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CONFIG_ARCH_SUNXI=y |
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CONFIG_MACH_SUN9I=y |
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# these are unused atm but we must set them to something |
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CONFIG_DRAM_CLK=360 |
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CONFIG_DRAM_ZQ=123 |
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CONFIG_SYS_CLK_FREQ=1008000000 |
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@ -0,0 +1,273 @@ |
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/*
|
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* Copyright (c) 2014, Antmicro Ltd <www.antmicro.com> |
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* Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu> |
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* Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* \todo Detect chip parameters (page size, ECC mode, randomisation...) |
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*/ |
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|
||||
#include <common.h> |
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#include <config.h> |
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#include <asm/io.h> |
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#include <nand.h> |
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#include <asm/arch/cpu.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/dma.h> |
||||
#include <asm/arch/nand.h> |
||||
|
||||
void |
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nand_init(void) |
||||
{ |
||||
struct sunxi_ccm_reg * const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE; |
||||
u32 val; |
||||
|
||||
board_nand_init(); |
||||
|
||||
/* "un-gate" NAND clock and clock source
|
||||
* This assumes that the clock was already correctly configured by |
||||
* BootROM */ |
||||
setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); |
||||
#ifdef CONFIG_MACH_SUN9I |
||||
setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); |
||||
#else |
||||
setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); |
||||
#endif |
||||
setbits_le32(&ccm->nand0_clk_cfg, 0x80000000); |
||||
|
||||
val = readl(&nand->ctl); |
||||
val |= SUNXI_NAND_CTL_RST; |
||||
writel(val, &nand->ctl); |
||||
|
||||
/* Wait until reset pin is deasserted */ |
||||
do { |
||||
val = readl(&nand->ctl); |
||||
if (!(val & SUNXI_NAND_CTL_RST)) |
||||
break; |
||||
} while (1); |
||||
|
||||
/** \todo Chip select, currently kind of static */ |
||||
val = readl(&nand->ctl); |
||||
val &= 0xf0fff0f2; |
||||
val |= SUNXI_NAND_CTL_EN; |
||||
val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE); |
||||
writel(val, &nand->ctl); |
||||
|
||||
writel(0x100, &nand->timing_ctl); |
||||
writel(0x7ff, &nand->timing_cfg); |
||||
|
||||
/* reset CMD */ |
||||
val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG | |
||||
NAND_CMD_RESET; |
||||
writel(val, &nand->cmd); |
||||
do { |
||||
val = readl(&nand->st); |
||||
if (val & (1<<1)) |
||||
break; |
||||
udelay(1000); |
||||
} while (1); |
||||
|
||||
printf("Nand initialised\n"); |
||||
} |
||||
|
||||
int |
||||
nand_wait_timeout(u32 *reg, u32 mask, u32 val) |
||||
{ |
||||
unsigned long tmo = timer_get_us() + 1000000; /* 1s */ |
||||
|
||||
while ((readl(reg) & mask) != val) { |
||||
if (timer_get_us() > tmo) |
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* random seed */ |
||||
static const uint16_t random_seed[128] = { |
||||
0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72, |
||||
0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436, |
||||
0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d, |
||||
0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130, |
||||
0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56, |
||||
0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55, |
||||
0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb, |
||||
0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17, |
||||
0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62, |
||||
0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064, |
||||
0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126, |
||||
0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e, |
||||
0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3, |
||||
0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b, |
||||
0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d, |
||||
0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db, |
||||
}; |
||||
|
||||
uint32_t ecc_errors = 0; |
||||
|
||||
static void |
||||
nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome) |
||||
{ |
||||
static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64}; |
||||
int i; |
||||
uint32_t ecc_mode; |
||||
u32 ecc; |
||||
u16 seed = 0; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(strength); i++) { |
||||
if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) { |
||||
ecc_mode = i; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (i == ARRAY_SIZE(strength)) { |
||||
printf("ECC strength unsupported\n"); |
||||
return; |
||||
} |
||||
|
||||
ecc = SUNXI_NAND_ECC_CTL_ECC_EN | |
||||
SUNXI_NAND_ECC_CTL_PIPELINE | |
||||
SUNXI_NAND_ECC_CTL_RND_EN | |
||||
SUNXI_NAND_ECC_CTL_MODE(ecc_mode); |
||||
|
||||
if (CONFIG_NAND_SUNXI_ECC_STEP == 512) |
||||
ecc |= SUNXI_NAND_ECC_CTL_BS_512B; |
||||
|
||||
if (syndrome) |
||||
seed = 0x4A80; |
||||
else |
||||
seed = random_seed[page % ARRAY_SIZE(random_seed)]; |
||||
|
||||
ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed); |
||||
|
||||
writel(ecc, &nand->ecc_ctl); |
||||
} |
||||
|
||||
/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */ |
||||
void |
||||
nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst, |
||||
int syndrome) |
||||
{ |
||||
struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE; |
||||
struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0]; |
||||
|
||||
uint32_t shift; |
||||
uint32_t page; |
||||
uint32_t addr; |
||||
uint32_t oob_offset; |
||||
uint32_t ecc_bytes; |
||||
u32 val; |
||||
u32 cmd; |
||||
|
||||
page = src / CONFIG_NAND_SUNXI_PAGE_SIZE; |
||||
if (page > 0xFFFF) { |
||||
/* TODO: currently this is not supported */ |
||||
printf("Reading from address >= %08X is not allowed.\n", |
||||
0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE); |
||||
return; |
||||
} |
||||
|
||||
shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE; |
||||
writel(0, &nand->ecc_st); |
||||
|
||||
/* ECC_CTL, randomization */ |
||||
ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH * |
||||
fls(CONFIG_NAND_SUNXI_ECC_STEP * 8); |
||||
ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8); |
||||
ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */ |
||||
ecc_bytes += 4; |
||||
|
||||
nand_config_ecc(nand, page, syndrome); |
||||
if (syndrome) { |
||||
/* shift every 1kB in syndrome */ |
||||
shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes; |
||||
oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift; |
||||
} else { |
||||
oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE + |
||||
(shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes; |
||||
} |
||||
|
||||
addr = (page << 16) | shift; |
||||
|
||||
/* DMA */ |
||||
val = readl(&nand->ctl); |
||||
writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl); |
||||
|
||||
writel(oob_offset, &nand->spare_area); |
||||
|
||||
/* DMAC
|
||||
* \todo Separate this into a tidy driver */ |
||||
writel(0x0, &dma->irq_en); /* clear dma interrupts */ |
||||
writel((uint32_t) &nand->io_data , &dma_cfg->src_addr); |
||||
writel(dst , &dma_cfg->dst_addr); |
||||
writel(0x00007F0F , &dma_cfg->ddma_para); |
||||
writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc); |
||||
|
||||
val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) | |
||||
SUNXI_DMA_CTL_MODE_IO | |
||||
SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 | |
||||
SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) | |
||||
SUNXI_DMA_CTL_DST_DATA_WIDTH_32 | |
||||
SUNXI_DMA_CTL_TRIGGER; |
||||
writel(val, &dma_cfg->ctl); |
||||
|
||||
writel(0x00E00530, &nand->rcmd_set); |
||||
nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0); |
||||
|
||||
writel(1 , &nand->block_num); |
||||
writel(addr, &nand->addr_low); |
||||
writel(0 , &nand->addr_high); |
||||
|
||||
/* CMD (PAGE READ) */ |
||||
cmd = 0x85E80000; |
||||
cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES); |
||||
cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ : |
||||
SUNXI_NAND_CMD_ORDER_INTERLEAVE); |
||||
writel(cmd, &nand->cmd); |
||||
|
||||
if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT, |
||||
SUNXI_NAND_ST_DMA_INT)) { |
||||
printf("NAND timeout reading data\n"); |
||||
return; |
||||
} |
||||
|
||||
if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) { |
||||
printf("NAND timeout reading data\n"); |
||||
return; |
||||
} |
||||
|
||||
if (readl(&nand->ecc_st)) |
||||
ecc_errors++; |
||||
} |
||||
|
||||
int |
||||
nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) |
||||
{ |
||||
struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE; |
||||
dma_addr_t dst_block; |
||||
dma_addr_t dst_end; |
||||
phys_addr_t addr = offs; |
||||
|
||||
dst_end = ((dma_addr_t) dest) + size; |
||||
|
||||
memset((void *)dest, 0x0, size); |
||||
ecc_errors = 0; |
||||
for (dst_block = (dma_addr_t) dest; dst_block < dst_end; |
||||
dst_block += CONFIG_NAND_SUNXI_ECC_STEP, |
||||
addr += CONFIG_NAND_SUNXI_ECC_STEP) { |
||||
/* syndrome read first 4MiB to match Allwinner BootROM */ |
||||
nand_read_block(nand, addr, dst_block, addr < 0x400000); |
||||
} |
||||
|
||||
if (ecc_errors) |
||||
printf("Error: %d ECC failures detected\n", ecc_errors); |
||||
return ecc_errors == 0; |
||||
} |
||||
|
||||
void |
||||
nand_deselect(void) |
||||
{} |
||||
@ -0,0 +1,21 @@ |
||||
/*
|
||||
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> |
||||
* |
||||
* Configuration settings for the Allwinner A80 (sun9i) CPU |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* A80 specific configuration |
||||
*/ |
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are |
||||
*/ |
||||
#include <configs/sunxi-common.h> |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue