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@ -1,5 +1,5 @@ |
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/*
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* Copyright (C) 2017 Armadeus Systems |
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* Copyright (C) 2018 Armadeus Systems |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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@ -9,15 +9,12 @@ |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/mx6ul_pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/mach-imx/iomux-v3.h> |
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#include <asm/io.h> |
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#include <common.h> |
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#include <environment.h> |
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#include <fsl_esdhc.h> |
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#include <mmc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -138,12 +135,6 @@ int board_late_init(void) |
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return opos6ul_board_late_init(); |
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} |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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return cfg->esdhc_base == USDHC1_BASE_ADDR; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = imx_ddr_size(); |
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@ -153,32 +144,9 @@ int dram_init(void) |
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#ifdef CONFIG_SPL_BUILD |
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#include <asm/arch/mx6-ddr.h> |
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#include <asm/arch/opos6ul.h> |
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#include <linux/libfdt.h> |
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#include <spl.h> |
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#define USDHC_PAD_CTRL ( \ |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
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) |
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struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC1_BASE_ADDR, 0, 8}, |
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}; |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
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.grp_addds = 0x00000030, |
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.grp_ddrmode_ctl = 0x00020000, |
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@ -240,11 +208,14 @@ static struct mx6_ddr3_cfg mem_ddr = { |
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.trasmin = 3750, |
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}; |
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int board_mmc_init(bd_t *bis) |
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void board_boot_order(u32 *spl_boot_list) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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unsigned int bmode = readl(&src_base->sbmr2); |
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if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */ |
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spl_boot_list[0] = BOOT_DEVICE_UART; |
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else |
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spl_boot_list[0] = spl_boot_device(); |
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} |
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static void ccgr_init(void) |
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@ -282,6 +253,11 @@ static void spl_dram_init(void) |
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
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} |
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void spl_board_init(void) |
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{ |
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preloader_console_init(); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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ccgr_init(); |
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@ -292,10 +268,6 @@ void board_init_f(ulong dummy) |
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/* setup GP timer */ |
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timer_init(); |
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/* UART clocks enabled and gd valid - init serial console */ |
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opos6ul_setup_uart_debug(); |
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preloader_console_init(); |
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/* DDR initialization */ |
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spl_dram_init(); |
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} |
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Tom Rini
6 years ago