From 536c5c7a331d417d416dc04271b6f146db41cab0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:26:59 -0700 Subject: [PATCH 01/15] imx: imx6sx-sdb: Enable DM QSPI driver To support DM QSPI driver - Add spi0 and spi1 alias for qspi1 and qspi2. - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI/QSPI relavent configurations - Remove iomux settings of qspi2 in board codes which is not needed for DM driver. - Add sf default settings. So running "sf probe" can detect the flash Signed-off-by: Ye Li --- arch/arm/dts/imx6sx-sdb-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/imx6sx.dtsi | 12 +++++++----- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 ------------------------- configs/mx6sxsabresd_defconfig | 7 +++++++ include/configs/mx6sxsabresd.h | 4 ++++ 5 files changed, 34 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/imx6sx-sdb-u-boot.dtsi diff --git a/arch/arm/dts/imx6sx-sdb-u-boot.dtsi b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi new file mode 100644 index 0000000..8e592cd --- /dev/null +++ b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi2 { + num-cs = <2>; + + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; + + flash1: n25q256a@1 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 1a473e8..8ccf264 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -40,11 +40,13 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; + spi0 = &qspi1; + spi1 = &qspi2; + spi2 = &ecspi1; + spi3 = &ecspi2; + spi4 = &ecspi3; + spi5 = &ecspi4; + spi6 = &ecspi5; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index d56e235..3e10c7f 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -205,33 +205,8 @@ int board_mmc_get_env_dev(int devno) #ifdef CONFIG_FSL_QSPI -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); - /* Set the clock */ enable_qspi_clk(1); diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index dcac6f4..4c235c1 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y @@ -37,8 +38,14 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_QSPI=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index dc4181d..2a7eb22 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -184,6 +184,10 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif #define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif #ifndef CONFIG_SPL_BUILD From 0925ee21851287d48279bb43e4a0876b2005a5f2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:27:00 -0700 Subject: [PATCH 02/15] imx: imx6sx-sabreauto: convert to use DM QSPI driver To support DM QSPI driver: - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI and DM SPI FLASH configurations - Remove iomux settings of qspi1 in board codes which is not needed for DM driver. Signed-off-by: Ye Li --- arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 16 ++++++++++ arch/arm/dts/imx6sx-sabreauto.dts | 40 +++++++++++++++++++++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 24 --------------- configs/mx6sxsabreauto_defconfig | 2 ++ 4 files changed, 58 insertions(+), 24 deletions(-) create mode 100644 arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi new file mode 100644 index 0000000..f5c68d7 --- /dev/null +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi1 { + num-cs = <2>; + + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; + + flash1: n25q256a@1 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts index a4c2627..9643d1f 100644 --- a/arch/arm/dts/imx6sx-sabreauto.dts +++ b/arch/arm/dts/imx6sx-sabreauto.dts @@ -96,6 +96,29 @@ }; }; +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + &iomuxc { imx6x-sabreauto { pinctrl_i2c2_1: i2c2grp-1 { @@ -112,6 +135,23 @@ >; }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 975af2c..6e606da 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -218,32 +218,8 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_QSPI - -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); - /* Set the clock */ enable_qspi_clk(0); diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 359b9b6..0e15bd6 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -36,6 +36,8 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y From 3b82335015cc695b760c90f904ea85bae53c0597 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:30:53 -0700 Subject: [PATCH 03/15] imx: imx7d-sdb: Add DM QSPI support On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default). To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399 populate R392-R395, R299, R300). So we add new DTS file and new defconfig dedicated for QSPI. Other changes to support the DM QSPI: - Add QSPI node and alias spi0. - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req conflict - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to align with kernel and also present the conflict. - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to "spi-flash" - Remove iomux settings of qspi in board codes which is not needed for DM driver. Signed-off-by: Ye Li --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi | 10 ++++ arch/arm/dts/imx7d-sdb-qspi.dts | 44 ++++++++++++++++ arch/arm/dts/imx7d-sdb.dts | 6 ++- arch/arm/dts/imx7d.dtsi | 12 +++++ arch/arm/dts/imx7s.dtsi | 22 ++++++-- board/freescale/mx7dsabresd/mx7dsabresd.c | 16 ------ configs/mx7dsabresd_qspi_defconfig | 83 +++++++++++++++++++++++++++++++ include/configs/mx7dsabresd.h | 4 +- 9 files changed, 175 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi create mode 100644 arch/arm/dts/imx7d-sdb-qspi.dts create mode 100644 configs/mx7dsabresd_qspi_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa227..68e5c4f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -445,7 +445,8 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ - imx7d-sdb.dtb + imx7d-sdb.dtb \ + imx7d-sdb-qspi.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --git a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi new file mode 100644 index 0000000..2ce6961 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi1 { + flash0: mx25l51245g@0 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts new file mode 100644 index 0000000..9bb4c74 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include "imx7d-sdb.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l51245g"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index bafcc79..76aa69a 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -11,11 +11,15 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + aliases { + spi5 = &soft_spi; + }; + memory { reg = <0x80000000 0x80000000>; }; - spi4 { + soft_spi: soft-spi { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index f6dee41..30b0589 100644 --- a/arch/arm/dts/imx7d.dtsi +++ b/arch/arm/dts/imx7d.dtsi @@ -86,6 +86,18 @@ }; }; +&aips2 { + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; +}; + &aips3 { usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 4d42335..5067b9f 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -82,10 +82,11 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; + spi0 = &qspi1; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; }; cpus { @@ -1072,6 +1073,19 @@ status = "disabled"; }; + qspi1: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + sdma: sdma@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 90e2d1a..191b59a 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -36,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) -#define QSPI_PAD_CTRL \ - (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) #define SPI_PAD_CTRL \ @@ -278,21 +275,8 @@ int board_phy_config(struct phy_device *phydev) #endif #ifdef CONFIG_FSL_QSPI -static iomux_v3_cfg_t const quadspi_pads[] = { - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), -}; - int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); - /* Set the clock */ set_clk_qspi(); diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig new file mode 100644 index 0000000..a798804 --- /dev/null +++ b/configs/mx7dsabresd_qspi_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +# CONFIG_CMD_BMODE is not set +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_QSPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 11fcc9f..87241ef 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -225,9 +225,7 @@ #endif #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 From 9e1e6f6fe8d4fab523c7b211a7377167dbdcb707 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 20:23:15 -0700 Subject: [PATCH 04/15] dts: imx6ul: Update alias to support DM Add spi0 alias for qspi for enabling DM SPI. Change usb alias for usbotg1 and usbotg2 for enabling DM USB Signed-off-by: Ye Li --- arch/arm/dts/imx6ul.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index b33e624..71b42d4 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -39,14 +39,15 @@ sai1 = &sai1; sai2 = &sai2; sai3 = &sai3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbotg0 = &usbotg1; - usbotg1 = &usbotg2; + spi0 = &qspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { From 25baafc44c460da6f676a550fe477e8040bd575d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 20:23:16 -0700 Subject: [PATCH 05/15] dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary for converting to use u-boot DM driver. Two -u-boot.dtsi are added to modify compatible string of SPI flash device to "spi-flash". Signed-off-by: Ye Li --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 10 + arch/arm/dts/imx6ul-14x14-evk.dts | 427 +++++++++++++++++++++++++++ arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi | 10 + arch/arm/dts/imx6ul-9x9-evk.dts | 471 ++++++++++++++++++++++++++++++ 5 files changed, 921 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dts create mode 100644 arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-9x9-evk.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 68e5c4f..31d9256 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -440,7 +440,9 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ - imx6ul-opos6uldev.dtb + imx6ul-opos6uldev.dtb \ + imx6ul-14x14-evk.dtb \ + imx6ul-9x9-evk.dtb dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi new file mode 100644 index 0000000..db640d6 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi { + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts b/arch/arm/dts/imx6ul-14x14-evk.dts new file mode 100644 index 0000000..a642d77 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; + + aliases { + spi5 = &soft_spi; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + soft_spi: soft-spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi new file mode 100644 index 0000000..db640d6 --- /dev/null +++ b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi { + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts new file mode 100644 index 0000000..2270451 --- /dev/null +++ b/arch/arm/dts/imx6ul-9x9-evk.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + aliases { + spi5 = &soft_spi; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + }; + + soft_spi: soft-spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; From 1a8c01995fa7a5086a51f3cf0d11e54ef07beefe Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 20:23:17 -0700 Subject: [PATCH 06/15] imx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot Convert the codes and configurations to enable DM drivers in u-boot for modules: i2c, PMIC, regulator, USB, Ethernet, SD/MMC, GPIO and QSPI This patch does not change SPL, so it still uses non-DM driver for UART, GPIO and SD/MMC. Signed-off-by: Ye Li --- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 208 +++++----------------- configs/mx6ul_14x14_evk_defconfig | 17 +- configs/mx6ul_9x9_evk_defconfig | 20 ++- include/configs/mx6ul_14x14_evk.h | 13 +- 4 files changed, 82 insertions(+), 176 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 1c9ffda..595ad76 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -59,158 +59,47 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define IOX_SDI IMX_GPIO_NR(5, 10) -#define IOX_STCP IMX_GPIO_NR(5, 7) -#define IOX_SHCP IMX_GPIO_NR(5, 11) -#define IOX_OE IMX_GPIO_NR(5, 8) - -static iomux_v3_cfg_t const iox_pads[] = { - /* IOX_SDI */ - MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_SHCP */ - MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_STCP */ - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_nOE */ - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -/* - * HDMI_nRST --> Q0 - * ENET1_nRST --> Q1 - * ENET2_nRST --> Q2 - * CAN1_2_STBY --> Q3 - * BT_nPWD --> Q4 - * CSI_RST --> Q5 - * CSI_PWDN --> Q6 - * LCD_nPWREN --> Q7 - */ -enum qn { - HDMI_NRST, - ENET1_NRST, - ENET2_NRST, - CAN1_2_STBY, - BT_NPWD, - CSI_RST, - CSI_PWDN, - LCD_NPWREN, -}; - -enum qn_func { - qn_reset, - qn_enable, - qn_disable, -}; - -enum qn_level { - qn_low = 0, - qn_high = 1, -}; - -static enum qn_level seq[3][2] = { - {0, 1}, {1, 1}, {0, 0} -}; - -static enum qn_func qn_output[8] = { - qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, - qn_disable, qn_disable -}; +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -static void iox74lv_init(void) +#ifdef CONFIG_DM_PMIC +int power_init_board(void) { - int i; + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; - gpio_direction_output(IOX_OE, 0); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); -}; + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC and EEPROM */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, - .gp = IMX_GPIO_NR(1, 28), - }, - .sda = { - .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, - .gp = IMX_GPIO_NR(1, 29), - }, -}; + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -int power_init_board(void) -{ - if (is_mx6ul_9x9_evk()) { - struct pmic *pfuze; - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) - return ret; - - pfuze = pmic_get("PFUZE3000"); - ret = pmic_probe(pfuze); - if (ret) - return ret; - - pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); - pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", - reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); - - /* SW1B step ramp up time from 2us to 4us/25mV */ - reg = 0x40; - pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); - - /* SW1B mode to APS/PFM */ - reg = 0xc; - pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); - - /* SW1B standby voltage set to 0.975V */ - reg = 0xb; - pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); - } + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); return 0; } #endif -#endif int dram_init(void) { @@ -294,25 +183,8 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_QSPI - -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - static int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); /* Set the clock */ enable_qspi_clk(0); @@ -349,6 +221,7 @@ int board_mmc_getcd(struct mmc *mmc) ret = 1; #else imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); gpio_direction_input(USDHC2_CD_GPIO); /* @@ -393,6 +266,7 @@ int board_mmc_init(bd_t *bis) case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -408,6 +282,7 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); @@ -430,11 +305,13 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; /* At default the 3v3 enables the MIC2026 for VBUS power */ @@ -468,6 +345,7 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif #ifdef CONFIG_FEC_MXC /* @@ -606,11 +484,13 @@ static int setup_lcd(void) imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); udelay(500); gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); return 0; @@ -629,21 +509,15 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); - - iox74lv_init(); - -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -#endif - #ifdef CONFIG_FEC_MXC setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 038f3a6..64ddc4f 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y @@ -30,11 +31,18 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y @@ -45,8 +53,15 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 5e02073..af8939f 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y @@ -30,11 +31,18 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y @@ -45,8 +53,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 3ad2518..c8c088e 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -38,17 +38,14 @@ /* I2C configs */ #ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif -/* PMIC only for 9X9 EVK */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#ifdef CONFIG_DM_GPIO +#define CONFIG_DM_74X164 #endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -166,6 +163,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 @@ -190,12 +188,13 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x2 #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" #endif -#define CONFIG_ETHPRIME "FEC" #endif #define CONFIG_IMX_THERMAL From 69f78cf840d03c25347847aaa74f2bdfa6c19f46 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Sat, 21 Jul 2018 19:47:03 +0200 Subject: [PATCH 07/15] watchdog: mx25: use the imx_watchdog driver for mx25 The existing imx_watchdog driver is compatible with mx25 chipsets. Add a WDOG1_BASE_ADDR define for the base address and enable the driver in watchdog's Makefile. To use the driver, a board must define CONFIG_IMX_WATCHDOG and CONFIG_HW_WATCHDOG. This fixes an issue when booting an mx25 chip via usb/serial. In this case, the boot rom will always enable the watchdog. If u-boot is running in interactive mode and the watchdog is not serviced, the system is rebooted when the watchdog expires. Signed-off-by: Martin Kaiser Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-mx25/imx-regs.h | 1 + drivers/watchdog/Makefile | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index cee42e5..5d0974f 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -354,6 +354,7 @@ struct cspi_regs { #define IMX_GPIO2_BASE (0x53FD0000) #define IMX_SDMA_BASE (0x53FD4000) #define IMX_WDT_BASE (0x53FDC000) +#define WDOG1_BASE_ADDR IMX_WDT_BASE #define IMX_PWM1_BASE (0x53FE0000) #define IMX_RTIC_BASE (0x53FEC000) #define IMX_IIM_BASE (0x53FF0000) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index f405f51..08406ca 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) +ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o From 41b7b4b936a08ad0b7dac333bf2071a3bcf3407c Mon Sep 17 00:00:00 2001 From: Alex Kiernan Date: Tue, 24 Jul 2018 07:29:40 +0000 Subject: [PATCH 08/15] Cleanup CONFIG_BOOTDELAY on cl-som-imx7 CONFIG_BOOTDELAY has been migrated to Kconfig, but cl-som-imx7 was missed. We can just delete the assignments as the config already has the correct value. Signed-off-by: Alex Kiernan --- include/configs/cl-som-imx7.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index f86324a..1b2eee3 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -63,9 +63,7 @@ #undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS #undef CONFIG_BOOTCOMMAND -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_EXTRA_ENV_SETTINGS \ From 11e52bca84e65a35d10830c306dab37dc5621a3d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 8 Aug 2018 09:17:48 +0800 Subject: [PATCH 09/15] imx: mx7: psci: improve cpu hotplug flow This patch improves cpu hotplug, previous cpu_off implementation is NOT safe, a CPU can NOT power down itself in runtime, it will cause system bus hang due to pending transaction. So need to use other online CPU to kill it when it is ready for killed. Here use SRC parameter register and a magic number of ~0 as handshake for killing a offline CPU, when the online CPU checks the psci_affinity_info, it will help kill the offline CPU according to the magic number stored in SRC parameter register. Signed-off-by: Anson Huang --- arch/arm/mach-imx/mx7/psci-mx7.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index aae96c5..d6c4263 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -44,6 +44,14 @@ #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" #endif +#define imx_cpu_gpr_entry_offset(cpu) \ + (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8) +#define imx_cpu_gpr_para_offset(cpu) \ + (imx_cpu_gpr_entry_offset(cpu) + 4) + +#define IMX_CPU_SYNC_OFF ~0 +#define IMX_CPU_SYNC_ON 0 + u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = { PSCI_AFFINITY_LEVEL_ON, PSCI_AFFINITY_LEVEL_OFF}; @@ -116,7 +124,7 @@ __secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep, psci_save(cpu, ep, context_id); - writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); + writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu)); psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); @@ -137,7 +145,11 @@ __secure s32 psci_cpu_off(void) imx_enable_cpu_ca7(cpu, false); imx_gpcv2_set_core_power(cpu, false); - writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); + /* + * We use the cpu jumping argument register to sync with + * psci_affinity_info() which is running on cpu0 to kill the cpu. + */ + writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu)); while (1) wfi(); @@ -198,6 +210,13 @@ __secure s32 psci_affinity_info(u32 __always_unused function_id, if (cpu >= IMX7D_PSCI_NR_CPUS) return ARM_PSCI_RET_INVAL; + /* CPU is waiting for killed */ + if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) { + imx_enable_cpu_ca7(cpu, false); + imx_gpcv2_set_core_power(cpu, false); + writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu)); + } + return psci_state[cpu]; } From b059837850e466d033b09d279743166e352519d1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 8 Aug 2018 09:17:49 +0800 Subject: [PATCH 10/15] imx: mx7: add gpc initialization for low power mode Add i.MX7D GPC initialization for low power mode support like system suspend/resume from linux kernel: - Pending IOMUXC IRQ to workaround GPC state machine issue; - Mask all GPC interrupts for M4/C0/C1; - Configure SCU timing; - Configure time slot ack; - Configure C0/C1 power up/down timing; - Configure wakeup source mechanism; - Disable DSM/RBC related settings. Signed-off-by: Anson Huang --- arch/arm/mach-imx/mx7/soc.c | 103 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 7334ca9..502f033 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -18,6 +18,37 @@ #include #include +#define IOMUXC_GPR1 0x4 +#define BM_IOMUXC_GPR1_IRQ 0x1000 + +#define GPC_LPCR_A7_BSC 0x0 +#define GPC_LPCR_M4 0x8 +#define GPC_SLPCR 0x14 +#define GPC_PGC_ACK_SEL_A7 0x24 +#define GPC_IMR1_CORE0 0x30 +#define GPC_IMR1_CORE1 0x40 +#define GPC_IMR1_M4 0x50 +#define GPC_PGC_CPU_MAPPING 0xec +#define GPC_PGC_C0_PUPSCR 0x804 +#define GPC_PGC_SCU_TIMING 0x890 +#define GPC_PGC_C1_PUPSCR 0x844 + +#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000 +#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000 +#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000 +#define BM_SLPCR_EN_DSM 0x80000000 +#define BM_SLPCR_RBC_EN 0x40000000 +#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000 +#define BM_SLPCR_VSTBY 0x4 +#define BM_SLPCR_SBYOS 0x2 +#define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000 + +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000 +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000 + +#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80 + #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, @@ -159,6 +190,76 @@ static void imx_enet_mdio_fixup(void) } } +static void imx_gpcv2_init(void) +{ + u32 val, i; + + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1); + val |= BM_IOMUXC_GPR1_IRQ; + writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1); + + /* Initially mask all interrupts */ + for (i = 0; i < 4; i++) { + writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4); + writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4); + } + + /* set SCU timing */ + writel((0x59 << 10) | 0x5B | (0x2 << 20), + GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); + + /* set C0 power up timming per design requirement */ + val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR); + + /* set C1 power up timming per design requirement */ + val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR); + + /* dummy ack for time slot by default */ + writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7); + + /* mask M4 DSM trigger */ + writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, + GPC_IPS_BASE_ADDR + GPC_LPCR_M4); + + /* set mega/fast mix in A7 domain */ + writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING); + + /* DSM related settings */ + val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY | + BM_SLPCR_REG_BYPASS_COUNT); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* + * disabling RBC need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); +} + int arch_cpu_init(void) { init_aips(); @@ -180,6 +281,8 @@ int arch_cpu_init(void) init_snvs(); + imx_gpcv2_init(); + return 0; } From 57b620255e726fae38e5e2ac5c7dec4b9011ffca Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 8 Aug 2018 09:17:50 +0800 Subject: [PATCH 11/15] imx: mx7: add system suspend/resume support This patch adds system suspend/resume support, when linux kernel enters deep sleep mode, SoC will go into below mode: - CA7 platform goes into STOP mode; - SoC goes into DSM mode; - DDR goes into self-refresh mode; - CPU0/SCU will be powered down. When wake up event arrives: - SoC DSM mdoe exits; - CA7 platform exit STOP mode, SCU/CPU0 power up; - Invalidate L1 cache; - DDR exit self-refresh mode; - Do secure monitor mode related initialization; - Jump to linux kernel resume entry. Belwo is the log of 1 iteration of system suspend/resume: [ 338.824862] PM: suspend entry (deep) [ 338.828853] PM: Syncing filesystems ... done. [ 338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 338.842939] OOM killer disabled. [ 338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 338.869717] PM: suspend devices took 0.010 seconds [ 338.877846] Disabling non-boot CPUs ... [ 338.960301] Retrying again to check for CPU kill [ 338.964953] CPU1 killed. [ 338.968104] Enabling non-boot CPUs ... [ 338.973598] CPU1 is up [ 339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes) [ 339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes) [ 339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes) [ 339.385065] PM: resume devices took 0.400 seconds [ 339.389836] OOM killer enabled. [ 339.392986] Restarting tasks ... done. [ 339.398990] PM: suspend exit The resume entry function has to initialize stack pointer before calling C code, otherwise there will be an external abort occur, in additional, invalidate L1 cache must be done in secure section as well, so this patch also adds assembly code back and keep it as simple as possible. Signed-off-by: Anson Huang Acked-by: Stefan Agner Tested-by: Stefan Agner --- arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/psci-mx7.c | 449 ++++++++++++++++++++++++++++++++++- arch/arm/mach-imx/mx7/psci-suspend.S | 67 ++++++ 3 files changed, 515 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-imx/mx7/psci-suspend.S diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index 94a0e64..f1436e2 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -4,4 +4,4 @@ # obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o -obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o +obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o psci-suspend.o diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index d6c4263..34ba0a9 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -8,20 +8,77 @@ #include #include #include +#include +#include #include #include #include -#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_LPCR_A7_BSC 0x0 +#define GPC_LPCR_A7_AD 0x4 +#define GPC_SLPCR 0x14 +#define GPC_PGC_ACK_SEL_A7 0x24 +#define GPC_IMR1_CORE0 0x30 +#define GPC_SLOT0_CFG 0xb0 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PGC_C0 0x800 #define GPC_PGC_C0 0x800 #define GPC_PGC_C1 0x840 +#define GPC_PGC_SCU 0x880 + +#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000 +#define BM_LPCR_A7_BSC_LPM1 0xc +#define BM_LPCR_A7_BSC_LPM0 0x3 +#define BP_LPCR_A7_BSC_LPM0 0 +#define BM_SLPCR_EN_DSM 0x80000000 +#define BM_SLPCR_RBC_EN 0x40000000 +#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000 +#define BM_SLPCR_VSTBY 0x4 +#define BM_SLPCR_SBYOS 0x2 +#define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_LPCR_A7_AD_L2PGE 0x10000 +#define BM_LPCR_A7_AD_EN_C1_PUP 0x800 +#define BM_LPCR_A7_AD_EN_C0_PUP 0x200 +#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10 +#define BM_LPCR_A7_AD_EN_C1_PDN 0x8 +#define BM_LPCR_A7_AD_EN_C0_PDN 0x2 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 -/* below is for i.MX7D */ +#define BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK 0x8000 +#define BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK 0x80000000 + +#define MAX_SLOT_NUMBER 10 +#define A7_LPM_WAIT 0x5 +#define A7_LPM_STOP 0xa + +#define BM_SYS_COUNTER_CNTCR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTCR_FCR0 0x100 + +#define REG_SET 0x4 +#define REG_CLR 0x8 + +#define ANADIG_ARM_PLL 0x60 +#define ANADIG_DDR_PLL 0x70 +#define ANADIG_SYS_PLL 0xb0 +#define ANADIG_ENET_PLL 0xe0 +#define ANADIG_AUDIO_PLL 0xf0 +#define ANADIG_VIDEO_PLL 0x130 +#define BM_ANATOP_ARM_PLL_OVERRIDE BIT(20) +#define BM_ANATOP_DDR_PLL_OVERRIDE BIT(19) +#define BM_ANATOP_SYS_PLL_OVERRIDE (0x1ff << 17) +#define BM_ANATOP_ENET_PLL_OVERRIDE BIT(13) +#define BM_ANATOP_AUDIO_PLL_OVERRIDE BIT(24) +#define BM_ANATOP_VIDEO_PLL_OVERRIDE BIT(24) + +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_PSTAT 0x3fc + #define SRC_GPR1_MX7D 0x074 +#define SRC_GPR2_MX7D 0x078 #define SRC_A7RCR0 0x004 #define SRC_A7RCR1 0x008 @@ -56,6 +113,27 @@ u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = { PSCI_AFFINITY_LEVEL_ON, PSCI_AFFINITY_LEVEL_OFF}; +enum imx_gpc_slot { + CORE0_A7, + CORE1_A7, + SCU_A7, + FAST_MEGA_MIX, + MIPI_PHY, + PCIE_PHY, + USB_OTG1_PHY, + USB_OTG2_PHY, + USB_HSIC_PHY, + CORE0_M4, +}; + +enum mxc_cpu_pwr_mode { + RUN, + WAIT, + STOP, +}; + +extern void psci_system_resume(void); + static inline void psci_set_state(int cpu, u8 state) { psci_state[cpu] = state; @@ -237,7 +315,374 @@ __secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) case ARM_PSCI_0_2_FN_SYSTEM_OFF: case ARM_PSCI_0_2_FN_SYSTEM_RESET: case ARM_PSCI_1_0_FN_PSCI_FEATURES: + case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND: return 0x0; } return ARM_PSCI_RET_NI; } + +static __secure void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode) +{ + u32 val1, val2, val3; + + val1 = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); + val2 = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* all cores' LPM settings must be same */ + val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1); + val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + + val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + /* + * GPC: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_IRQ. + * 2) Software should then unmask IRQ #32 in GPC before setting GPC + * Low-Power mode. + * 3) Software should mask IRQ #32 right after GPC Low-Power mode + * is set. + */ + switch (mode) { + case RUN: + val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + val3 &= ~0x1; + writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + break; + case WAIT: + val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + val3 &= ~0x1; + writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + break; + case STOP: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_SBYOS; + val2 |= BM_SLPCR_VSTBY; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + val3 |= 0x1; + writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); + break; + default: + return; + } + writel(val1, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); + writel(val2, GPC_IPS_BASE_ADDR + GPC_SLPCR); +} + +static __secure void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) +{ + u32 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD); + + val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE); + if (pdn) + val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE; + + writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD); +} + +static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn) +{ + u32 val; + + val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD); + if (cpu == 0) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP); + } + if (cpu == 1) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP); + } + writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD); +} + +static __secure void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core, + bool mode, bool ack) +{ + u32 val; + + if (index >= MAX_SLOT_NUMBER) + return; + + /* set slot */ + writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | + ((mode + 1) << (m_core * 2)), + GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); + + if (ack) { + /* set ack */ + val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7); + /* clear dummy ack */ + val &= ~(mode ? BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK : + BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK); + val |= 1 << (m_core + (mode ? 16 : 0)); + writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7); + } +} + +static __secure void imx_system_counter_resume(void) +{ + u32 val; + + val = readl(SYSCNT_CTRL_IPS_BASE_ADDR); + val &= ~BM_SYS_COUNTER_CNTCR_FCR1; + val |= BM_SYS_COUNTER_CNTCR_FCR0; + writel(val, SYSCNT_CTRL_IPS_BASE_ADDR); +} + +static __secure void imx_system_counter_suspend(void) +{ + u32 val; + + val = readl(SYSCNT_CTRL_IPS_BASE_ADDR); + val &= ~BM_SYS_COUNTER_CNTCR_FCR0; + val |= BM_SYS_COUNTER_CNTCR_FCR1; + writel(val, SYSCNT_CTRL_IPS_BASE_ADDR); +} + +static __secure void gic_resume(void) +{ + u32 itlinesnr, i; + u32 gic_dist_addr = GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET; + + /* enable the GIC distributor */ + writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, + gic_dist_addr + GICD_CTLR); + + /* TYPER[4:0] contains an encoded number of available interrupts */ + itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; + + /* set all bits in the GIC group registers to one to allow access + * from non-secure state. The first 32 interrupts are private per + * CPU and will be set later when enabling the GIC for each core + */ + for (i = 1; i <= itlinesnr; i++) + writel((u32)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); +} + +static inline void imx_pll_suspend(void) +{ + writel(BM_ANATOP_ARM_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_SET); + writel(BM_ANATOP_DDR_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_SET); + writel(BM_ANATOP_SYS_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_SET); + writel(BM_ANATOP_ENET_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_SET); + writel(BM_ANATOP_AUDIO_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_SET); + writel(BM_ANATOP_VIDEO_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_SET); +} + +static inline void imx_pll_resume(void) +{ + writel(BM_ANATOP_ARM_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_CLR); + writel(BM_ANATOP_DDR_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_CLR); + writel(BM_ANATOP_SYS_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_CLR); + writel(BM_ANATOP_ENET_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_CLR); + writel(BM_ANATOP_AUDIO_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_CLR); + writel(BM_ANATOP_VIDEO_PLL_OVERRIDE, + ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_CLR); +} + +static inline void imx_udelay(u32 usec) +{ + u32 freq; + u64 start, end; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); + do { + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); + if ((end - start) > usec * (freq / 1000000)) + break; + } while (1); +} + +static inline void imx_ddrc_enter_self_refresh(void) +{ + writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); + while (readl(DDRC_IPS_BASE_ADDR + DDRC_PSTAT) & 0x10001) + ; + + writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); + while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23) + ; + writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8, + DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); +} + +static inline void imx_ddrc_exit_self_refresh(void) +{ + writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); + while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3) + ; + writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1, + DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); +} + +__secure void imx_system_resume(void) +{ + unsigned int i, val, imr[4], entry; + + entry = psci_get_target_pc(0); + imx_ddrc_exit_self_refresh(); + imx_system_counter_resume(); + imx_gpcv2_set_lpm_mode(RUN); + imx_gpcv2_set_cpu_power_gate_by_lpm(0, false); + imx_gpcv2_set_plat_power_gate_by_lpm(false); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU); + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + for (i = 0; i < 4; i++) { + imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + } + + /* configure RBC enable bit */ + val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + val &= ~BM_SLPCR_RBC_EN; + writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* configure RBC count */ + val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + val &= ~BM_SLPCR_REG_BYPASS_COUNT; + writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + imx_udelay(65); + + /* restore GPC interrupt mask settings */ + for (i = 0; i < 4; i++) + writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + + /* initialize gic distributor */ + gic_resume(); + _nonsec_init(); + + /* save cpu0 entry */ + psci_save(0, entry, 0); + psci_cpu_entry(); +} + +__secure void psci_system_suspend(u32 __always_unused function_id, + u32 ep, u32 context_id) +{ + u32 gpc_mask[4]; + u32 i, val; + + psci_save(0, ep, context_id); + /* overwrite PLL to be controlled by low power mode */ + imx_pll_suspend(); + imx_system_counter_suspend(); + /* set CA7 platform to enter STOP mode */ + imx_gpcv2_set_lpm_mode(STOP); + /* enable core0/scu power down/up with low power mode */ + imx_gpcv2_set_cpu_power_gate_by_lpm(0, true); + imx_gpcv2_set_plat_power_gate_by_lpm(true); + /* time slot settings for core0 and scu */ + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + imx_gpcv2_set_slot_ack(1, SCU_A7, false, true); + imx_gpcv2_set_slot_ack(5, SCU_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU); + psci_v7_flush_dcache_all(); + + imx_ddrc_enter_self_refresh(); + + /* + * e10133: ARM: Boot failure after A7 enters into + * low-power idle mode + * + * Workaround: + * If both CPU0/CPU1 are IDLE, the last IDLE CPU should + * disable GIC first, then REG_BYPASS_COUNTER is used + * to mask wakeup INT, and then execute “wfi” is used to + * bring the system into power down processing safely. + * The counter must be enabled as close to the “wfi” state + * as possible. The following equation can be used to + * determine the RBC counter value: + * RBC_COUNT * (1/32K RTC frequency) >= + * (46 + PDNSCR_SW + PDNSCR_SW2ISO ) ( 1/IPG_CLK frequency ). + */ + + /* disable GIC distributor */ + writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET); + + for (i = 0; i < 4; i++) + gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (240us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~250uS. + */ + val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + val &= ~(0x3f << 24); + val |= (0x8 << 24); + writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* enable the counter. */ + val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); + val |= (1 << 30); + writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR); + + /* unmask all the GPC interrupts. */ + for (i = 0; i < 4; i++) + writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + imx_udelay(3); + + /* save resume entry and sp in CPU0 GPR registers */ + asm volatile("mov %0, sp" : "=r" (val)); + writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D); + writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D); + + /* sleep */ + while (1) + wfi(); +} diff --git a/arch/arm/mach-imx/mx7/psci-suspend.S b/arch/arm/mach-imx/mx7/psci-suspend.S new file mode 100644 index 0000000..a21403f --- /dev/null +++ b/arch/arm/mach-imx/mx7/psci-suspend.S @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + +.globl v7_invalidate_l1 +v7_invalidate_l1: + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + movw r1, #0x7fff + and r2, r1, r0, lsr #13 + + movw r1, #0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: + sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: + subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp< Date: Mon, 6 Aug 2018 09:19:18 +0200 Subject: [PATCH 12/15] board: toradex: common: fail gracefully on missing NAND chip If the NAND chip is missing get_nand_dev_by_index() returns NULL. Fail gracefully in this case. Signed-off-by: Stefan Agner --- board/toradex/common/tdx-cfg-block.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 57edb6c..d4f5b18 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -156,10 +156,13 @@ out: static int read_tdx_cfg_block_from_nand(unsigned char *config_block) { size_t size = TDX_CFG_BLOCK_MAX_SIZE; + struct mtd_info *mtd = get_nand_dev_by_index(0); + + if (!mtd) + return -ENODEV; /* Read production parameter config block from NAND page */ - return nand_read_skip_bad(get_nand_dev_by_index(0), - CONFIG_TDX_CFG_BLOCK_OFFSET, + return nand_read_skip_bad(mtd, CONFIG_TDX_CFG_BLOCK_OFFSET, &size, NULL, TDX_CFG_BLOCK_MAX_SIZE, config_block); } From a62c60610f514063ac71f8835b47d413972256b8 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 6 Aug 2018 09:19:19 +0200 Subject: [PATCH 13/15] colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support This commit adds support for the Toradex Colibri iMX7D 1GB Computer on Module. The module is very similar to the Colibri iMX7D 512MB but uses eMMC instead of raw NAND. This patch introduces a new board specific Kconfig symbol to select between the two flash options. Signed-off-by: Stefan Agner --- board/toradex/colibri_imx7/Kconfig | 42 ++++++++++++++- board/toradex/colibri_imx7/MAINTAINERS | 4 ++ board/toradex/colibri_imx7/colibri_imx7.c | 41 ++++++++++++-- include/configs/colibri_imx7.h | 90 ++++++++++++++++++++++++------- 4 files changed, 154 insertions(+), 23 deletions(-) diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig index 414a600..d33ec63 100644 --- a/board/toradex/colibri_imx7/Kconfig +++ b/board/toradex/colibri_imx7/Kconfig @@ -1,5 +1,24 @@ if TARGET_COLIBRI_IMX7 +choice + prompt "Colibri iMX7S/D variant" + +config TARGET_COLIBRI_IMX7_NAND + bool "Support Colibri iMX7 Solo 256MB/Dual 512MB (raw NAND) modules" + imply NAND_MXS + help + Choose this option if you build for a Toradex Colibri iMX7S + 256MB or Colibri iMX7D 512MB module which do have raw NAND + on-module. + +config TARGET_COLIBRI_IMX7_EMMC + bool "Support Colibri iMX7 Dual 1GB (eMMC) modules" + help + Choose this option if you build for a Toradex Colibri iMX7D + 1GB module which does have eMMC on-module. + +endchoice + config SYS_BOARD default "colibri_imx7" @@ -19,6 +38,11 @@ config COLIBRI_IMX7_EXT_PHYCLK config TDX_CFG_BLOCK default y +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +if TARGET_COLIBRI_IMX7_NAND + config TDX_HAVE_NAND default y @@ -28,9 +52,25 @@ config TDX_CFG_BLOCK_OFFSET config TDX_CFG_BLOCK_OFFSET2 default "133120" -config TDX_CFG_BLOCK_2ND_ETHADDR +endif + +if TARGET_COLIBRI_IMX7_EMMC + +config TDX_HAVE_MMC default y +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +endif + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 5ffb241..9c1d42a 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,6 +1,10 @@ Colibri iMX7 M: Stefan Agner +M: Toradex ARM Support +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_imx7/ F: include/configs/colibri_imx7.h F: configs/colibri_imx7_defconfig +F: configs/colibri_imx7_emmc_defconfig diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 2210095..2b7591e 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Toradex AG + * Copyright (C) 2016-2018 Toradex AG */ #include @@ -81,7 +81,7 @@ static iomux_v3_cfg_t const usb_cdet_pads[] = { }; #endif -#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -109,6 +109,24 @@ static void setup_gpmi_nand(void) } #endif +#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -198,6 +216,9 @@ static void setup_iomux_uart(void) #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) static struct fsl_esdhc_cfg usdhc_cfg[] = { +#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC + {USDHC3_BASE_ADDR}, +#endif {USDHC1_BASE_ADDR, 0, 4}, }; @@ -210,6 +231,11 @@ int board_mmc_getcd(struct mmc *mmc) case USDHC1_BASE_ADDR: ret = !gpio_get_value(USDHC1_CD_GPIO); break; +#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC + case USDHC3_BASE_ADDR: + ret = 1; + break; +#endif } return ret; @@ -218,7 +244,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int i, ret; - /* USDHC1 is mmc0 */ + /* USDHC1 is mmc0, USDHC3 is mmc1 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: @@ -228,6 +254,13 @@ int board_mmc_init(bd_t *bis) gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; +#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads, + ARRAY_SIZE(usdhc3_emmc_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; +#endif default: printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board\n", i + 1); @@ -305,7 +338,7 @@ int board_init(void) setup_fec(); #endif -#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND setup_gpmi_nand(); #endif diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index e7da8b7..ff6bd67 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2018 Toradex AG * * Configuration settings for the Colibri iMX7 module. * @@ -14,7 +14,7 @@ #include "mx7_common.h" /*#define CONFIG_DBG_MONITOR*/ -#define PHYS_SDRAM_SIZE SZ_512M +#define PHYS_SDRAM_SIZE SZ_1G /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) @@ -34,7 +34,13 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND #define CONFIG_SYS_FSL_USDHC_NUM 1 +#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SUPPORT_EMMC_BOOT +#endif #undef CONFIG_BOOTM_PLAN9 #undef CONFIG_BOOTM_RTEMS @@ -47,6 +53,16 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 +#define EMMC_BOOTCMD \ + "emmcargs=ip=off root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait\0" \ + "emmcboot=run setup; " \ + "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ + "${vidargs}; echo Booting from internal eMMC chip...; " \ + "run m4boot && " \ + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-emmc-${fdt_board}.dtb && " \ + "load mmc 0:1 ${kernel_addr_r} ${boot_file} && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" + #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ @@ -55,22 +71,34 @@ "kernel_addr_r=0x81000000\0" \ "ramdisk_addr_r=0x82100000\0" +#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define SD_BOOTCMD \ - "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \ "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ "run m4boot && " \ "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk1p2 ro rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "run m4boot && " \ + "load mmc 1:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 1:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" +#endif + #define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ "nfsboot=run setup; " \ "setenv bootargs ${defargs} ${nfsargs} " \ "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #define UBI_BOOTCMD \ @@ -84,13 +112,40 @@ "ubi read ${fdt_addr_r} dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" +#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) +#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \ + "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" +#define MODULE_EXTRA_ENV_SETTINGS \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + UBI_BOOTCMD +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \ + "setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;" +#define MODULE_EXTRA_ENV_SETTINGS \ + "variant=-emmc\0" \ + EMMC_BOOTCMD +#endif + +#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#endif +#include #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ NFS_BOOTCMD \ SD_BOOTCMD \ - UBI_BOOTCMD \ + MODULE_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "defargs=\0" \ "fdt_board=eval-v3\0" \ @@ -98,7 +153,6 @@ "m4boot=;\0" \ "ip_dyn=yes\0" \ "kernel_file=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -139,26 +193,26 @@ /* environment organization */ #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 #elif defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #endif +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES - -/* Dynamic MTD partition support */ - -/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET From b8babd8050f6780bb67e90d9402f9f19e0d63045 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 31 Aug 2018 12:08:43 +0200 Subject: [PATCH 14/15] imx: missing CONFIG_MII in mx7dsabresd_qspi_defconfig CONFIG_CMD_MII is set without CONFIG_MII, build is broken. Signed-off-by: Stefano Babic --- configs/mx7dsabresd_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index a798804..53894e6 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_BAR=y +CONFIG_MII=y CONFIG_PHYLIB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y From c1d1543ebc6e1fb026d0d7ac96d865faa7567555 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 1 Sep 2018 14:24:56 -0300 Subject: [PATCH 15/15] mx7dsabresd: Add the qspi target to the list of supported defconfigs Add an entry for mx7dsabresd_qspi_defconfig to avoid the following warnings: WARNING: no status info for 'mx7dsabresd_qspi' WARNING: no maintainers for 'mx7dsabresd_qspi' Reported-by: Tom Rini Signed-off-by: Fabio Estevam --- board/freescale/mx7dsabresd/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS index b96642a..5f805af 100644 --- a/board/freescale/mx7dsabresd/MAINTAINERS +++ b/board/freescale/mx7dsabresd/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mx7dsabresd F: include/configs/mx7dsabresd.h F: configs/mx7dsabresd_defconfig +F: configs/mx7dsabresd_qspi_defconfig