Split clock.c for am335x and ti814x and add ti814x specific clock support. Signed-off-by: Matt Porter <mporter@ti.com>master
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/*
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* clock_ti814x.c |
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* |
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* Clocks for TI814X based boards |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <common.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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/* PRCM */ |
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#define PRCM_MOD_EN 0x2 |
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/* CLK_SRC */ |
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#define OSC_SRC0 0 |
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#define OSC_SRC1 1 |
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#define L3_OSC_SRC OSC_SRC0 |
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#define OSC_0_FREQ 20 |
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#define DCO_HS2_MIN 500 |
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#define DCO_HS2_MAX 1000 |
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#define DCO_HS1_MIN 1000 |
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#define DCO_HS1_MAX 2000 |
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#define SELFREQDCO_HS2 0x00000801 |
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#define SELFREQDCO_HS1 0x00001001 |
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#define MPU_N 0x1 |
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#define MPU_M 0x3C |
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#define MPU_M2 1 |
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#define MPU_CLKCTRL 0x1 |
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#define L3_N 19 |
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#define L3_M 880 |
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#define L3_M2 4 |
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#define L3_CLKCTRL 0x801 |
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#define DDR_N 19 |
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#define DDR_M 666 |
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#define DDR_M2 2 |
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#define DDR_CLKCTRL 0x801 |
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/* ADPLLJ register values */ |
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#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ |
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#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ |
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#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) |
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#define ADPLLJ_CLKCTRL_IDLE (1 << 23) |
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#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) |
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#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) |
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#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) |
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#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) |
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#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) |
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#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) |
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#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) |
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#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ |
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ADPLLJ_CLKCTRL_CLKOUTEN | \
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ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
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ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) |
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#define ADPLLJ_STATUS_PHASELOCK (1 << 10) |
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#define ADPLLJ_STATUS_FREQLOCK (1 << 9) |
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#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ |
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ADPLLJ_STATUS_FREQLOCK) |
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#define ADPLLJ_STATUS_BYPASSACK (1 << 8) |
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#define ADPLLJ_STATUS_BYPASS (1 << 0) |
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#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ |
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ADPLLJ_STATUS_BYPASS) |
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#define ADPLLJ_TENABLE_ENB (1 << 0) |
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#define ADPLLJ_TENABLEDIV_ENB (1 << 0) |
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#define ADPLLJ_M2NDIV_M2SHIFT 16 |
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#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) |
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#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) |
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#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) |
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struct ad_pll { |
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unsigned int pwrctrl; |
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unsigned int clkctrl; |
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unsigned int tenable; |
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unsigned int tenablediv; |
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unsigned int m2ndiv; |
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unsigned int mn2div; |
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unsigned int fracdiv; |
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unsigned int bwctrl; |
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unsigned int fracctrl; |
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unsigned int status; |
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unsigned int m3div; |
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unsigned int rampctrl; |
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}; |
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#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) |
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/* PRCM */ |
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#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) |
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struct cm_def { |
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unsigned int resv0[2]; |
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unsigned int l3fastclkstctrl; |
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unsigned int resv1[1]; |
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unsigned int pciclkstctrl; |
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unsigned int resv2[1]; |
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unsigned int ducaticlkstctrl; |
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unsigned int resv3[1]; |
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unsigned int emif0clkctrl; |
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unsigned int emif1clkctrl; |
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unsigned int dmmclkctrl; |
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unsigned int fwclkctrl; |
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unsigned int resv4[10]; |
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unsigned int usbclkctrl; |
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unsigned int resv5[1]; |
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unsigned int sataclkctrl; |
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unsigned int resv6[4]; |
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unsigned int ducaticlkctrl; |
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unsigned int pciclkctrl; |
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}; |
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#define CM_ALWON_BASE (PRCM_BASE + 0x1400) |
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struct cm_alwon { |
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unsigned int l3slowclkstctrl; |
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unsigned int ethclkstctrl; |
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unsigned int l3medclkstctrl; |
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unsigned int mmu_clkstctrl; |
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unsigned int mmucfg_clkstctrl; |
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unsigned int ocmc0clkstctrl; |
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unsigned int vcpclkstctrl; |
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unsigned int mpuclkstctrl; |
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unsigned int sysclk4clkstctrl; |
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unsigned int sysclk5clkstctrl; |
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unsigned int sysclk6clkstctrl; |
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unsigned int rtcclkstctrl; |
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unsigned int l3fastclkstctrl; |
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unsigned int resv0[67]; |
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unsigned int mcasp0clkctrl; |
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unsigned int mcasp1clkctrl; |
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unsigned int mcasp2clkctrl; |
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unsigned int mcbspclkctrl; |
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unsigned int uart0clkctrl; |
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unsigned int uart1clkctrl; |
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unsigned int uart2clkctrl; |
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unsigned int gpio0clkctrl; |
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unsigned int gpio1clkctrl; |
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unsigned int i2c0clkctrl; |
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unsigned int i2c1clkctrl; |
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unsigned int mcasp345clkctrl; |
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unsigned int atlclkctrl; |
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unsigned int mlbclkctrl; |
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unsigned int pataclkctrl; |
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unsigned int resv1[1]; |
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unsigned int uart3clkctrl; |
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unsigned int uart4clkctrl; |
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unsigned int uart5clkctrl; |
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unsigned int wdtimerclkctrl; |
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unsigned int spiclkctrl; |
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unsigned int mailboxclkctrl; |
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unsigned int spinboxclkctrl; |
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unsigned int mmudataclkctrl; |
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unsigned int resv2[2]; |
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unsigned int mmucfgclkctrl; |
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unsigned int resv3[2]; |
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unsigned int ocmc0clkctrl; |
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unsigned int vcpclkctrl; |
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unsigned int resv4[2]; |
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unsigned int controlclkctrl; |
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unsigned int resv5[2]; |
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unsigned int gpmcclkctrl; |
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unsigned int ethernet0clkctrl; |
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unsigned int resv6[1]; |
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unsigned int mpuclkctrl; |
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unsigned int debugssclkctrl; |
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unsigned int l3clkctrl; |
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unsigned int l4hsclkctrl; |
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unsigned int l4lsclkctrl; |
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unsigned int rtcclkctrl; |
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unsigned int tpccclkctrl; |
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unsigned int tptc0clkctrl; |
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unsigned int tptc1clkctrl; |
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unsigned int tptc2clkctrl; |
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unsigned int tptc3clkctrl; |
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unsigned int resv7[4]; |
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unsigned int dcan01clkctrl; |
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unsigned int mmchs0clkctrl; |
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unsigned int mmchs1clkctrl; |
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unsigned int mmchs2clkctrl; |
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unsigned int custefuseclkctrl; |
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}; |
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const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; |
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const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; |
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/*
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* Enable the peripheral clock for required peripherals |
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*/ |
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static void enable_per_clocks(void) |
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{ |
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/* UART0 */ |
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writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); |
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while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) |
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; |
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/* HSMMC1 */ |
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writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); |
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while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) |
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; |
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} |
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/*
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* select the HS1 or HS2 for DCO Freq |
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* return : CLKCTRL |
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*/ |
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static u32 pll_dco_freq_sel(u32 clkout_dco) |
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{ |
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if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) |
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return SELFREQDCO_HS2; |
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else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) |
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return SELFREQDCO_HS1; |
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else |
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return -1; |
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} |
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/*
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* select the sigma delta config |
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* return: sigma delta val |
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*/ |
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static u32 pll_sigma_delta_val(u32 clkout_dco) |
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{ |
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u32 sig_val = 0; |
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float frac_div; |
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frac_div = (float) clkout_dco / 250; |
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frac_div = frac_div + 0.90; |
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sig_val = (int)frac_div; |
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sig_val = sig_val << 24; |
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return sig_val; |
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} |
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/*
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* configure individual ADPLLJ |
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*/ |
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static void pll_config(u32 base, u32 n, u32 m, u32 m2, |
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u32 clkctrl_val, int adpllj) |
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{ |
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const struct ad_pll *adpll = (struct ad_pll *)base; |
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u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; |
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u32 sig_val = 0, hs_mod = 0; |
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m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; |
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mn2val = m; |
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/* calculate clkout_dco */ |
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clkout_dco = ((OSC_0_FREQ / (n+1)) * m); |
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/* sigma delta & Hs mode selection skip for ADPLLS*/ |
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if (adpllj) { |
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sig_val = pll_sigma_delta_val(clkout_dco); |
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hs_mod = pll_dco_freq_sel(clkout_dco); |
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} |
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/* by-pass pll */ |
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read_clkctrl = readl(&adpll->clkctrl); |
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writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); |
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while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) |
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!= ADPLLJ_STATUS_BYPASSANDACK) |
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; |
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/* clear TINITZ */ |
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read_clkctrl = readl(&adpll->clkctrl); |
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writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); |
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/*
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* ref_clk = 20/(n + 1); |
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* clkout_dco = ref_clk * m; |
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* clk_out = clkout_dco/m2; |
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*/ |
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read_clkctrl = readl(&adpll->clkctrl) & |
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~(ADPLLJ_CLKCTRL_LPMODE | |
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ADPLLJ_CLKCTRL_DRIFTGUARDIAN | |
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ADPLLJ_CLKCTRL_REGM4XEN); |
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writel(m2nval, &adpll->m2ndiv); |
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writel(mn2val, &adpll->mn2div); |
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/* Skip for modena(ADPLLS) */ |
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if (adpllj) { |
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writel(sig_val, &adpll->fracdiv); |
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writel((read_clkctrl | hs_mod), &adpll->clkctrl); |
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} |
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/* Load M2, N2 dividers of ADPLL */ |
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writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); |
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writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); |
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/* Load M, N dividers of ADPLL */ |
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writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); |
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writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); |
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/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ |
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read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; |
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if (adpllj) |
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writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), |
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&adpll->clkctrl); |
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/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ |
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read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; |
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writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); |
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/* Wait for phase and freq lock */ |
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while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != |
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ADPLLJ_STATUS_PHSFRQLOCK) |
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; |
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} |
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static void unlock_pll_control_mmr(void) |
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{ |
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/* TRM 2.10.1.4 and 3.2.7-3.2.11 */ |
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writel(0x1EDA4C3D, 0x481C5040); |
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writel(0x2FF1AC2B, 0x48140060); |
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writel(0xF757FDC0, 0x48140064); |
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writel(0xE2BC3A6D, 0x48140068); |
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writel(0x1EBF131D, 0x4814006c); |
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writel(0x6F361E05, 0x48140070); |
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} |
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static void mpu_pll_config(void) |
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{ |
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pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); |
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} |
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static void l3_pll_config(void) |
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{ |
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u32 l3_osc_src, rd_osc_src = 0; |
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l3_osc_src = L3_OSC_SRC; |
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rd_osc_src = readl(OSC_SRC_CTRL); |
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if (OSC_SRC0 == l3_osc_src) |
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writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); |
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else |
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writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); |
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pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); |
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} |
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void ddr_pll_config(unsigned int ddrpll_m) |
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{ |
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pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); |
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} |
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void enable_emif_clocks(void) {}; |
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void enable_dmm_clocks(void) |
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{ |
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writel(PRCM_MOD_EN, &cmdef->fwclkctrl); |
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writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); |
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writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); |
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while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) |
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; |
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writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); |
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while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) |
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; |
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while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) |
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; |
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writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); |
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while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) |
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; |
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writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); |
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while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) |
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; |
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} |
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/*
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* Configure the PLL/PRCM for necessary peripherals |
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*/ |
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void pll_init() |
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{ |
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unlock_pll_control_mmr(); |
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/* Enable the control module */ |
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writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); |
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mpu_pll_config(); |
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l3_pll_config(); |
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/* Enable the required peripherals */ |
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enable_per_clocks(); |
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} |
@ -0,0 +1,30 @@ |
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/*
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* hardware_am33xx.h |
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* |
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* AM33xx hardware specific header |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef __AM33XX_HARDWARE_AM33XX_H |
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#define __AM33XX_HARDWARE_AM33XX_H |
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/* VTP Base address */ |
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#define VTP0_CTRL_ADDR 0x44E10E0C |
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/* DDR Base address */ |
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#define DDR_PHY_CMD_ADDR 0x44E12000 |
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#define DDR_PHY_DATA_ADDR 0x44E120C8 |
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#define DDR_DATA_REGS_NR 2 |
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#endif /* __AM33XX_HARDWARE_AM33XX_H */ |
@ -0,0 +1,30 @@ |
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/*
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* hardware_ti814x.h |
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* |
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* TI814x hardware specific header |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef __AM33XX_HARDWARE_TI814X_H |
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#define __AM33XX_HARDWARE_TI814X_H |
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/* VTP Base address */ |
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#define VTP0_CTRL_ADDR 0x48140E0C |
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/* DDR Base address */ |
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#define DDR_PHY_CMD_ADDR 0x47C0C400 |
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#define DDR_PHY_DATA_ADDR 0x47C0C4C8 |
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#define DDR_DATA_REGS_NR 4 |
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#endif /* __AM33XX_HARDWARE_TI814X_H */ |
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