This board never left prototyping state and it became a millstone round my neck. So remove it. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>master
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@ -1,54 +0,0 @@ |
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#
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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ifneq ($(OBJTREE),$(SRCTREE)) |
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$(shell mkdir -p $(obj)../common) |
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endif |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o strataflash.o ../common/misc.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,45 +0,0 @@ |
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# esd ADCIOP boards
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#
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#TEXT_BASE = 0xFFFE0000
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ifeq ($(ramsym),1) |
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TEXT_BASE = 0x07FD0000
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else |
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TEXT_BASE = 0xFFFC0000
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#TEXT_BASE = 0x01fc0000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
@ -1,152 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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extern void lxt971_no_sleep(void); |
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long int fixed_sdram( void ); |
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int board_early_init_f (void) |
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{ |
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uint reg; |
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects |
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*-------------------------------------------------------------------*/ |
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mtdcr( ebccfga, xbcfg ); |
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reg = mfdcr( ebccfgd ); |
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mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ |
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mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ |
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mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ |
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/* test-only: other regs still missing... */ |
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc. |
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*-------------------------------------------------------------------*/ |
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mtdcr( uic0sr, 0xffffffff ); /* clear all */ |
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mtdcr( uic0er, 0x00000000 ); /* disable all */ |
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mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ |
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mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ |
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mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ |
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mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ |
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mtdcr( uic0sr, 0xffffffff ); /* clear all */ |
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mtdcr( uic1sr, 0xffffffff ); /* clear all */ |
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mtdcr( uic1er, 0x00000000 ); /* disable all */ |
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mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ |
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mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ |
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mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ |
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mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ |
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mtdcr( uic1sr, 0xffffffff ); /* clear all */ |
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return 0; |
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} |
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int checkboard (void) |
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{ |
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sys_info_t sysinfo; |
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get_sys_info(&sysinfo); |
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printf("Board: esd CPCI-440\n"); |
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printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); |
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printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); |
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printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); |
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printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); |
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printf("\tEBC: %lu MHz\n", sysinfo.freqEBC/1000000); |
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/*
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* Disable sleep mode in LXT971 |
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*/ |
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lxt971_no_sleep(); |
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return (0); |
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} |
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long int initdram (int board_type) |
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{ |
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long dram_size = 0; |
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dram_size = fixed_sdram(); |
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return dram_size; |
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} |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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* |
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* Assumes: 64 MB, non-ECC, non-registered |
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* PLB @ 133 MHz |
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* |
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************************************************************************/ |
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long int fixed_sdram( void ) |
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{ |
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uint reg; |
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#if 1 /* test-only */ |
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/*--------------------------------------------------------------------
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* Setup some default |
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*------------------------------------------------------------------*/ |
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mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ |
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mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ |
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mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ |
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mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ |
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mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ |
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem |
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*------------------------------------------------------------------*/ |
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB |
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*/ |
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mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ |
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mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ |
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/* RA=10 RD=3 */ |
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mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
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mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ |
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mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ |
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udelay( 400 ); /* Delay 200 usecs (min) */ |
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete |
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*------------------------------------------------------------------*/ |
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mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ |
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for(;;) |
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{ |
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mfsdram( mem_mcsts, reg ); |
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if( reg & 0x80000000 ) |
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break; |
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} |
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return( 64 * 1024 * 1024 ); /* 64 MB */ |
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#else |
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return( 32 * 1024 * 1024 ); /* 64 MB */ |
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#endif |
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} |
@ -1,94 +0,0 @@ |
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/* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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/* General */ |
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#define TLB_VALID 0x00000200 |
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/* Supported page sizes */ |
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#define SZ_1K 0x00000000 |
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#define SZ_4K 0x00000010 |
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#define SZ_16K 0x00000020 |
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#define SZ_64K 0x00000030 |
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#define SZ_256K 0x00000040 |
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#define SZ_1M 0x00000050 |
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#define SZ_16M 0x00000070 |
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#define SZ_256M 0x00000090 |
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/* Storage attributes */ |
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#define SA_W 0x00000800 /* Write-through */ |
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#define SA_I 0x00000400 /* Caching inhibited */ |
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#define SA_M 0x00000200 /* Memory coherence */ |
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#define SA_G 0x00000100 /* Guarded */ |
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#define SA_E 0x00000080 /* Endian */ |
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/* Access control */ |
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#define AC_X 0x00000024 /* Execute */ |
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#define AC_W 0x00000012 /* Write */ |
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#define AC_R 0x00000009 /* Read */ |
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/* Some handy macros */ |
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#define EPN(e) ((e) & 0xfffffc00) |
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
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#define TLB2(a) ( (a)&0x00000fbf ) |
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#define tlbtab_start\ |
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mflr r1 ;\
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bl 0f ;
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#define tlbtab_end\ |
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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#define tlbentry(epn,sz,rpn,erpn,attr)\ |
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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.globl tlbtab
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tlbtab: |
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tlbtab_start |
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tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) |
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tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) |
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tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) |
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tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) |
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tlbtab_end |
@ -1,755 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#undef DEBUG_FLASH |
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/*
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* This file implements a Common Flash Interface (CFI) driver for U-Boot. |
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* The width of the port and the width of the chips are determined at initialization. |
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* These widths are used to calculate the address for access CFI data structures. |
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* It has been tested on an Intel Strataflash implementation. |
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* |
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* References |
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* JEDEC Standard JESD68 - Common Flash Interface (CFI) |
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* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes |
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* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets |
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* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet |
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* |
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* TODO |
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* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available |
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* Add support for other command sets Use the PRI and ALT to determine command set |
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* Verify erase and program timeouts. |
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*/ |
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#define FLASH_CMD_CFI 0x98 |
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#define FLASH_CMD_READ_ID 0x90 |
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#define FLASH_CMD_RESET 0xff |
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#define FLASH_CMD_BLOCK_ERASE 0x20 |
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#define FLASH_CMD_ERASE_CONFIRM 0xD0 |
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#define FLASH_CMD_WRITE 0x40 |
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#define FLASH_CMD_PROTECT 0x60 |
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#define FLASH_CMD_PROTECT_SET 0x01 |
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#define FLASH_CMD_PROTECT_CLEAR 0xD0 |
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#define FLASH_CMD_CLEAR_STATUS 0x50 |
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#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
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#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 |
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#define FLASH_STATUS_DONE 0x80 |
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#define FLASH_STATUS_ESS 0x40 |
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#define FLASH_STATUS_ECLBS 0x20 |
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#define FLASH_STATUS_PSLBS 0x10 |
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#define FLASH_STATUS_VPENS 0x08 |
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#define FLASH_STATUS_PSS 0x04 |
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#define FLASH_STATUS_DPS 0x02 |
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#define FLASH_STATUS_R 0x01 |
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#define FLASH_STATUS_PROTECT 0x01 |
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|
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#define FLASH_OFFSET_CFI 0x55 |
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#define FLASH_OFFSET_CFI_RESP 0x10 |
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#define FLASH_OFFSET_WTOUT 0x1F |
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#define FLASH_OFFSET_WBTOUT 0x20 |
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#define FLASH_OFFSET_ETOUT 0x21 |
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#define FLASH_OFFSET_CETOUT 0x22 |
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#define FLASH_OFFSET_WMAX_TOUT 0x23 |
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#define FLASH_OFFSET_WBMAX_TOUT 0x24 |
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#define FLASH_OFFSET_EMAX_TOUT 0x25 |
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#define FLASH_OFFSET_CEMAX_TOUT 0x26 |
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#define FLASH_OFFSET_SIZE 0x27 |
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#define FLASH_OFFSET_INTERFACE 0x28 |
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#define FLASH_OFFSET_BUFFER_SIZE 0x2A |
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#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
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#define FLASH_OFFSET_ERASE_REGIONS 0x2D |
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#define FLASH_OFFSET_PROTECT 0x02 |
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#define FLASH_OFFSET_USER_PROTECTION 0x85 |
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#define FLASH_OFFSET_INTEL_PROTECTION 0x81 |
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|
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|
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#define FLASH_MAN_CFI 0x01000000 |
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|
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|
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typedef union { |
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unsigned char c; |
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unsigned short w; |
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unsigned long l; |
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} cfiword_t; |
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typedef union { |
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unsigned char * cp; |
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unsigned short *wp; |
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unsigned long *lp; |
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} cfiptr_t; |
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|
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#define NUM_ERASE_REGIONS 4 |
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|
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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|
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|
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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|
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|
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static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); |
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static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); |
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static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); |
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static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); |
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static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); |
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static int flash_detect_cfi(flash_info_t * info); |
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static ulong flash_get_size (ulong base, int banknum); |
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static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); |
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static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); |
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#ifdef CFG_FLASH_USE_BUFFER_WRITE |
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static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); |
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#endif |
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/*-----------------------------------------------------------------------
|
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* create an address based on the offset and the port width |
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*/ |
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inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) |
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{ |
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return ((uchar *)(info->start[sect] + (offset * info->portwidth))); |
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} |
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/*-----------------------------------------------------------------------
|
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* read a character at a port width address |
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*/ |
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inline uchar flash_read_uchar(flash_info_t * info, uchar offset) |
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{ |
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uchar *cp; |
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cp = flash_make_addr(info, 0, offset); |
||||
return (cp[info->portwidth - 1]); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a short word by swapping for ppc format. |
||||
*/ |
||||
ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) |
||||
{ |
||||
uchar * addr; |
||||
|
||||
addr = flash_make_addr(info, sect, offset); |
||||
return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); |
||||
|
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a long word by picking the least significant byte of each maiximum |
||||
* port size word. Swap for ppc format. |
||||
*/ |
||||
ulong flash_read_long(flash_info_t * info, int sect, uchar offset) |
||||
{ |
||||
uchar * addr; |
||||
|
||||
addr = flash_make_addr(info, sect, offset); |
||||
return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | |
||||
(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); |
||||
|
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size; |
||||
int i; |
||||
unsigned long address; |
||||
|
||||
|
||||
/* The flash is positioned back to back, with the demultiplexing of the chip
|
||||
* based on the A24 address line. |
||||
* |
||||
*/ |
||||
|
||||
address = CFG_FLASH_BASE; |
||||
size = 0; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
size += flash_info[i].size = flash_get_size(address, i); |
||||
address += CFG_FLASH_INCREMENT; |
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, |
||||
flash_info[0].size, flash_info[i].size<<20); |
||||
} |
||||
} |
||||
|
||||
#if 0 /* test-only */
|
||||
/* Monitor protection ON by default */ |
||||
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) |
||||
for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) |
||||
(void)flash_real_protect(&flash_info[0], i, 1); |
||||
#endif |
||||
#endif |
||||
|
||||
return (size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
int rcode = 0; |
||||
int prot; |
||||
int sect; |
||||
|
||||
if( info->flash_id != FLASH_MAN_CFI) { |
||||
printf ("Can't erase unknown flash type - aborted\n"); |
||||
return 1; |
||||
} |
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
printf ("- no sectors to erase\n"); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
|
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); |
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); |
||||
|
||||
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { |
||||
rcode = 1; |
||||
} else |
||||
printf("."); |
||||
} |
||||
} |
||||
printf (" done\n"); |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id != FLASH_MAN_CFI) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
printf("CFI conformant FLASH (%d x %d)", |
||||
(info->portwidth << 3 ), (info->chipwidth << 3 )); |
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", |
||||
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n"); |
||||
printf (" %08lX%5s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong wp; |
||||
ulong cp; |
||||
int aln; |
||||
cfiword_t cword; |
||||
int i, rc; |
||||
|
||||
/* get lower aligned address */ |
||||
wp = (addr & ~(info->portwidth - 1)); |
||||
|
||||
/* handle unaligned start */ |
||||
if((aln = addr - wp) != 0) { |
||||
cword.l = 0; |
||||
cp = wp; |
||||
for(i=0;i<aln; ++i, ++cp) |
||||
flash_add_byte(info, &cword, (*(uchar *)cp)); |
||||
|
||||
for(; (i< info->portwidth) && (cnt > 0) ; i++) { |
||||
flash_add_byte(info, &cword, *src++); |
||||
cnt--; |
||||
cp++; |
||||
} |
||||
for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) |
||||
flash_add_byte(info, &cword, (*(uchar *)cp)); |
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0) |
||||
return rc; |
||||
wp = cp; |
||||
} |
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE |
||||
while(cnt >= info->portwidth) { |
||||
i = info->buffer_size > cnt? cnt: info->buffer_size; |
||||
if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) |
||||
return rc; |
||||
wp += i; |
||||
src += i; |
||||
cnt -=i; |
||||
} |
||||
#else |
||||
/* handle the aligned part */ |
||||
while(cnt >= info->portwidth) { |
||||
cword.l = 0; |
||||
for(i = 0; i < info->portwidth; i++) { |
||||
flash_add_byte(info, &cword, *src++); |
||||
} |
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0) |
||||
return rc; |
||||
wp += info->portwidth; |
||||
cnt -= info->portwidth; |
||||
} |
||||
#endif /* CFG_FLASH_USE_BUFFER_WRITE */ |
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
cword.l = 0; |
||||
for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { |
||||
flash_add_byte(info, &cword, *src++); |
||||
--cnt; |
||||
} |
||||
for (; i<info->portwidth; ++i, ++cp) { |
||||
flash_add_byte(info, & cword, (*(uchar *)cp)); |
||||
} |
||||
|
||||
return flash_write_cfiword(info, wp, cword); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
int flash_real_protect(flash_info_t *info, long sector, int prot) |
||||
{ |
||||
int retcode = 0; |
||||
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); |
||||
if(prot) |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); |
||||
else |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); |
||||
|
||||
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, |
||||
prot?"protect":"unprotect")) == 0) { |
||||
|
||||
info->protect[sector] = prot; |
||||
/* Intel's unprotect unprotects all locking */ |
||||
if(prot == 0) { |
||||
int i; |
||||
for(i = 0 ; i<info->sector_count; i++) { |
||||
if(info->protect[i]) |
||||
flash_real_protect(info, i, 1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return retcode; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
* wait for XSR.7 to be set. Time out with an error if it does not. |
||||
* This routine does not set the flash to read-array mode. |
||||
*/ |
||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) |
||||
{ |
||||
ulong start; |
||||
|
||||
/* Wait for command completion */ |
||||
start = get_timer (0); |
||||
while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { |
||||
if (get_timer(start) > info->erase_blk_tout) { |
||||
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); |
||||
return ERR_TIMOUT; |
||||
} |
||||
} |
||||
return ERR_OK; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. |
||||
* This routine sets the flash to read-array mode. |
||||
*/ |
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) |
||||
{ |
||||
int retcode; |
||||
retcode = flash_status_check(info, sector, tout, prompt); |
||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { |
||||
retcode = ERR_INVAL; |
||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]); |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ |
||||
printf("Command Sequence Error.\n"); |
||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ |
||||
printf("Block Erase Error.\n"); |
||||
retcode = ERR_NOT_ERASED; |
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { |
||||
printf("Locking Error\n"); |
||||
} |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ |
||||
printf("Block locked.\n"); |
||||
retcode = ERR_PROTECTED; |
||||
} |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) |
||||
printf("Vpp Low Error.\n"); |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); |
||||
return retcode; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) |
||||
{ |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cword->c = c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cword->w = (cword->w << 8) | c; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cword->l = (cword->l << 8) | c; |
||||
} |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths |
||||
*/ |
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) |
||||
{ |
||||
int i; |
||||
uchar *cp = (uchar *)cmdbuf; |
||||
for(i=0; i< info->portwidth; i++) |
||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; |
||||
} |
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address |
||||
*/ |
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) |
||||
{ |
||||
|
||||
volatile cfiptr_t addr; |
||||
cfiword_t cword; |
||||
addr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
*addr.cp = cword.c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
*addr.wp = cword.w; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
*addr.lp = cword.l; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) |
||||
{ |
||||
cfiptr_t cptr; |
||||
cfiword_t cword; |
||||
int retval; |
||||
cptr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
retval = (cptr.cp[0] == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
retval = (cptr.wp[0] == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
retval = (cptr.lp[0] == cword.l); |
||||
break; |
||||
default: |
||||
retval = 0; |
||||
break; |
||||
} |
||||
return retval; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) |
||||
{ |
||||
cfiptr_t cptr; |
||||
cfiword_t cword; |
||||
int retval; |
||||
cptr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
retval = ((cptr.cp[0] & cword.c) == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
retval = ((cptr.wp[0] & cword.w) == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
retval = ((cptr.lp[0] & cword.l) == cword.l); |
||||
break; |
||||
default: |
||||
retval = 0; |
||||
break; |
||||
} |
||||
return retval; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI) |
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
* |
||||
*/ |
||||
static int flash_detect_cfi(flash_info_t * info) |
||||
{ |
||||
|
||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; |
||||
info->portwidth <<= 1) { |
||||
for(info->chipwidth =FLASH_CFI_BY8; |
||||
info->chipwidth <= info->portwidth; |
||||
info->chipwidth <<= 1) { |
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); |
||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && |
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && |
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
* |
||||
*/ |
||||
static ulong flash_get_size (ulong base, int banknum) |
||||
{ |
||||
flash_info_t * info = &flash_info[banknum]; |
||||
int i, j; |
||||
int sect_cnt; |
||||
unsigned long sector; |
||||
unsigned long tmp; |
||||
int size_ratio; |
||||
uchar num_erase_regions; |
||||
int erase_region_size; |
||||
int erase_region_count; |
||||
|
||||
info->start[0] = base; |
||||
|
||||
if(flash_detect_cfi(info)){ |
||||
#ifdef DEBUG_FLASH |
||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ |
||||
#endif |
||||
size_ratio = info->portwidth / info->chipwidth; |
||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); |
||||
#ifdef DEBUG_FLASH |
||||
printf("found %d erase regions\n", num_erase_regions); |
||||
#endif |
||||
sect_cnt = 0; |
||||
sector = base; |
||||
for(i = 0 ; i < num_erase_regions; i++) { |
||||
if(i > NUM_ERASE_REGIONS) { |
||||
printf("%d erase regions found, only %d used\n", |
||||
num_erase_regions, NUM_ERASE_REGIONS); |
||||
break; |
||||
} |
||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); |
||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; |
||||
tmp >>= 16; |
||||
erase_region_count = (tmp & 0xffff) +1; |
||||
for(j = 0; j< erase_region_count; j++) { |
||||
info->start[sect_cnt] = sector; |
||||
sector += (erase_region_size * size_ratio); |
||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); |
||||
sect_cnt++; |
||||
} |
||||
} |
||||
|
||||
info->sector_count = sect_cnt; |
||||
/* multiply the size by the number of chips */ |
||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; |
||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); |
||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); |
||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); |
||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; |
||||
info->flash_id = FLASH_MAN_CFI; |
||||
} |
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
||||
return(info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) |
||||
{ |
||||
|
||||
cfiptr_t ctladdr; |
||||
cfiptr_t cptr; |
||||
int flag; |
||||
|
||||
ctladdr.cp = flash_make_addr(info, 0, 0); |
||||
cptr.cp = (uchar *)dest; |
||||
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
flag = ((cptr.cp[0] & cword.c) == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
flag = ((cptr.wp[0] & cword.w) == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
flag = ((cptr.lp[0] & cword.l) == cword.l); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
if(!flag) |
||||
return 2; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); |
||||
|
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cptr.cp[0] = cword.c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cptr.wp[0] = cword.w; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cptr.lp[0] = cword.l; |
||||
break; |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if(flag) |
||||
enable_interrupts(); |
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write"); |
||||
} |
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE |
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address |
||||
* we have a match |
||||
*/ |
||||
static int find_sector(flash_info_t *info, ulong addr) |
||||
{ |
||||
int sector; |
||||
for(sector = info->sector_count - 1; sector >= 0; sector--) { |
||||
if(addr >= info->start[sector]) |
||||
break; |
||||
} |
||||
return sector; |
||||
} |
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) |
||||
{ |
||||
|
||||
int sector; |
||||
int cnt; |
||||
int retcode; |
||||
volatile cfiptr_t src; |
||||
volatile cfiptr_t dst; |
||||
|
||||
src.cp = cp; |
||||
dst.cp = (uchar *)dest; |
||||
sector = find_sector(info, dest); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); |
||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout, |
||||
"write to buffer")) == ERR_OK) { |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cnt = len; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cnt = len >> 1; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cnt = len >> 2; |
||||
break; |
||||
default: |
||||
return ERR_INVAL; |
||||
break; |
||||
} |
||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1); |
||||
while(cnt-- > 0) { |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
*dst.cp++ = *src.cp++; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
*dst.wp++ = *src.wp++; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
*dst.lp++ = *src.lp++; |
||||
break; |
||||
default: |
||||
return ERR_INVAL; |
||||
break; |
||||
} |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); |
||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout, |
||||
"buffer write"); |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
||||
return retcode; |
||||
} |
||||
#endif /* CFG_USE_FLASH_BUFFER_WRITE */ |
@ -1,159 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
/* .resetvec 0x01FFFFFC :*/ |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
/* .bootpg 0x01FFF000 :*/ |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/esd/cpci440/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/4xx_uart.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,287 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* board/config_CPCI440.h - configuration for esd CPCI-440 board |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_CPCI440 1 /* Board is ebony */ |
||||
#define CONFIG_440GP 1 /* Specifc GP support */ |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
||||
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ |
||||
#if 1 |
||||
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ |
||||
#else |
||||
#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ |
||||
#endif |
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) |
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC |
||||
* |
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base |
||||
* address for the RTC registers is: |
||||
* |
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE |
||||
* |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#if 1 /* test-only */ |
||||
|
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ |
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#undef CFG_FLASH_BASE |
||||
#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ |
||||
|
||||
#else /* test-only */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#if 0 /* test-only */
|
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ |
||||
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ |
||||
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
||||
|
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
#define CFG_ENV_ADDR \ |
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) |
||||
#else |
||||
|
||||
#if 0 /* test-only */
|
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ |
||||
#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ |
||||
/* total size of a CAT24WC16 is 2048 bytes */ |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#undef CONFIG_BOOTCOMMAND |
||||
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_EEPROM |
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if 0 |
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
||||
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
#endif |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* Configuration Port location */ |
||||
#define CONFIG_PORT_ADDR 0xF0000500 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
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Reference in new issue