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/*------------------------------------------------------------------------------+ |
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* |
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* This source code has been made available to you by IBM on an AS-IS |
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* basis. Anyone receiving this source is licensed under IBM |
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* copyrights to use it in any way he or she deems fit, including |
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* copying it, modifying it, compiling it, and redistributing it either |
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* with or without modifications. No license under IBM patents or |
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* patent applications is to be implied by the copyright license. |
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* |
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* Any user of this software should understand that IBM cannot provide |
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* technical support for this software and will not be responsible for |
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* any consequences resulting from the use of this software. |
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* |
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* Any person who transfers this source code or any derivative work |
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* must include the IBM copyright notice, this paragraph, and the |
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* preceding two paragraphs in the transferred software. |
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* |
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* COPYRIGHT I B M CORPORATION 1995 |
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
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*-------------------------------------------------------------------------------*/ |
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|
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/*----------------------------------------------------------------------------- |
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* Function: ext_bus_cntlr_init |
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* Description: Initializes the External Bus Controller for the external |
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* peripherals. IMPORTANT: For pass1 this code must run from |
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* cache since you can not reliably change a peripheral banks |
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* timing register (pbxap) while running code from that bank. |
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* For ex., since we are running from ROM on bank 0, we can NOT |
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* execute the code that modifies bank 0 timings from ROM, so |
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* we run it from cache. |
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* Bank 0 - Flash or Multi Purpose Socket |
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* Bank 1 - Multi Purpose Socket or Flash |
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* Bank 2 - not used |
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* Bank 3 - not used |
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* Bank 4 - not used |
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* Bank 5 - not used |
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* Bank 6 - used to switch on the 12V for the Multipurpose socket |
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* Bank 7 - Config Register |
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*-----------------------------------------------------------------------------*/ |
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#include <ppc4xx.h> |
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ |
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#include "configs/PIP405.h" |
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#include <asm/cache.h> |
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#include <asm/mmu.h> |
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init: |
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mflr r4 /* save link register */ |
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bl ..getAddr |
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..getAddr: |
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mflr r3 /* get address of ..getAddr */ |
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mtlr r4 /* restore link register */ |
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addi r4,0,14 /* set ctr to 14; used to prefetch */
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mtctr r4 /* 14 cache lines to fit this function */ |
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/* in cache (gives us 8x14=112 instrctns) */ |
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..ebcloop: |
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icbt r0,r3 /* prefetch cache line for addr in r3 */ |
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addi r3,r3,32 /* move to next cache line */ |
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bdnz ..ebcloop /* continue for 14 cache lines */ |
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|
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/*------------------------------------------------------------------- |
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* Delay to ensure all accesses to ROM are complete before changing |
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* bank 0 timings. |
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*------------------------------------------------------------------- */ |
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addis r3,0,0x0 |
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ori r3,r3,0xA000 |
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mtctr r3 |
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..spinlp: |
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bdnz ..spinlp /* spin loop */ |
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/*----------------------------------------------------------------------- |
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* decide boot up mode |
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*----------------------------------------------------------------------- */ |
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addi r4,0,pb0cr |
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mtdcr ebccfga,r4 |
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mfdcr r4,ebccfgd |
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andi. r0, r4, 0x2000 /* mask out irrelevant bits */ |
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beq 0f /* jump if 8 bit bus width */ |
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/* setup 16 bit things |
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*----------------------------------------------------------------------- |
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* Memory Bank 0 (16 Bit Flash) initialization |
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*---------------------------------------------------------------------- */ |
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addi r4,0,pb0ap |
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mtdcr ebccfga,r4 |
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addis r4,0,0x9B01 |
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ori r4,r4,0x5480 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb0cr |
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mtdcr ebccfga,r4 |
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/* BS=0x011(8MB),BU=0x3(R/W), */ |
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addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
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ori r4,r4,0xA000 /* BW=0x01(16 bits) */ |
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mtdcr ebccfgd,r4 |
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/*----------------------------------------------------------------------- |
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* Memory Bank 1 (Multi Purpose Socket) initialization |
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*----------------------------------------------------------------------*/ |
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addi r4,0,pb1ap |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0281 |
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ori r4,r4,0x5480 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb1cr |
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mtdcr ebccfga,r4 |
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/* BS=0x011(8MB),BU=0x3(R/W), */ |
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addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
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ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ |
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mtdcr ebccfgd,r4 |
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b 1f |
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0: |
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/* 8Bit boot mode: */ |
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/*----------------------------------------------------------------------- |
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* Memory Bank 0 Multi Purpose Socket initialization |
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*----------------------------------------------------------------------- */ |
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addi r4,0,pb0ap |
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mtdcr ebccfga,r4 |
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addis r4,0,0x9B01 |
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ori r4,r4,0x5480 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb0cr |
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mtdcr ebccfga,r4 |
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/* BS=0x011(4MB),BU=0x3(R/W), */ |
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addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
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ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ |
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mtdcr ebccfgd,r4 |
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/*----------------------------------------------------------------------- |
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* Memory Bank 1 (Flash) initialization |
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*-----------------------------------------------------------------------*/ |
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addi r4,0,pb1ap |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0281 |
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ori r4,r4,0x5480 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb1cr |
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mtdcr ebccfga,r4 |
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/* BS=0x011(8MB),BU=0x3(R/W), */ |
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addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
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ori r4,r4,0xA000 /* BW=0x0( 8 bits) */ |
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mtdcr ebccfgd,r4 |
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1: |
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/*----------------------------------------------------------------------- |
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* Memory Bank 2-3-4-5-6 (not used) initialization |
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*-----------------------------------------------------------------------*/ |
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addi r4,0,pb2cr |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0000 |
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ori r4,r4,0x0000 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb3cr |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0000 |
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ori r4,r4,0x0000 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb4cr |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0000 |
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ori r4,r4,0x0000 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb5cr |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0000 |
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ori r4,r4,0x0000 |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb6cr |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0000 |
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ori r4,r4,0x0000 |
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mtdcr ebccfgd,r4 |
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/*----------------------------------------------------------------------- |
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* Memory Bank 7 (Config Register) initialization |
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*----------------------------------------------------------------------- */ |
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addi r4,0,pb7ap |
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mtdcr ebccfga,r4 |
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addis r4,0,0x0181 /* Doc says TWT=3 and Openios TWT=3!! */ |
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ori r4,r4,0x5280 /* disable Ready, BEM=0 */ |
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mtdcr ebccfgd,r4 |
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addi r4,0,pb7cr |
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mtdcr ebccfga,r4 |
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/* BS=0x0(1MB),BU=0x3(R/W), */ |
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addis r4,0,((CONFIG_PORT_ADDR & 0xFFF00000) | 0x00010000)@h
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ori r4,r4,0x8000 /* BW=0x0(8 bits) */ |
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mtdcr ebccfgd,r4 |
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nop /* pass2 DCR errata #8 */ |
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blr |
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/*----------------------------------------------------------------------------- |
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* Function: sdram_init |
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* Description: Configures the internal SRAM memory. and setup the |
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* Stackpointer in it. |
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*----------------------------------------------------------------------------- */ |
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.globl sdram_init
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sdram_init: |
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blr |
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