Add the new board PM9G45 from Ronetix GmbH. * AT91SAM9G45 MCU at 400Mhz. * 128MB DDR2 SDRAM * 256MB NAND * 10/100 MBits Ethernet DP83848 * Serial number chip DS2401 The board is made as SODIMM200 module. For more info www.ronatix.at or info@ronetix.at. Signed-off-by: Asen Dimov <dimov@ronetix.at>master
parent
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#
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# (C) Copyright 2003-2008
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
|
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# Stelian Pop <stelian.pop@leadtechdesign.com>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += pm9g45.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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TEXT_BASE = 0x73f00000
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@ -0,0 +1,188 @@ |
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/*
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* (C) Copyright 2010 |
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* Ilko Iliev <iliev@ronetix.at> |
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* Asen Dimov <dimov@ronetix.at> |
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* Ronetix GmbH <www.ronetix.at> |
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* |
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/sizes.h> |
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#include <asm/arch/at91sam9g45.h> |
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#include <asm/arch/at91sam9_smc.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/at91_matrix.h> |
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#include <asm/arch/at91_pio.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/io.h> |
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#include <asm/arch/hardware.h> |
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
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#include <net.h> |
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#endif |
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#include <netdev.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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#ifdef CONFIG_CMD_NAND |
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static void pm9g45_nand_hw_init(void) |
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{ |
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unsigned long csa; |
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; |
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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/* Enable CS3 */ |
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csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; |
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writel(csa, &matrix->ccr[6]); |
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|
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), |
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&smc->cs[3].setup); |
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), |
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&smc->cs[3].pulse); |
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writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), |
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&smc->cs[3].cycle); |
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
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AT91_SMC_MODE_EXNW_DISABLE | |
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AT91_SMC_MODE_DBW_8 | |
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AT91_SMC_MODE_TDF_CYCLE(3), |
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&smc->cs[3].mode); |
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writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer); |
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#ifdef CONFIG_SYS_NAND_READY_PIN |
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/* Configure RDY/BSY */ |
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
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#endif |
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/* Enable NandFlash */ |
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
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} |
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#endif |
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#ifdef CONFIG_MACB |
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static void pm9g45_macb_hw_init(void) |
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{ |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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/*
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* PD2 enables the 50MHz oscillator for Ethernet PHY |
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* 1 - enable |
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* 0 - disable |
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*/ |
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at91_set_pio_output(AT91_PIO_PORTD, 2, 1); |
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at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ |
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/* Enable clock */ |
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writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer); |
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/*
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* Disable pull-up on: |
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* RXDV (PA15) => PHY normal mode (not Test mode) |
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* ERX0 (PA12) => PHY ADDR0 |
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* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 |
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* |
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* PHY has internal pull-down |
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*/ |
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); |
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); |
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); |
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/* Re-enable pull-up */ |
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at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); |
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at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); |
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at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); |
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at91_macb_hw_init(); |
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} |
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#endif |
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int board_init(void) |
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{ |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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/* Enable Ctrlc */ |
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console_init_f(); |
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writel((1 << AT91SAM9G45_ID_PIOA) | |
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(1 << AT91SAM9G45_ID_PIOB) | |
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(1 << AT91SAM9G45_ID_PIOC) | |
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(1 << AT91SAM9G45_ID_PIODE), &pmc->pcer); |
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/* arch number of AT91SAM9M10G45EK-Board */ |
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gd->bd->bi_arch_number = MACH_TYPE_PM9G45; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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at91_serial_hw_init(); |
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#ifdef CONFIG_CMD_NAND |
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pm9g45_nand_hw_init(); |
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#endif |
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#ifdef CONFIG_MACB |
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pm9g45_macb_hw_init(); |
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#endif |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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#ifdef CONFIG_RESET_PHY_R |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_MACB |
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/*
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* Initialize ethernet HW addr prior to starting Linux, |
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* needed for nfsroot |
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*/ |
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eth_init(gd->bd); |
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#endif |
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} |
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#endif |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_MACB |
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rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); |
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#endif |
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return rc; |
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} |
@ -0,0 +1,186 @@ |
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/*
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* (C) Copyright 2010 |
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* Ilko Iliev <iliev@ronetix.at> |
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* Asen Dimov <dimov@ronetix.at> |
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* Ronetix GmbH <www.ronetix.at> |
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* |
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* Configuation settings for the PM9G45 board. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
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#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ |
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#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ |
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/* ARM asynchronous clock */ |
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS 1 |
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#define CONFIG_INITRD_TAG 1 |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SKIP_RELOCATE_UBOOT |
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/*
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* Hardware drivers |
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*/ |
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#define CONFIG_AT91_GPIO 1 |
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#define CONFIG_ATMEL_USART 1 |
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#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
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#define CONFIG_SYS_USE_NANDFLASH 1 |
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/* LED */ |
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#define CONFIG_AT91_LED |
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#define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */ |
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#define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */ |
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#define CONFIG_BOOTDELAY 3 |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE 1 |
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#define CONFIG_BOOTP_BOOTPATH 1 |
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#define CONFIG_BOOTP_GATEWAY 1 |
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#define CONFIG_BOOTP_HOSTNAME 1 |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#undef CONFIG_CMD_FPGA |
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#undef CONFIG_CMD_IMLS |
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#define CONFIG_CMD_PING 1 |
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#define CONFIG_CMD_DHCP 1 |
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#define CONFIG_CMD_NAND 1 |
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#define CONFIG_CMD_USB 1 |
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#define CONFIG_CMD_JFFS2 1 |
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#define CONFIG_JFFS2_CMDLINE 1 |
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#define CONFIG_JFFS2_NAND 1 |
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#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ |
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#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ |
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#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ |
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/* SDRAM */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM 0x70000000 |
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
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/* NOR flash, not available */ |
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#define CONFIG_SYS_NO_FLASH 1 |
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#undef CONFIG_CMD_FLASH |
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|
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/* NAND flash */ |
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#ifdef CONFIG_CMD_NAND |
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#define CONFIG_NAND_MAX_CHIPS 1 |
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#define CONFIG_NAND_ATMEL |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_BASE 0x40000000 |
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#define CONFIG_SYS_NAND_DBW_8 1 |
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/* our ALE is AD21 */ |
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
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/* our CLE is AD22 */ |
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 |
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 |
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#endif |
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|
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/* Ethernet */ |
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#define CONFIG_MACB 1 |
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#define CONFIG_RMII 1 |
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#define CONFIG_NET_MULTI 1 |
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#define CONFIG_NET_RETRY_COUNT 20 |
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#define CONFIG_RESET_PHY_R 1 |
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/* USB */ |
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#define CONFIG_USB_ATMEL |
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#define CONFIG_USB_OHCI_NEW 1 |
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#define CONFIG_DOS_PARTITION 1 |
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ |
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" |
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
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#define CONFIG_USB_STORAGE 1 |
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/* board specific(not enough SRAM) */ |
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#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 |
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|
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ |
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
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#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE |
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|
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/* bootstrap + u-boot + env + linux in nandflash */ |
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#define CONFIG_ENV_IS_IN_NAND 1 |
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#define CONFIG_ENV_OFFSET 0x60000 |
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#define CONFIG_ENV_OFFSET_REDUND 0x80000 |
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
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#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" |
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#define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \ |
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"console=ttyS0,115200 " \
|
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"root=/dev/mtdblock4 " \
|
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"mtdparts=atmel_nand:128k(bootstrap)ro," \
|
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"256k(uboot)ro,1664k(env)," \
|
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"2M(linux)ro,-(root) rw " \
|
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"rootfstype=jffs2" |
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|
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
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|
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#define CONFIG_SYS_PROMPT "U-Boot> " |
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#define CONFIG_SYS_CBSIZE 256 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_LONGHELP 1 |
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#define CONFIG_CMDLINE_EDITING 1 |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
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|
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/*
|
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ |
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0x1000) |
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
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|
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
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|
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#ifdef CONFIG_USE_IRQ |
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#error CONFIG_USE_IRQ not supported |
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#endif |
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|
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#endif |
Loading…
Reference in new issue