The Turris Omnia is a open-source router created by CZ.NIC. The code is based on the Marvell/db-88f6820-gp by Stefan Roese with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot repository, which can be found at https://gitlab.labs.nic.cz/turris/turris-omnia-uboot By default, the Turris Omnia uses btrfs as the main and only filesystem, and also loads kernel and device tree from this filesystem. Since U-Boot does not yet support btrfs, you should not flash your Turris Omnia board with this unless you know what you are doing. Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz> Signed-off-by: Marek Behun <marek.behun@nic.cz> create mode 100644 board/CZ.NIC/turris_omnia/Makefile create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c create mode 100644 configs/turris_omnia_defconfig create mode 100644 include/configs/turris_omnia.h Signed-off-by: Stefan Roese <sr@denx.de>master
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#
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# Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := turris_omnia.o
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# |
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# Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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# |
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# Armada XP uses version 1 image format |
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VERSION 1 |
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# Boot Media configurations |
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BOOT_FROM spi |
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# Binary Header (bin_hdr) with DDR3 training code |
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BINARY spl/u-boot-spl.bin 0000005b 00000068 |
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/*
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* Copyright (C) 2017 Marek Behun <marek.behun@nic.cz> |
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* Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz> |
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* |
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* Derived from the code for |
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* Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <dm/uclass.h> |
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#include <fdt_support.h> |
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#include <time.h> |
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#ifdef CONFIG_ATSHA204A |
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# include <atsha204a-i2c.h> |
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#endif |
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#ifdef CONFIG_WDT_ORION |
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# include <wdt.h> |
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#endif |
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#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" |
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#include <../serdes/a38x/high_speed_env_spec.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" |
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#define OMNIA_I2C_EEPROM 0x54 |
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#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 |
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#define OMNIA_I2C_EEPROM_ADDRLEN 2 |
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#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 |
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#define OMNIA_I2C_MCU_DM_NAME "i2c@0" |
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#define OMNIA_I2C_MCU_ADDR_STATUS 0x1 |
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#define OMNIA_I2C_MCU_SATA 0x20 |
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#define OMNIA_I2C_MCU_CARDDET 0x10 |
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#define OMNIA_I2C_MCU 0x2a |
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#define OMNIA_I2C_MCU_WDT_ADDR 0x0b |
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#define OMNIA_ATSHA204_OTP_VERSION 0 |
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#define OMNIA_ATSHA204_OTP_SERIAL 1 |
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#define OMNIA_ATSHA204_OTP_MAC0 3 |
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#define OMNIA_ATSHA204_OTP_MAC1 4 |
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#define MVTWSI_ARMADA_DEBUG_REG 0x8c |
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/*
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* Those values and defines are taken from the Marvell U-Boot version |
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* "u-boot-2013.01-2014_T3.0" |
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*/ |
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#define OMNIA_GPP_OUT_ENA_LOW \ |
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(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
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BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
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BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) |
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#define OMNIA_GPP_OUT_ENA_MID \ |
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(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
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BIT(16) | BIT(17) | BIT(18))) |
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#define OMNIA_GPP_OUT_VAL_LOW 0x0 |
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#define OMNIA_GPP_OUT_VAL_MID 0x0 |
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#define OMNIA_GPP_POL_LOW 0x0 |
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#define OMNIA_GPP_POL_MID 0x0 |
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static struct serdes_map board_serdes_map_pex[] = { |
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{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
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{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} |
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}; |
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static struct serdes_map board_serdes_map_sata[] = { |
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{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
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{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} |
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}; |
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static bool omnia_detect_sata(void) |
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{ |
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struct udevice *bus, *dev; |
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int ret; |
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u16 mode; |
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puts("SERDES0 card detect: "); |
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if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { |
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puts("Cannot find MCU bus!\n"); |
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return false; |
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} |
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ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); |
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if (ret) { |
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puts("Cannot get MCU chip!\n"); |
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return false; |
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} |
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ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); |
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if (ret) { |
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puts("I2C read failed! Default PEX\n"); |
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return false; |
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} |
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if (!(mode & OMNIA_I2C_MCU_CARDDET)) { |
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puts("NONE\n"); |
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return false; |
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} |
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if (mode & OMNIA_I2C_MCU_SATA) { |
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puts("SATA\n"); |
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return true; |
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} else { |
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puts("PEX\n"); |
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return false; |
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} |
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} |
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) |
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{ |
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if (omnia_detect_sata()) { |
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*serdes_map_array = board_serdes_map_sata; |
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*count = ARRAY_SIZE(board_serdes_map_sata); |
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} else { |
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*serdes_map_array = board_serdes_map_pex; |
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*count = ARRAY_SIZE(board_serdes_map_pex); |
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} |
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return 0; |
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} |
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struct omnia_eeprom { |
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u32 magic; |
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u32 ramsize; |
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char region[4]; |
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u32 crc; |
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}; |
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static bool omnia_read_eeprom(struct omnia_eeprom *oep) |
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{ |
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struct udevice *bus, *dev; |
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int ret, crc, retry = 3; |
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if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { |
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puts("Cannot find EEPROM bus\n"); |
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return false; |
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} |
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ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); |
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if (ret) { |
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puts("Cannot get EEPROM chip\n"); |
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return false; |
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} |
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for (; retry > 0; --retry) { |
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ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); |
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if (ret) |
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continue; |
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if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { |
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puts("I2C EEPROM missing magic number!\n"); |
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continue; |
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} |
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crc = crc32(0, (unsigned char *) oep, |
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sizeof(struct omnia_eeprom) - 4); |
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if (crc == oep->crc) { |
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break; |
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} else { |
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printf("CRC of EEPROM memory config failed! " |
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"calc=0x%04x saved=0x%04x\n", crc, oep->crc); |
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} |
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} |
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if (!retry) { |
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puts("I2C EEPROM read failed!\n"); |
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return false; |
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} |
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return true; |
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} |
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/*
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* Define the DDR layout / topology here in the board file. This will |
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* be used by the DDR3 init code in the SPL U-Boot version to configure |
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* the DDR3 controller. |
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*/ |
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static struct hws_topology_map board_topology_map_1g = { |
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0x1, /* active interfaces */ |
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ |
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{ { { {0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0} }, |
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SPEED_BIN_DDR_1600K, /* speed_bin */ |
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BUS_WIDTH_16, /* memory_width */ |
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MEM_4G, /* mem_size */ |
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DDR_FREQ_800, /* frequency */ |
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0, 0, /* cas_l cas_wl */ |
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HWS_TEMP_NORMAL, /* temperature */ |
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HWS_TIM_2T} }, /* timing (force 2t) */ |
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5, /* Num Of Bus Per Interface*/ |
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BUS_MASK_32BIT /* Busses mask */ |
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}; |
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static struct hws_topology_map board_topology_map_2g = { |
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0x1, /* active interfaces */ |
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ |
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{ { { {0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0}, |
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{0x1, 0, 0, 0} }, |
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SPEED_BIN_DDR_1600K, /* speed_bin */ |
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BUS_WIDTH_16, /* memory_width */ |
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MEM_8G, /* mem_size */ |
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DDR_FREQ_800, /* frequency */ |
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0, 0, /* cas_l cas_wl */ |
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HWS_TEMP_NORMAL, /* temperature */ |
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HWS_TIM_2T} }, /* timing (force 2t) */ |
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5, /* Num Of Bus Per Interface*/ |
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BUS_MASK_32BIT /* Busses mask */ |
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}; |
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struct hws_topology_map *ddr3_get_topology_map(void) |
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{ |
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static int mem = 0; |
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struct omnia_eeprom oep; |
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/* Get the board config from EEPROM */ |
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if (mem == 0) { |
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if(!omnia_read_eeprom(&oep)) |
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goto out; |
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printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); |
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if (oep.ramsize == 0x2) |
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mem = 2; |
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else |
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mem = 1; |
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} |
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out: |
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/* Hardcoded fallback */ |
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if (mem == 0) { |
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puts("WARNING: Memory config from EEPROM read failed.\n"); |
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puts("Falling back to default 1GiB map.\n"); |
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mem = 1; |
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} |
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/* Return the board topology as defined in the board code */ |
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if (mem == 1) |
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return &board_topology_map_1g; |
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if (mem == 2) |
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return &board_topology_map_2g; |
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return &board_topology_map_1g; |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static int set_regdomain(void) |
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{ |
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struct omnia_eeprom oep; |
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char rd[3] = {' ', ' ', 0}; |
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if (omnia_read_eeprom(&oep)) |
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memcpy(rd, &oep.region, 2); |
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else |
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puts("EEPROM regdomain read failed.\n"); |
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printf("Regdomain set to %s\n", rd); |
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return setenv("regdomain", rd); |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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u32 i2c_debug_reg; |
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/* Configure MPP */ |
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writel(0x11111111, MVEBU_MPP_BASE + 0x00); |
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writel(0x11111111, MVEBU_MPP_BASE + 0x04); |
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writel(0x11244011, MVEBU_MPP_BASE + 0x08); |
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writel(0x22222111, MVEBU_MPP_BASE + 0x0c); |
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writel(0x22200002, MVEBU_MPP_BASE + 0x10); |
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writel(0x30042022, MVEBU_MPP_BASE + 0x14); |
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writel(0x55550555, MVEBU_MPP_BASE + 0x18); |
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writel(0x00005550, MVEBU_MPP_BASE + 0x1c); |
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/* Set GPP Out value */ |
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writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); |
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writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); |
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/* Set GPP Polarity */ |
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writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); |
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writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); |
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/* Set GPP Out Enable */ |
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writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
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writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); |
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/* Disable I2C debug mode blocking 0x64 I2C address */ |
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i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); |
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i2c_debug_reg &= ~(1<<18); |
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writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); |
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return 0; |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static bool disable_mcu_watchdog(void) |
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{ |
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struct udevice *bus, *dev; |
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int ret, retry = 3; |
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uchar buf[1] = {0x0}; |
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if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { |
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puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); |
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return false; |
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} |
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ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); |
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if (ret) { |
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puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); |
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return false; |
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} |
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for (; retry > 0; --retry) |
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if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) |
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break; |
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if (retry <= 0) { |
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puts("I2C MCU watchdog failed to disable!\n"); |
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return false; |
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} |
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return true; |
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} |
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#endif |
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) |
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static struct udevice *watchdog_dev = NULL; |
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#endif |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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#ifndef CONFIG_SPL_BUILD |
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# ifdef CONFIG_WDT_ORION |
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { |
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puts("Cannot find Armada 385 watchdog!\n"); |
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} else { |
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puts("Enabling Armada 385 watchdog.\n"); |
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wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); |
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} |
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# endif |
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if (disable_mcu_watchdog()) |
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puts("Disabled MCU startup watchdog.\n"); |
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set_regdomain(); |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_WATCHDOG |
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/* Called by macro WATCHDOG_RESET */ |
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void watchdog_reset(void) |
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{ |
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# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) |
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static ulong next_reset = 0; |
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ulong now; |
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if (!watchdog_dev) |
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return; |
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now = timer_get_us(); |
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/* Do not reset the watchdog too often */ |
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if (now > next_reset) { |
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wdt_reset(watchdog_dev); |
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next_reset = now + 1000; |
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} |
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# endif |
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} |
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#endif |
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int board_late_init(void) |
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{ |
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#ifndef CONFIG_SPL_BUILD |
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set_regdomain(); |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_ATSHA204A |
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static struct udevice *get_atsha204a_dev(void) |
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{ |
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static struct udevice *dev = NULL; |
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if (dev != NULL) |
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return dev; |
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if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { |
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puts("Cannot find ATSHA204A on I2C bus!\n"); |
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dev = NULL; |
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} |
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return dev; |
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} |
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#endif |
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int checkboard(void) |
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{ |
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u32 version_num, serial_num; |
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int err = 1; |
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#ifdef CONFIG_ATSHA204A |
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struct udevice *dev = get_atsha204a_dev(); |
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if (dev) { |
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err = atsha204a_wakeup(dev); |
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if (err) |
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goto out; |
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err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
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OMNIA_ATSHA204_OTP_VERSION, |
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(u8 *) &version_num); |
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if (err) |
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goto out; |
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err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
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OMNIA_ATSHA204_OTP_SERIAL, |
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(u8 *) &serial_num); |
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if (err) |
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goto out; |
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atsha204a_sleep(dev); |
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} |
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out: |
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#endif |
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if (err) |
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printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); |
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else |
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printf("Board: Turris Omnia SNL %08X%08X\n", |
||||
be32_to_cpu(version_num), be32_to_cpu(serial_num)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void increment_mac(u8 *mac) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 5; i >= 3; i--) { |
||||
mac[i] += 1; |
||||
if (mac[i]) |
||||
break; |
||||
} |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_ATSHA204A |
||||
int err; |
||||
struct udevice *dev = get_atsha204a_dev(); |
||||
u8 mac0[4], mac1[4], mac[6]; |
||||
|
||||
if (!dev) |
||||
goto out; |
||||
|
||||
err = atsha204a_wakeup(dev); |
||||
if (err) |
||||
goto out; |
||||
|
||||
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
||||
OMNIA_ATSHA204_OTP_MAC0, mac0); |
||||
if (err) |
||||
goto out; |
||||
|
||||
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, |
||||
OMNIA_ATSHA204_OTP_MAC1, mac1); |
||||
if (err) |
||||
goto out; |
||||
|
||||
atsha204a_sleep(dev); |
||||
|
||||
mac[0] = mac0[1]; |
||||
mac[1] = mac0[2]; |
||||
mac[2] = mac0[3]; |
||||
mac[3] = mac1[1]; |
||||
mac[4] = mac1[2]; |
||||
mac[5] = mac1[3]; |
||||
|
||||
if (is_valid_ethaddr(mac)) |
||||
eth_setenv_enetaddr("ethaddr", mac); |
||||
|
||||
increment_mac(mac); |
||||
|
||||
if (is_valid_ethaddr(mac)) |
||||
eth_setenv_enetaddr("eth1addr", mac); |
||||
|
||||
increment_mac(mac); |
||||
|
||||
if (is_valid_ethaddr(mac)) |
||||
eth_setenv_enetaddr("eth2addr", mac); |
||||
|
||||
out: |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
@ -0,0 +1,62 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MVEBU=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_TARGET_TURRIS_OMNIA=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y |
||||
CONFIG_SPL_SPI_SUPPORT=y |
||||
CONFIG_SPL_BOOT_DEVICE_SPI=y |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_SPI=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_GO=y |
||||
CONFIG_CMD_RUN=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SAVEENV=y |
||||
CONFIG_CMD_LOADB=y |
||||
CONFIG_CMD_LOADS=y |
||||
CONFIG_CMD_MEMORY=y |
||||
CONFIG_CMD_ECHO=y |
||||
CONFIG_CMD_SETEXPR=y |
||||
# CONFIG_PARTITION_UUIDS is not set |
||||
# CONFIG_SPL_PARTITION_UUIDS is not set |
||||
CONFIG_DOS_PARTITION=y |
||||
CONFIG_SPL_OF_TRANSLATE=y |
||||
CONFIG_MISC=y |
||||
CONFIG_ATSHA204A=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_NS16550=y |
||||
CONFIG_DEBUG_UART_BASE=0xd0012000 |
||||
CONFIG_DEBUG_UART_CLOCK=250000000 |
||||
CONFIG_DEBUG_UART_SHIFT=2 |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_MV=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_EHCI=y |
||||
CONFIG_USB_EHCI_MARVELL=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_WDT=y |
||||
CONFIG_WDT_ORION=y |
||||
CONFIG_ARCH_MISC_INIT=y |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_CMDLINE=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="=> " |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
@ -0,0 +1,178 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Marek Behun <marek.behun@nic.cz> |
||||
* Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_TURRIS_OMNIA_H |
||||
#define _CONFIG_TURRIS_OMNIA_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE |
||||
|
||||
/*
|
||||
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
||||
* for DDR ECC byte filling in the SPL before loading the main |
||||
* U-Boot into it. |
||||
*/ |
||||
#define CONFIG_SYS_TEXT_BASE 0x00800000 |
||||
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
||||
|
||||
/*
|
||||
* Commands configuration |
||||
*/ |
||||
#define CONFIG_CMD_PCI |
||||
|
||||
/* I2C support */ |
||||
#define CONFIG_DM_I2C |
||||
#define CONFIG_I2C_MUX |
||||
#define CONFIG_I2C_MUX_PCA954x |
||||
#define CONFIG_SPL_I2C_MUX |
||||
#define CONFIG_SYS_I2C_MVTWSI |
||||
|
||||
/* Watchdog support */ |
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) |
||||
# define CONFIG_WATCHDOG |
||||
#endif |
||||
|
||||
/* SPI NOR flash default params, used by sf commands */ |
||||
#define CONFIG_SF_DEFAULT_SPEED 1000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
|
||||
/*
|
||||
* SDIO/MMC Card Configuration |
||||
*/ |
||||
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE |
||||
|
||||
/*
|
||||
* SATA/SCSI/AHCI configuration |
||||
*/ |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_SCSI_AHCI |
||||
#define CONFIG_SCSI_AHCI_PLAT |
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1 |
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
||||
CONFIG_SYS_SCSI_MAX_LUN) |
||||
|
||||
/* Additional FS support/configuration */ |
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
/* USB/EHCI configuration */ |
||||
#define CONFIG_EHCI_IS_TDI |
||||
|
||||
/* Environment in SPI NOR flash */ |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET (3*(1 << 18)) /* 768KiB in */ |
||||
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ |
||||
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ |
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */ |
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
||||
|
||||
/* PCIe support */ |
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_PCI_MVEBU |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */ |
||||
#define RELOCATION_LIMITS_ENV_SETTINGS \ |
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0" |
||||
|
||||
/* Defines for SPL */ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_SIZE (140 << 10) |
||||
#define CONFIG_SPL_TEXT_BASE 0x40000030 |
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) |
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) |
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_MALLOC_SIMPLE |
||||
#endif |
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT |
||||
|
||||
#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI |
||||
/* SPL related SPI defines */ |
||||
# define CONFIG_SPL_SPI_LOAD |
||||
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 |
||||
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
||||
#endif |
||||
|
||||
#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC |
||||
/* SPL related MMC defines */ |
||||
# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) |
||||
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS |
||||
# ifdef CONFIG_SPL_BUILD |
||||
# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ |
||||
# endif |
||||
#endif |
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them |
||||
* to enable certain macros |
||||
*/ |
||||
#include "mv-common.h" |
||||
|
||||
/* Include the common distro boot environment */ |
||||
#ifndef CONFIG_SPL_BUILD |
||||
#include <config_distro_defaults.h> |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
||||
#else |
||||
#define BOOT_TARGET_DEVICES_MMC(func) |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_STORAGE |
||||
#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
||||
#else |
||||
#define BOOT_TARGET_DEVICES_USB(func) |
||||
#endif |
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \ |
||||
BOOT_TARGET_DEVICES_MMC(func) \
|
||||
BOOT_TARGET_DEVICES_USB(func) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na) |
||||
|
||||
#define KERNEL_ADDR_R __stringify(0x1000000) |
||||
#define FDT_ADDR_R __stringify(0x2000000) |
||||
#define RAMDISK_ADDR_R __stringify(0x2200000) |
||||
#define SCRIPT_ADDR_R __stringify(0x1800000) |
||||
#define PXEFILE_ADDR_R __stringify(0x1900000) |
||||
|
||||
#define LOAD_ADDRESS_ENV_SETTINGS \ |
||||
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
|
||||
"fdt_addr_r=" FDT_ADDR_R "\0" \
|
||||
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
|
||||
"scriptaddr=" SCRIPT_ADDR_R "\0" \
|
||||
"pxefile_addr_r=" PXEFILE_ADDR_R "\0" |
||||
|
||||
#include <config_distro_bootcmd.h> |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
BOOTENV |
||||
|
||||
#endif /* CONFIG_SPL_BUILD */ |
||||
|
||||
#endif /* _CONFIG_TURRIS_OMNIA_H */ |
Loading…
Reference in new issue