Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>master
rick
7 years ago
committed by
Andes
parent
f5076f8698
commit
b841b6e946
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# Copyright (C) 2011 Andes Technology Corporation
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# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := cpu.o timer.o
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obj-y += lowlevel_init.o
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ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG |
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obj-y += watchdog.o
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endif |
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@ -0,0 +1,45 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* CPU specific code */ |
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#include <common.h> |
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#include <command.h> |
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#include <watchdog.h> |
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#include <asm/cache.h> |
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#include <faraday/ftwdt010_wdt.h> |
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/*
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* cleanup_before_linux() is called just before we call linux |
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* it prepares the processor for linux |
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* |
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* we disable interrupt and caches. |
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*/ |
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int cleanup_before_linux(void) |
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{ |
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disable_interrupts(); |
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/* turn off I/D-cache */ |
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cache_flush(); |
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icache_disable(); |
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dcache_disable(); |
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return 0; |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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disable_interrupts(); |
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panic("AE3XX wdt not support yet.\n"); |
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} |
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@ -0,0 +1,148 @@ |
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/* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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.pic |
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.text |
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#include <common.h> |
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#include <config.h> |
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#include <asm/macro.h> |
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#include <generated/asm-offsets.h> |
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/* |
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* parameters for the SDRAM controller |
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*/ |
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#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) |
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#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) |
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#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) |
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#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) |
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#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) |
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#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) |
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#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 |
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#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 |
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#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 |
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#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 |
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#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR |
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#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR |
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/* |
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* for Orca and Emerald |
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*/ |
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#define BOARD_ID_REG 0x104 |
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#define BOARD_ID_FAMILY_MASK 0xfff000 |
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#define BOARD_ID_FAMILY_V5 0x556000 |
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#define BOARD_ID_FAMILY_K7 0x74b000 |
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/* |
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* parameters for the static memory controller |
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*/ |
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#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) |
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#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) |
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#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG |
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#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING |
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/* |
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* for Orca and Emerald |
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*/ |
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#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) |
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#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 |
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/* |
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* parameters for the pmu controoler |
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*/ |
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#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) |
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/* |
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* numeric 7 segment display |
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*/ |
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.macro led, num |
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write32 CONFIG_DEBUG_LED, \num |
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.endm |
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/* |
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* Waiting for SDRAM to set up |
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*/ |
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.macro wait_sdram
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li $r0, CONFIG_FTSDMC021_BASE |
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1: |
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lwi $r1, [$r0+FTSDMC021_CR2] |
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bnez $r1, 1b |
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.endm |
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.globl mem_init
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mem_init: |
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move $r11, $lp |
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li $r0, SMC_BANK0_CR_A |
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lwi $r1, [$r0+#0x00] |
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ori $r1, $r1, 0x8f0 |
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xori $r1, $r1, 0x8f0 |
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/* 16-bit mode */ |
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ori $r1, $r1, 0x60 |
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li $r2, 0x00153153 |
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swi $r1, [$r0+#0x00] |
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swi $r2, [$r0+#0x04] |
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move $lp, $r11 |
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ret |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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.globl lowlevel_init
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lowlevel_init: |
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move $r10, $lp |
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jal remap |
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) |
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jal enable_fpu |
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#endif |
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ret $r10 |
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remap: |
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move $r11, $lp |
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relo_base: |
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mfusr $r0, $pc |
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#ifdef CONFIG_MEM_REMAP |
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li $r4, 0x00000000 |
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li $r5, 0x80000000 |
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la $r6, _end@GOTOFF
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1: |
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lmw.bim $r12, [$r5], $r19 |
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smw.bim $r12, [$r4], $r19 |
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blt $r5, $r6, 1b |
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#endif /* #ifdef CONFIG_MEM_REMAP */ |
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move $lp, $r11 |
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2: |
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ret |
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/* |
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* enable_fpu: |
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* Some of Andes CPU version support FPU coprocessor, if so, |
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* and toolchain support FPU instruction set, we should enable it. |
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*/ |
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) |
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enable_fpu: |
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mfsr $r0, $CPU_VER /* enable FPU if it exists */ |
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srli $r0, $r0, 3 |
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andi $r0, $r0, 1 |
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beqz $r0, 1f /* skip if no COP */ |
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mfsr $r0, $FUCOP_EXIST |
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srli $r0, $r0, 31 |
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beqz $r0, 1f /* skip if no FPU */ |
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mfsr $r0, $FUCOP_CTL |
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ori $r0, $r0, 1 |
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mtsr $r0, $FUCOP_CTL |
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1: |
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ret |
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#endif |
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#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ |
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@ -0,0 +1,16 @@ |
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/*
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* (C) Copyright 2009 Faraday Technology |
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* Po-Yu Chuang <ratbert@faraday-tech.com> |
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* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef CONFIG_TIMER |
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#include <common.h> |
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#include <asm/io.h> |
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#include <faraday/fttmr010.h> |
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#error "AE3XX timer only support DM flow" |
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#endif /* CONFIG_TIMER */ |
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@ -0,0 +1,17 @@ |
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/* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch-ag101/ag101.h> |
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#include <linux/linkage.h> |
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.text |
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#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG |
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ENTRY(turnoff_watchdog) |
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#error "AE3XX not support wdt yet" |
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ENDPROC(turnoff_watchdog) |
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#endif |
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@ -0,0 +1,65 @@ |
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/dts-v1/; |
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/ { |
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compatible = "nds32 ae3xx"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&intc>; |
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aliases { |
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uart0 = &serial0; |
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} ; |
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chosen { |
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/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ |
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bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; |
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stdout-path = "uart0:38400n8"; |
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tick-timer = &timer0; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x00000000 0x40000000>; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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compatible = "andestech,n13"; |
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reg = <0>; |
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/* FIXME: to fill correct frqeuency */ |
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clock-frequency = <60000000>; |
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}; |
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}; |
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intc: interrupt-controller { |
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compatible = "andestech,atnointc010"; |
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#interrupt-cells = <1>; |
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interrupt-controller; |
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}; |
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serial0: serial@f0300000 { |
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compatible = "andestech,uart16550", "ns16550a"; |
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reg = <0xf0300000 0x1000>; |
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interrupts = <7 4>; |
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clock-frequency = <14745600>; |
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reg-shift = <2>; |
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reg-offset = <32>; |
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no-loopback-test = <1>; |
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}; |
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timer0: timer@f0400000 { |
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compatible = "andestech,atcpit100"; |
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reg = <0xf0400000 0x1000>; |
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interrupts = <2 4>; |
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clock-frequency = <30000000>; |
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}; |
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nor@0,0 { |
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compatible = "cfi-flash"; |
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reg = <0x88000000 0x1000>; |
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bank-width = <2>; |
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device-width = <1>; |
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}; |
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}; |
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@ -0,0 +1,54 @@ |
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/*
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* Copyright (C) 2016 Andes Technology Corporation |
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* Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __AE3XX_H |
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#define __AE3XX_H |
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/* Hardware register bases */ |
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/* Static Memory Controller (SRAM) */ |
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#define CONFIG_FTSMC020_BASE 0xe0400000 |
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/* DMA Controller */ |
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#define CONFIG_FTDMAC020_BASE 0xf0c00000 |
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/* AHB-to-APB Bridge */ |
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#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 |
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/* Reserved */ |
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#define CONFIG_RESERVED_01_BASE 0xe0500000 |
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/* Reserved */ |
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#define CONFIG_RESERVED_02_BASE 0xf0800000 |
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/* Reserved */ |
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#define CONFIG_RESERVED_03_BASE 0xf0900000 |
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/* Ethernet */ |
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#define CONFIG_FTMAC100_BASE 0xe0100000 |
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/* Reserved */ |
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#define CONFIG_RESERVED_04_BASE 0xf1000000 |
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/* APB Device definitions */ |
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/* UART1 */ |
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#define CONFIG_FTUART010_01_BASE 0xf0200000 |
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/* UART2 */ |
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#define CONFIG_FTUART010_02_BASE 0xf0300000 |
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/* Counter/Timers */ |
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#define CONFIG_FTTMR010_BASE 0xf0400000 |
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/* Watchdog Timer */ |
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#define CONFIG_FTWDT010_BASE 0xf0500000 |
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/* Real Time Clock */ |
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#define CONFIG_FTRTC010_BASE 0xf0600000 |
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/* GPIO */ |
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#define CONFIG_FTGPIO010_BASE 0xf0700000 |
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/* I2C */ |
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#define CONFIG_FTIIC010_BASE 0xf0a00000 |
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/* SD Controller */ |
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#define CONFIG_FTSDC010_BASE 0xf0e00000 |
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/* The following address was not defined in Linux */ |
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/* Synchronous Serial Port Controller (SSP) 01 */ |
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#define CONFIG_FTSSP010_01_BASE 0xf0d00000 |
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#endif /* __AE3XX_H */ |
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@ -0,0 +1,65 @@ |
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/*
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* Copyright (c) 2013, Google Inc. |
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* |
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* Copyright (C) 2011 |
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef NDS32_BOOTM_H |
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#define NDS32_BOOTM_H |
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extern void udc_disconnect(void); |
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#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ |
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defined(CONFIG_CMDLINE_TAG) || \
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defined(CONFIG_INITRD_TAG) || \
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defined(CONFIG_SERIAL_TAG) || \
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defined(CONFIG_REVISION_TAG) |
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# define BOOTM_ENABLE_TAGS 1 |
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#else |
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# define BOOTM_ENABLE_TAGS 0 |
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#endif |
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#ifdef CONFIG_SETUP_MEMORY_TAGS |
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# define BOOTM_ENABLE_MEMORY_TAGS 1 |
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#else |
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# define BOOTM_ENABLE_MEMORY_TAGS 0 |
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#endif |
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#ifdef CONFIG_CMDLINE_TAG |
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#define BOOTM_ENABLE_CMDLINE_TAG 1 |
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#else |
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#define BOOTM_ENABLE_CMDLINE_TAG 0 |
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#endif |
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#ifdef CONFIG_INITRD_TAG |
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#define BOOTM_ENABLE_INITRD_TAG 1 |
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#else |
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#define BOOTM_ENABLE_INITRD_TAG 0 |
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#endif |
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#ifdef CONFIG_SERIAL_TAG |
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#define BOOTM_ENABLE_SERIAL_TAG 1 |
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void get_board_serial(struct tag_serialnr *serialnr); |
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#else |
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#define BOOTM_ENABLE_SERIAL_TAG 0 |
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static inline void get_board_serial(struct tag_serialnr *serialnr) |
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{ |
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} |
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#endif |
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#ifdef CONFIG_REVISION_TAG |
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#define BOOTM_ENABLE_REVISION_TAG 1 |
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u32 get_board_rev(void); |
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#else |
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#define BOOTM_ENABLE_REVISION_TAG 0 |
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static inline u32 get_board_rev(void) |
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{ |
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return 0; |
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} |
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#endif |
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#endif |
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@ -0,0 +1,20 @@ |
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/*
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* Copyright (C) 2011 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned long do_go_exec(ulong (*entry)(int, char * const []), |
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int argc, char * const argv[]) |
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{ |
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cleanup_before_linux(); |
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return entry(argc, argv); |
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} |
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@ -0,0 +1,18 @@ |
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if TARGET_ADP_AE3XX |
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config SYS_CPU |
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default "n1213" |
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config SYS_BOARD |
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default "adp-ae3xx" |
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config SYS_VENDOR |
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default "AndesTech" |
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config SYS_SOC |
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default "ae3xx" |
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config SYS_CONFIG_NAME |
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default "adp-ae3xx" |
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endif |
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@ -0,0 +1,6 @@ |
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ADP-AG101P BOARD |
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M: Andes <uboot@andestech.com> |
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S: Maintained |
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F: board/AndesTech/adp-ae3xx/ |
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F: include/configs/adp-ae3xx.h |
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F: configs/adp-ae3xx_defconfig |
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@ -0,0 +1,8 @@ |
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#
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# Copyright (C) 2016 Andes Technology Corporation
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := adp-ae3xx.o
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@ -0,0 +1,86 @@ |
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/*
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#if defined(CONFIG_FTMAC100) |
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#include <netdev.h> |
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#endif |
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#include <linux/io.h> |
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#include <faraday/ftsdc010.h> |
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#include <faraday/ftsmc020.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscellaneous platform dependent initializations |
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*/ |
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int board_init(void) |
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{ |
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/*
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* refer to BOOT_PARAMETER_PA_BASE within |
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* "linux/arch/nds32/include/asm/misc_spec.h" |
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*/ |
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printf("Board: %s\n" , CONFIG_SYS_BOARD); |
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gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX; |
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gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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unsigned long sdram_base = PHYS_SDRAM_0; |
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unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; |
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unsigned long actual_size; |
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actual_size = get_ram_size((void *)sdram_base, expected_size); |
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gd->ram_size = actual_size; |
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if (expected_size != actual_size) { |
||||
printf("Warning: Only %lu of %lu MiB SDRAM is working\n", |
||||
actual_size >> 20, expected_size >> 20); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_0; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_FTMAC100) |
||||
int board_eth_init(bd_t *bd) |
||||
{ |
||||
return ftmac100_initialize(bd); |
||||
} |
||||
#endif |
||||
|
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
||||
{ |
||||
if (banknum == 0) { /* non-CFI boot flash */ |
||||
info->portwidth = FLASH_CFI_8BIT; |
||||
info->chipwidth = FLASH_CFI_BY8; |
||||
info->interface = FLASH_CFI_X8; |
||||
return 1; |
||||
} else { |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
#ifndef CONFIG_DM_MMC |
||||
#ifdef CONFIG_FTSDC010 |
||||
ftsdc010_mmc_init(0); |
||||
#endif |
||||
#endif |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,25 @@ |
||||
CONFIG_NDS32=y |
||||
CONFIG_TARGET_ADP_AE3XX=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ae3xx" |
||||
CONFIG_FIT=y |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_SYS_PROMPT="NDS32 # " |
||||
CONFIG_CMD_MMC=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_DATE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_MMC=y |
||||
CONFIG_MTD_NOR_FLASH=y |
||||
CONFIG_BAUDRATE=38400 |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_MTD=y |
||||
CONFIG_CFI_FLASH=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_AE3XX_TIMER=y |
||||
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Andestech ATCPIT100 timer driver |
||||
* |
||||
* (C) Copyright 2016 |
||||
* Rick Chen, NDS32 Software Engineering, rick@andestech.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <timer.h> |
||||
#include <linux/io.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2))) |
||||
|
||||
/*
|
||||
* Definition of register offsets |
||||
*/ |
||||
|
||||
/* ID and Revision Register */ |
||||
#define ID_REV 0x0 |
||||
|
||||
/* Configuration Register */ |
||||
#define CFG 0x10 |
||||
|
||||
/* Interrupt Enable Register */ |
||||
#define INT_EN 0x14 |
||||
#define CH_INT_EN(c , i) ((1<<i)<<(4*c)) |
||||
|
||||
/* Interrupt Status Register */ |
||||
#define INT_STA 0x18 |
||||
#define CH_INT_STA(c , i) ((1<<i)<<(4*c)) |
||||
|
||||
/* Channel Enable Register */ |
||||
#define CH_EN 0x1C |
||||
#define CH_TMR_EN(c , t) ((1<<t)<<(4*c)) |
||||
|
||||
/* Ch n Control REgister */ |
||||
#define CH_CTL(n) (0x20+0x10*n) |
||||
/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ |
||||
#define APB_CLK (1<<3) |
||||
/* Channel mode , bit 0~2 */ |
||||
#define TMR_32 1 |
||||
#define TMR_16 2 |
||||
#define TMR_8 3 |
||||
#define PWM 4 |
||||
|
||||
#define CH_REL(n) (0x24+0x10*n) |
||||
#define CH_CNT(n) (0x28+0x10*n) |
||||
|
||||
struct atctmr_timer_regs { |
||||
u32 id_rev; /* 0x00 */ |
||||
u32 reservd[3]; /* 0x04 ~ 0x0c */ |
||||
u32 cfg; /* 0x10 */ |
||||
u32 int_en; /* 0x14 */ |
||||
u32 int_st; /* 0x18 */ |
||||
u32 ch_en; /* 0x1c */ |
||||
u32 ch0_ctrl; /* 0x20 */ |
||||
u32 ch0_reload; /* 0x24 */ |
||||
u32 ch0_cntr; /* 0x28 */ |
||||
u32 reservd1; /* 0x2c */ |
||||
u32 ch1_ctrl; /* 0x30 */ |
||||
u32 ch1_reload; /* 0x34 */ |
||||
u32 int_mask; /* 0x38 */ |
||||
}; |
||||
|
||||
struct atftmr_timer_platdata { |
||||
unsigned long *regs; |
||||
}; |
||||
|
||||
static int atftmr_timer_get_count(struct udevice *dev, u64 *count) |
||||
{ |
||||
struct atftmr_timer_platdata *plat = dev->platdata; |
||||
u32 val; |
||||
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); |
||||
*count = timer_conv_64(val); |
||||
return 0; |
||||
} |
||||
|
||||
static int atctmr_timer_probe(struct udevice *dev) |
||||
{ |
||||
struct atftmr_timer_platdata *plat = dev->platdata; |
||||
REG32_TMR(CH_REL(1)) = 0xffffffff; |
||||
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; |
||||
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); |
||||
return 0; |
||||
} |
||||
|
||||
static int atctme_timer_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct atftmr_timer_platdata *plat = dev_get_platdata(dev); |
||||
plat->regs = map_physmem(dev_get_addr(dev) , 0x100 , MAP_NOCACHE); |
||||
return 0; |
||||
} |
||||
|
||||
static const struct timer_ops ag101p_timer_ops = { |
||||
.get_count = atftmr_timer_get_count, |
||||
}; |
||||
|
||||
static const struct udevice_id ag101p_timer_ids[] = { |
||||
{ .compatible = "andestech,atcpit100" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(altera_timer) = { |
||||
.name = "ae3xx_timer", |
||||
.id = UCLASS_TIMER, |
||||
.of_match = ag101p_timer_ids, |
||||
.ofdata_to_platdata = atctme_timer_ofdata_to_platdata, |
||||
.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), |
||||
.probe = atctmr_timer_probe, |
||||
.ops = &ag101p_timer_ops, |
||||
.flags = DM_FLAG_PRE_RELOC, |
||||
}; |
||||
@ -0,0 +1,260 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch-ae3xx/ae3xx.h> |
||||
|
||||
/*
|
||||
* CPU and Board Configuration Options |
||||
*/ |
||||
#define CONFIG_USE_INTERRUPT |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
#define CONFIG_SKIP_TRUNOFF_WATCHDOG |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_PANIC_HANG |
||||
|
||||
#define CONFIG_SYS_ICACHE_OFF |
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_BOOTP_SERVERIP |
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SYS_TEXT_BASE 0x00500000 |
||||
#ifdef CONFIG_OF_CONTROL |
||||
#undef CONFIG_OF_SEPARATE |
||||
#define CONFIG_OF_EMBED |
||||
#endif |
||||
#else |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Timer |
||||
*/ |
||||
#define CONFIG_SYS_CLK_FREQ 39062500 |
||||
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ |
||||
|
||||
/*
|
||||
* Use Externel CLOCK or PCLK |
||||
*/ |
||||
#undef CONFIG_FTRTC010_EXTCLK |
||||
|
||||
#ifndef CONFIG_FTRTC010_EXTCLK |
||||
#define CONFIG_FTRTC010_PCLK |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FTRTC010_EXTCLK |
||||
#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ |
||||
#else |
||||
#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ |
||||
#endif |
||||
|
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
|
||||
/*
|
||||
* Real Time Clock |
||||
*/ |
||||
#define CONFIG_RTC_FTRTC010 |
||||
|
||||
/*
|
||||
* Real Time Clock Divider |
||||
* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
||||
*/ |
||||
#define OSC_5MHZ (5*1000000) |
||||
#define OSC_CLK (4*OSC_5MHZ) |
||||
#define RTC_DIV_COUNT (0.5) /* Why?? */ |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
|
||||
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE |
||||
#ifndef CONFIG_DM_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#endif |
||||
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ |
||||
|
||||
/*
|
||||
* Ethernet |
||||
*/ |
||||
#define CONFIG_FTMAC100 |
||||
|
||||
/*
|
||||
* SD (MMC) controller |
||||
*/ |
||||
#define CONFIG_FTSDC010 |
||||
#define CONFIG_FTSDC010_NUMBER 1 |
||||
#define CONFIG_FTSDC010_SDIO |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/* max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
|
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ |
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10) |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
||||
|
||||
#define PHYS_SDRAM_1 \ |
||||
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ |
||||
|
||||
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ |
||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Load address and memory test area should agree with |
||||
* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. |
||||
*/ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x300000 |
||||
|
||||
/* memtest works on 63 MB in DRAM */ |
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 |
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) |
||||
|
||||
/*
|
||||
* Static memory controller configuration |
||||
*/ |
||||
#define CONFIG_FTSMC020 |
||||
|
||||
#ifdef CONFIG_FTSMC020 |
||||
#include <faraday/ftsmc020.h> |
||||
|
||||
#define CONFIG_SYS_FTSMC020_CONFIGS { \ |
||||
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
|
||||
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
||||
} |
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ |
||||
#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||
FTSMC020_BANK_SIZE_32M | \
|
||||
FTSMC020_BANK_MBW_32) |
||||
|
||||
#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ |
||||
FTSMC020_TPR_AST(1) | \
|
||||
FTSMC020_TPR_CTW(1) | \
|
||||
FTSMC020_TPR_ATI(1) | \
|
||||
FTSMC020_TPR_AT2(1) | \
|
||||
FTSMC020_TPR_WTC(1) | \
|
||||
FTSMC020_TPR_AHT(1) | \
|
||||
FTSMC020_TPR_TRNA(1)) |
||||
#endif |
||||
|
||||
/*
|
||||
* FLASH on ADP_AG101P is connected to BANK0 |
||||
* Just disalbe the other BANK to avoid detection error. |
||||
*/ |
||||
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
|
||||
FTSMC020_BANK_SIZE_32M | \
|
||||
FTSMC020_BANK_MBW_32) |
||||
|
||||
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ |
||||
FTSMC020_TPR_CTW(3) | \
|
||||
FTSMC020_TPR_ATI(0xf) | \
|
||||
FTSMC020_TPR_AT2(3) | \
|
||||
FTSMC020_TPR_WTC(3) | \
|
||||
FTSMC020_TPR_AHT(3) | \
|
||||
FTSMC020_TPR_TRNA(0xf)) |
||||
|
||||
#define FTSMC020_BANK1_CONFIG (0x00) |
||||
#define FTSMC020_BANK1_TIMING (0x00) |
||||
#endif /* CONFIG_FTSMC020 */ |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
/* use CFI framework */ |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL |
||||
|
||||
/* support JEDEC */ |
||||
#ifdef CONFIG_CFI_FLASH |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
||||
#endif |
||||
|
||||
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ |
||||
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ |
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } |
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ |
||||
|
||||
/* max number of memory banks */ |
||||
/*
|
||||
* There are 4 banks supported for this Controller, |
||||
* but we have only 1 bank connected to flash on board |
||||
*/ |
||||
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#endif |
||||
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} |
||||
|
||||
/* max number of sectors on one chip */ |
||||
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) |
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||
|
||||
/* environments */ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) |
||||
#define CONFIG_ENV_SIZE 8192 |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 16 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
|
||||
/* Initial Memory map for Linux*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) |
||||
/* Increase max gunzip size */ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue