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@ -151,11 +151,13 @@ |
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#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ |
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#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ |
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/* values for memcfga register - indirect addressing of these regs */ |
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#ifndef CONFIG_405EP |
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#define mem_besra 0x00 /* bus error syndrome reg a */ |
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#define mem_besrsa 0x04 /* bus error syndrome reg set a */ |
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#define mem_besrb 0x08 /* bus error syndrome reg b */ |
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#define mem_besrsb 0x0c /* bus error syndrome reg set b */ |
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#define mem_bear 0x10 /* bus error address reg */ |
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#endif |
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#define mem_mcopt1 0x20 /* memory controller options 1 */ |
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#define mem_rtr 0x30 /* refresh timer reg */ |
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#define mem_pmit 0x34 /* power management idle timer */ |
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@ -164,8 +166,10 @@ |
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#define mem_mb2cf 0x48 /* memory bank 2 configuration */ |
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#define mem_mb3cf 0x4c /* memory bank 3 configuration */ |
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#define mem_sdtr1 0x80 /* timing reg 1 */ |
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#ifndef CONFIG_405EP |
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#define mem_ecccf 0x94 /* ECC configuration */ |
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#define mem_eccerr 0x98 /* ECC error status */ |
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#endif |
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/******************************************************************************
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* Decompression Controller |
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@ -227,6 +231,255 @@ |
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#define pbesr1 0x22 /* periph bus error status reg 1 */ |
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#define epcr 0x23 /* external periph control reg */ |
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#ifdef CONFIG_405EP |
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/******************************************************************************
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* Control |
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******************************************************************************/ |
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#define CNTRL_DCR_BASE 0x0f0 |
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#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ |
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#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ |
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#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ |
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#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ |
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#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ |
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#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ |
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ |
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ |
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ |
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ |
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#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ |
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#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ |
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#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ |
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#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ |
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#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ |
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#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ |
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/* Bit definitions */ |
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#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ |
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#define PLLMR0_CPU_DIV_BYPASS 0x00000000 |
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#define PLLMR0_CPU_DIV_2 0x00100000 |
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#define PLLMR0_CPU_DIV_3 0x00200000 |
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#define PLLMR0_CPU_DIV_4 0x00300000 |
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#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ |
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#define PLLMR0_CPU_PLB_DIV_1 0x00000000 |
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#define PLLMR0_CPU_PLB_DIV_2 0x00010000 |
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#define PLLMR0_CPU_PLB_DIV_3 0x00020000 |
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#define PLLMR0_CPU_PLB_DIV_4 0x00030000 |
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#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ |
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#define PLLMR0_OPB_PLB_DIV_1 0x00000000 |
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#define PLLMR0_OPB_PLB_DIV_2 0x00001000 |
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#define PLLMR0_OPB_PLB_DIV_3 0x00002000 |
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#define PLLMR0_OPB_PLB_DIV_4 0x00003000 |
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#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ |
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#define PLLMR0_EXB_PLB_DIV_2 0x00000000 |
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#define PLLMR0_EXB_PLB_DIV_3 0x00000100 |
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#define PLLMR0_EXB_PLB_DIV_4 0x00000200 |
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#define PLLMR0_EXB_PLB_DIV_5 0x00000300 |
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#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ |
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#define PLLMR0_MAL_PLB_DIV_1 0x00000000 |
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#define PLLMR0_MAL_PLB_DIV_2 0x00000010 |
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#define PLLMR0_MAL_PLB_DIV_3 0x00000020 |
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#define PLLMR0_MAL_PLB_DIV_4 0x00000030 |
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#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ |
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#define PLLMR0_PCI_PLB_DIV_1 0x00000000 |
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#define PLLMR0_PCI_PLB_DIV_2 0x00000001 |
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#define PLLMR0_PCI_PLB_DIV_3 0x00000002 |
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#define PLLMR0_PCI_PLB_DIV_4 0x00000003 |
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#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ |
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#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ |
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#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ |
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#define PLLMR1_FBMUL_DIV_16 0x00000000 |
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#define PLLMR1_FBMUL_DIV_1 0x00100000 |
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#define PLLMR1_FBMUL_DIV_2 0x00200000 |
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#define PLLMR1_FBMUL_DIV_3 0x00300000 |
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#define PLLMR1_FBMUL_DIV_4 0x00400000 |
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#define PLLMR1_FBMUL_DIV_5 0x00500000 |
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#define PLLMR1_FBMUL_DIV_6 0x00600000 |
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#define PLLMR1_FBMUL_DIV_7 0x00700000 |
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#define PLLMR1_FBMUL_DIV_8 0x00800000 |
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#define PLLMR1_FBMUL_DIV_9 0x00900000 |
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#define PLLMR1_FBMUL_DIV_10 0x00A00000 |
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#define PLLMR1_FBMUL_DIV_11 0x00B00000 |
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#define PLLMR1_FBMUL_DIV_12 0x00C00000 |
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#define PLLMR1_FBMUL_DIV_13 0x00D00000 |
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#define PLLMR1_FBMUL_DIV_14 0x00E00000 |
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#define PLLMR1_FBMUL_DIV_15 0x00F00000 |
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#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ |
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#define PLLMR1_FWDVA_DIV_8 0x00000000 |
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#define PLLMR1_FWDVA_DIV_7 0x00010000 |
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#define PLLMR1_FWDVA_DIV_6 0x00020000 |
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#define PLLMR1_FWDVA_DIV_5 0x00030000 |
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#define PLLMR1_FWDVA_DIV_4 0x00040000 |
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#define PLLMR1_FWDVA_DIV_3 0x00050000 |
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#define PLLMR1_FWDVA_DIV_2 0x00060000 |
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#define PLLMR1_FWDVA_DIV_1 0x00070000 |
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#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ |
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#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ |
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/* Defines for CPC0_EPRCSR register */ |
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#define CPC0_EPRCSR_E0NFE 0x80000000 |
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#define CPC0_EPRCSR_E1NFE 0x40000000 |
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#define CPC0_EPRCSR_E1RPP 0x00000080 |
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#define CPC0_EPRCSR_E0RPP 0x00000040 |
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#define CPC0_EPRCSR_E1ERP 0x00000020 |
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#define CPC0_EPRCSR_E0ERP 0x00000010 |
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#define CPC0_EPRCSR_E1PCI 0x00000002 |
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#define CPC0_EPRCSR_E0PCI 0x00000001 |
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/* Defines for CPC0_PCI Register */ |
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#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ |
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#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ |
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#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ |
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/* Defines for CPC0_BOOR Register */ |
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#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ |
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/* Defines for CPC0_PLLMR1 Register fields */ |
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#define PLL_ACTIVE 0x80000000 |
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#define CPC0_PLLMR1_SSCS 0x80000000 |
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#define PLL_RESET 0x40000000 |
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#define CPC0_PLLMR1_PLLR 0x40000000 |
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/* Feedback multiplier */ |
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#define PLL_FBKDIV 0x00F00000 |
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#define CPC0_PLLMR1_FBDV 0x00F00000 |
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#define PLL_FBKDIV_16 0x00000000 |
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#define PLL_FBKDIV_1 0x00100000 |
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#define PLL_FBKDIV_2 0x00200000 |
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#define PLL_FBKDIV_3 0x00300000 |
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#define PLL_FBKDIV_4 0x00400000 |
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#define PLL_FBKDIV_5 0x00500000 |
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#define PLL_FBKDIV_6 0x00600000 |
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#define PLL_FBKDIV_7 0x00700000 |
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#define PLL_FBKDIV_8 0x00800000 |
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#define PLL_FBKDIV_9 0x00900000 |
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#define PLL_FBKDIV_10 0x00A00000 |
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#define PLL_FBKDIV_11 0x00B00000 |
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#define PLL_FBKDIV_12 0x00C00000 |
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#define PLL_FBKDIV_13 0x00D00000 |
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#define PLL_FBKDIV_14 0x00E00000 |
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#define PLL_FBKDIV_15 0x00F00000 |
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/* Forward A divisor */ |
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#define PLL_FWDDIVA 0x00070000 |
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#define CPC0_PLLMR1_FWDVA 0x00070000 |
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#define PLL_FWDDIVA_8 0x00000000 |
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#define PLL_FWDDIVA_7 0x00010000 |
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#define PLL_FWDDIVA_6 0x00020000 |
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#define PLL_FWDDIVA_5 0x00030000 |
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#define PLL_FWDDIVA_4 0x00040000 |
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#define PLL_FWDDIVA_3 0x00050000 |
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#define PLL_FWDDIVA_2 0x00060000 |
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#define PLL_FWDDIVA_1 0x00070000 |
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/* Forward B divisor */ |
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#define PLL_FWDDIVB 0x00007000 |
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#define CPC0_PLLMR1_FWDVB 0x00007000 |
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#define PLL_FWDDIVB_8 0x00000000 |
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#define PLL_FWDDIVB_7 0x00001000 |
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#define PLL_FWDDIVB_6 0x00002000 |
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#define PLL_FWDDIVB_5 0x00003000 |
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#define PLL_FWDDIVB_4 0x00004000 |
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#define PLL_FWDDIVB_3 0x00005000 |
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#define PLL_FWDDIVB_2 0x00006000 |
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#define PLL_FWDDIVB_1 0x00007000 |
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/* PLL tune bits */ |
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#define PLL_TUNE_MASK 0x000003FF |
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#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ |
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#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ |
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#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ |
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#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ |
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#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ |
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#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ |
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#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ |
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/* Defines for CPC0_PLLMR0 Register fields */ |
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/* CPU divisor */ |
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#define PLL_CPUDIV 0x00300000 |
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#define CPC0_PLLMR0_CCDV 0x00300000 |
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#define PLL_CPUDIV_1 0x00000000 |
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#define PLL_CPUDIV_2 0x00100000 |
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#define PLL_CPUDIV_3 0x00200000 |
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#define PLL_CPUDIV_4 0x00300000 |
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/* PLB divisor */ |
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#define PLL_PLBDIV 0x00030000 |
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#define CPC0_PLLMR0_CBDV 0x00030000 |
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#define PLL_PLBDIV_1 0x00000000 |
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#define PLL_PLBDIV_2 0x00010000 |
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#define PLL_PLBDIV_3 0x00020000 |
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#define PLL_PLBDIV_4 0x00030000 |
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/* OPB divisor */ |
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#define PLL_OPBDIV 0x00003000 |
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#define CPC0_PLLMR0_OPDV 0x00003000 |
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#define PLL_OPBDIV_1 0x00000000 |
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#define PLL_OPBDIV_2 0x00001000 |
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#define PLL_OPBDIV_3 0x00002000 |
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#define PLL_OPBDIV_4 0x00003000 |
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/* EBC divisor */ |
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#define PLL_EXTBUSDIV 0x00000300 |
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#define CPC0_PLLMR0_EPDV 0x00000300 |
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#define PLL_EXTBUSDIV_2 0x00000000 |
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#define PLL_EXTBUSDIV_3 0x00000100 |
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#define PLL_EXTBUSDIV_4 0x00000200 |
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#define PLL_EXTBUSDIV_5 0x00000300 |
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/* MAL divisor */ |
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#define PLL_MALDIV 0x00000030 |
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#define CPC0_PLLMR0_MPDV 0x00000030 |
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#define PLL_MALDIV_1 0x00000000 |
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#define PLL_MALDIV_2 0x00000010 |
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#define PLL_MALDIV_3 0x00000020 |
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#define PLL_MALDIV_4 0x00000030 |
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/* PCI divisor */ |
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#define PLL_PCIDIV 0x00000003 |
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#define CPC0_PLLMR0_PPFD 0x00000003 |
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#define PLL_PCIDIV_1 0x00000000 |
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#define PLL_PCIDIV_2 0x00000001 |
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#define PLL_PCIDIV_3 0x00000002 |
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#define PLL_PCIDIV_4 0x00000003 |
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/*
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*------------------------------------------------------------------------------- |
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* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, |
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* assuming a 33.3MHz input clock to the 405EP. |
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*------------------------------------------------------------------------------- |
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*/ |
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#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ |
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PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
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PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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/*
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* PLL Voltage Controlled Oscillator (VCO) definitions |
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* Maximum and minimum values (in MHz) for correct PLL operation. |
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*/ |
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#define VCO_MIN 500 |
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#define VCO_MAX 1000 |
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#else /* #ifdef CONFIG_405EP */ |
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/******************************************************************************
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* Control |
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******************************************************************************/ |
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@ -236,7 +489,8 @@ |
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#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ |
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#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ |
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#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ |
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#define ecr (0xAA) /* edge conditioning register (405GPr) */ |
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#define ecr (0xaa) /* edge conditioner register (405gpr) */ |
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/* Bit definitions */ |
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#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ |
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@ -300,6 +554,7 @@ |
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*/ |
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#define VCO_MIN 400 |
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#define VCO_MAX 800 |
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#endif /* #ifdef CONFIG_405EP */ |
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/******************************************************************************
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* Memory Access Layer |
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@ -364,6 +619,25 @@ |
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#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ |
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#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ |
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/******************************************************************************
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* GPIO macro register defines |
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******************************************************************************/ |
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#define GPIO_BASE 0xEF600700 |
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#define GPIO0_OR (GPIO_BASE+0x0) |
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#define GPIO0_TCR (GPIO_BASE+0x4) |
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#define GPIO0_OSRH (GPIO_BASE+0x8) |
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#define GPIO0_OSRL (GPIO_BASE+0xC) |
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#define GPIO0_TSRH (GPIO_BASE+0x10) |
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#define GPIO0_TSRL (GPIO_BASE+0x14) |
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#define GPIO0_ODR (GPIO_BASE+0x18) |
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#define GPIO0_IR (GPIO_BASE+0x1C) |
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#define GPIO0_RR1 (GPIO_BASE+0x20) |
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#define GPIO0_RR2 (GPIO_BASE+0x24) |
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#define GPIO0_ISR1H (GPIO_BASE+0x30) |
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#define GPIO0_ISR1L (GPIO_BASE+0x34) |
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#define GPIO0_ISR2H (GPIO_BASE+0x38) |
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#define GPIO0_ISR2L (GPIO_BASE+0x3C) |
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/*
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* Macro for accessing the indirect EBC register |
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stroese
21 years ago