Tom Rini
6 years ago
commit
b8a1f47be3
@ -0,0 +1,192 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP |
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*/ |
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#include <common.h> |
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#include <linux/libfdt.h> |
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#include <fdt_support.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#include <asm/arch-fsl-layerscape/fsl_icid.h> |
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#include <fsl_fman.h> |
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static void set_icid(struct icid_id_table *tbl, int size) |
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{ |
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int i; |
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for (i = 0; i < size; i++) |
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out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); |
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} |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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void set_fman_icids(struct fman_icid_id_table *tbl, int size) |
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{ |
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int i; |
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ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; |
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for (i = 0; i < size; i++) { |
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out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], |
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tbl[i].icid); |
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} |
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} |
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#endif |
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void set_icids(void) |
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{ |
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/* setup general icid offsets */ |
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set_icid(icid_tbl, icid_tbl_sz); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); |
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#endif |
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} |
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int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) |
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{ |
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int i, ret; |
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u32 prop[8]; |
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/*
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* Note: The "iommus" property definition mentions Stream IDs while |
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* this code handles ICIDs. The current implementation assumes that |
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* ICIDs and Stream IDs are equal. |
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*/ |
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for (i = 0; i < num_ids; i++) { |
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prop[i * 2] = cpu_to_fdt32(smmu_ph); |
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prop[i * 2 + 1] = cpu_to_fdt32(ids[i]); |
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} |
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ret = fdt_setprop(blob, off, "iommus", |
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prop, sizeof(u32) * num_ids * 2); |
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if (ret) { |
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printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret)); |
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return ret; |
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} |
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return 0; |
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} |
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int fdt_fixup_icid_tbl(void *blob, int smmu_ph, |
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struct icid_id_table *tbl, int size) |
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{ |
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int i, err, off; |
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for (i = 0; i < size; i++) { |
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if (!tbl[i].compat) |
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continue; |
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off = fdt_node_offset_by_compat_reg(blob, |
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tbl[i].compat, |
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tbl[i].compat_addr); |
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if (off > 0) { |
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err = fdt_set_iommu_prop(blob, off, smmu_ph, |
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&tbl[i].id, 1); |
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if (err) |
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return err; |
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} else { |
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printf("WARNING could not find node %s: %s.\n", |
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tbl[i].compat, fdt_strerror(off)); |
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} |
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} |
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return 0; |
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} |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl, |
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const int size) |
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{ |
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int i; |
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for (i = 0; i < size; i++) { |
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if (tbl[i].port_id == port_id) |
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return tbl[i].icid; |
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} |
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return -1; |
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} |
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void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph, |
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const char *compat) |
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{ |
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int noff, len, icid; |
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const u32 *prop; |
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noff = fdt_node_offset_by_compatible(blob, -1, compat); |
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while (noff > 0) { |
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prop = fdt_getprop(blob, noff, "cell-index", &len); |
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if (!prop) { |
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printf("WARNING missing cell-index for fman port\n"); |
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continue; |
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} |
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if (len != 4) { |
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printf("WARNING bad cell-index size for fman port\n"); |
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continue; |
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} |
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icid = get_fman_port_icid(fdt32_to_cpu(*prop), |
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fman_icid_tbl, fman_icid_tbl_sz); |
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if (icid < 0) { |
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printf("WARNING unknown ICID for fman port %d\n", |
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*prop); |
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continue; |
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} |
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fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1); |
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noff = fdt_node_offset_by_compatible(blob, noff, compat); |
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} |
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} |
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void fdt_fixup_fman_icids(void *blob, int smmu_ph) |
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{ |
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static const char * const compats[] = { |
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"fsl,fman-v3-port-oh", |
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"fsl,fman-v3-port-rx", |
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"fsl,fman-v3-port-tx", |
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}; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(compats); i++) |
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fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]); |
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} |
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#endif |
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int fdt_get_smmu_phandle(void *blob) |
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{ |
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int noff, smmu_ph; |
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noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500"); |
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if (noff < 0) { |
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printf("WARNING failed to get smmu node: %s\n", |
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fdt_strerror(noff)); |
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return noff; |
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} |
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smmu_ph = fdt_get_phandle(blob, noff); |
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if (!smmu_ph) { |
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smmu_ph = fdt_create_phandle(blob, noff); |
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if (!smmu_ph) { |
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printf("WARNING failed to get smmu phandle\n"); |
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return -1; |
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} |
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} |
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return smmu_ph; |
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} |
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void fdt_fixup_icid(void *blob) |
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{ |
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int smmu_ph; |
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smmu_ph = fdt_get_smmu_phandle(blob); |
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if (smmu_ph < 0) |
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return; |
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fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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fdt_fixup_fman_icids(blob, smmu_ph); |
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#endif |
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} |
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@ -0,0 +1,89 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP |
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*/ |
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#include <common.h> |
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#include <asm/arch-fsl-layerscape/immap_lsch2.h> |
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#include <asm/arch-fsl-layerscape/fsl_icid.h> |
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#include <asm/arch-fsl-layerscape/fsl_portals.h> |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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}; |
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#endif |
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struct icid_id_table icid_tbl[] = { |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), |
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SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), |
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#endif |
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SET_SDHC_ICID(FSL_SDHC_STREAM_ID), |
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SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), |
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SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), |
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SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), |
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SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID), |
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SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID), |
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SET_EDMA_ICID(FSL_EDMA_STREAM_ID), |
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SET_ETR_ICID(FSL_ETR_STREAM_ID), |
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SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), |
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#ifdef CONFIG_FSL_CAAM |
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SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), |
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SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), |
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SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), |
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SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), |
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SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6), |
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SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7), |
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SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8), |
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SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9), |
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SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10), |
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SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11), |
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SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12), |
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SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 13), |
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#endif |
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}; |
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int icid_tbl_sz = ARRAY_SIZE(icid_tbl); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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struct fman_icid_id_table fman_icid_tbl[] = { |
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/* port id, icid */ |
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SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), |
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}; |
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int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl); |
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#endif |
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@ -0,0 +1,115 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* Copyright 2018 NXP |
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*/ |
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#ifndef _FSL_ICID_H_ |
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#define _FSL_ICID_H_ |
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#include <asm/types.h> |
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#include <fsl_qbman.h> |
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#include <fsl_sec.h> |
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struct icid_id_table { |
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const char *compat; |
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u32 id; |
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u32 reg; |
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phys_addr_t compat_addr; |
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phys_addr_t reg_addr; |
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}; |
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struct fman_icid_id_table { |
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u32 port_id; |
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u32 icid; |
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}; |
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u32 get_ppid_icid(int ppid_tbl_idx, int ppid); |
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int fdt_get_smmu_phandle(void *blob); |
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int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); |
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void set_icids(void); |
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void fdt_fixup_icid(void *blob); |
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#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ |
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{ .compat = name, \
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.id = idA, \
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.reg = regA, \
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.compat_addr = compataddr, \
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.reg_addr = addr, \
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} |
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#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ |
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SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
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offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
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compataddr) |
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#define SET_USB_ICID(usb_num, compat, streamid) \ |
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SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
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CONFIG_SYS_XHCI_USB##usb_num##_ADDR) |
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#define SET_SATA_ICID(compat, streamid) \ |
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SET_SCFG_ICID(compat, streamid, sata_icid,\
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AHCI_BASE_ADDR) |
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#define SET_SDHC_ICID(streamid) \ |
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SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
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CONFIG_SYS_FSL_ESDHC_ADDR) |
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#define SET_QDMA_ICID(compat, streamid) \ |
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SET_SCFG_ICID(compat, streamid, dma_icid,\
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QDMA_BASE_ADDR) |
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#define SET_EDMA_ICID(streamid) \ |
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SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
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EDMA_BASE_ADDR) |
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#define SET_ETR_ICID(streamid) \ |
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SET_SCFG_ICID(NULL, streamid, etr_icid, 0) |
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#define SET_DEBUG_ICID(streamid) \ |
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SET_SCFG_ICID(NULL, streamid, debug_icid, 0) |
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#define SET_QMAN_ICID(streamid) \ |
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SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
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offsetof(struct ccsr_qman, liodnr) + \
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CONFIG_SYS_FSL_QMAN_ADDR, \
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CONFIG_SYS_FSL_QMAN_ADDR) |
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#define SET_BMAN_ICID(streamid) \ |
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SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
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offsetof(struct ccsr_bman, liodnr) + \
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CONFIG_SYS_FSL_BMAN_ADDR, \
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CONFIG_SYS_FSL_BMAN_ADDR) |
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#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ |
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{ .port_id = (_port_id), .icid = (streamid) } |
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#define SET_SEC_QI_ICID(streamid) \ |
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SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
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(((streamid) << 16) | (streamid)), \
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offsetof(ccsr_sec_t, qilcr_ls) + \
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CONFIG_SYS_FSL_SEC_ADDR, \
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CONFIG_SYS_FSL_SEC_ADDR) |
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#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ |
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SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
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(((streamid) << 16) | (streamid)), \
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offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
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CONFIG_SYS_FSL_SEC_ADDR, \
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FSL_SEC_JR##jr_num##_BASE_ADDR) |
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#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ |
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SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
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offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
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CONFIG_SYS_FSL_SEC_ADDR, 0) |
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#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ |
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SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
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offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
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CONFIG_SYS_FSL_SEC_ADDR, 0) |
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extern struct icid_id_table icid_tbl[]; |
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extern struct fman_icid_id_table fman_icid_tbl[]; |
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extern int icid_tbl_sz; |
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extern int fman_icid_tbl_sz; |
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#endif |
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@ -0,0 +1,24 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* Copyright 2018 NXP |
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*/ |
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#ifndef _FSL_PORTALS_H_ |
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#define _FSL_PORTALS_H_ |
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struct qportal_info { |
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u16 dicid; /* DQRR ICID */ |
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u16 ficid; /* frame data ICID */ |
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u16 icid; |
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u8 sdest; |
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}; |
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#define SET_QP_INFO(streamid, dest) \ |
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{ .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
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.sdest = (dest) } |
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extern struct qportal_info qp_info[]; |
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void fdt_portal(void *blob, const char *compat, const char *container, |
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u64 addr, u32 size); |
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|
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#endif |
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