Add the initial SPL support for HummingBoard-i2eX, which is based on a MX6 Dual. For more information about HummingBoard, please check: http://www.solid-run.com/products/hummingboard/ Based on the work from Jon Nettleton and Rabeeh Khoury. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>master
Fabio Estevam
9 years ago
committed by
Stefano Babic
parent
08daa258e6
commit
b8ce6fe261
@ -0,0 +1,15 @@ |
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if TARGET_MX6CUBOXI |
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config SYS_BOARD |
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default "mx6cuboxi" |
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config SYS_VENDOR |
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default "solidrun" |
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config SYS_SOC |
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default "mx6" |
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config SYS_CONFIG_NAME |
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default "mx6cuboxi" |
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endif |
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@ -0,0 +1,6 @@ |
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MX6CUBOXI BOARD |
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M: Fabio Estevam <fabio.estevam@freescale.com> |
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S: Maintained |
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F: board/solidrun/mx6cuboxi/ |
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F: include/configs/mx6cuboxi.h |
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F: configs/mx6cuboxi_spl_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6cuboxi.o
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@ -0,0 +1,21 @@ |
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How to use U-boot on Solid-run mx6 hummingboard |
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----------------------------------------------- |
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- Build U-boot for hummingboard: |
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$ make mrproper |
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$ make mx6cuboxi_defconfig |
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$ make |
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This will generate the SPL image called SPL and the u-boot.img. |
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- Flash the SPL image into the SD card: |
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sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync |
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- Flash the u-boot.img image into the SD card: |
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sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync |
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- Insert the SD card in the hummingboard, power it up and U-boot messages |
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should come up. |
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@ -0,0 +1,330 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* Author: Fabio Estevam <fabio.estevam@freescale.com> |
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* |
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> |
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* |
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* Based on SPL code from Solidrun tree, which is: |
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* Author: Tungyi Lin <tungyilin1127@gmail.com> |
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* |
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* Derived from EDM_CF_IMX6 code by TechNexion,Inc |
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* Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/errno.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/io.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mx6-ddr.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
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#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) |
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int dram_init(void) |
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{ |
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gd->ram_size = imx_ddr_size(); |
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return 0; |
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} |
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static iomux_v3_cfg_t const uart1_pads[] = { |
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc2_pads[] = { |
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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} |
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static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC2_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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return 1; /* uSDHC2 is always present */ |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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} |
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static iomux_v3_cfg_t const enet_pads[] = { |
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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/* AR8035 reset */ |
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
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/* AR8035 interrupt */ |
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MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* GPIO16 -> AR8035 25MHz */ |
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ |
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), |
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
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}; |
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static void setup_iomux_enet(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
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gpio_direction_output(ETH_PHY_RESET, 0); |
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mdelay(2); |
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gpio_set_value(ETH_PHY_RESET, 1); |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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if (phydev->drv->config) |
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phydev->drv->config(phydev); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
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int ret = enable_fec_anatop_clock(ENET_25MHZ); |
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if (ret) |
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return ret; |
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/* set gpr1[ENET_CLK_SEL] */ |
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); |
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setup_iomux_enet(); |
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return cpu_eth_init(bis); |
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} |
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int board_early_init_f(void) |
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{ |
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setup_iomux_uart(); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: MX6 Hummingboard\n"); |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { |
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.dram_sdclk_0 = 0x00020030, |
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.dram_sdclk_1 = 0x00020030, |
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.dram_cas = 0x00020030, |
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.dram_ras = 0x00020030, |
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.dram_reset = 0x00020030, |
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.dram_sdcke0 = 0x00003000, |
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.dram_sdcke1 = 0x00003000, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdodt0 = 0x00003030, |
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.dram_sdodt1 = 0x00003030, |
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.dram_sdqs0 = 0x00000030, |
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.dram_sdqs1 = 0x00000030, |
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.dram_sdqs2 = 0x00000030, |
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.dram_sdqs3 = 0x00000030, |
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.dram_sdqs4 = 0x00000030, |
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.dram_sdqs5 = 0x00000030, |
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.dram_sdqs6 = 0x00000030, |
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.dram_sdqs7 = 0x00000030, |
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.dram_dqm0 = 0x00020030, |
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.dram_dqm1 = 0x00020030, |
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.dram_dqm2 = 0x00020030, |
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.dram_dqm3 = 0x00020030, |
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.dram_dqm4 = 0x00020030, |
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.dram_dqm5 = 0x00020030, |
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.dram_dqm6 = 0x00020030, |
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.dram_dqm7 = 0x00020030, |
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}; |
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { |
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.grp_ddr_type = 0x000C0000, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_addds = 0x00000030, |
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.grp_ctlds = 0x00000030, |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = 0x00000030, |
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.grp_b1ds = 0x00000030, |
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.grp_b2ds = 0x00000030, |
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.grp_b3ds = 0x00000030, |
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.grp_b4ds = 0x00000030, |
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.grp_b5ds = 0x00000030, |
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.grp_b6ds = 0x00000030, |
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.grp_b7ds = 0x00000030, |
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}; |
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static const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
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.p0_mpwldectrl0 = 0x00000000, |
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.p0_mpwldectrl1 = 0x00000000, |
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.p1_mpwldectrl0 = 0x00000000, |
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.p1_mpwldectrl1 = 0x00000000, |
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.p0_mpdgctrl0 = 0x0314031c, |
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.p0_mpdgctrl1 = 0x023e0304, |
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.p1_mpdgctrl0 = 0x03240330, |
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.p1_mpdgctrl1 = 0x03180260, |
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.p0_mprddlctl = 0x3630323c, |
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.p1_mprddlctl = 0x3436283a, |
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.p0_mpwrdlctl = 0x36344038, |
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.p1_mpwrdlctl = 0x422a423c, |
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}; |
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static struct mx6_ddr3_cfg mem_ddr = { |
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.mem_speed = 1600, |
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.density = 2, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 14, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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.SRT = 1, |
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}; |
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static void ccgr_init(void) |
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{ |
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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writel(0x00C03F3F, &ccm->CCGR0); |
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writel(0x0030FC03, &ccm->CCGR1); |
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writel(0x0FFFC000, &ccm->CCGR2); |
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writel(0x3FF00000, &ccm->CCGR3); |
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writel(0x00FFF300, &ccm->CCGR4); |
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writel(0x0F0000C3, &ccm->CCGR5); |
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writel(0x000003FF, &ccm->CCGR6); |
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} |
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static void gpr_init(void) |
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{ |
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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writel(0xF00000CF, &iomux->gpr[4]); |
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
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writel(0x007F007F, &iomux->gpr[6]); |
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writel(0x007F007F, &iomux->gpr[7]); |
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} |
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/*
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* This section requires the differentiation between Solidrun mx6 boards, but |
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* for now, it will configure only for the mx6dual hummingboard version. |
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*/ |
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static void spl_dram_init(void) |
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{ |
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struct mx6_ddr_sysinfo sysinfo = { |
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/* width of data bus: 0=16, 1=32, 2=64 */ |
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.dsize = 2, |
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/* config for full 4GB range so that get_mem_size() works */ |
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.cs_density = 32, /* 32Gb per CS */ |
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.ncs = 1, /* single chip select */ |
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.cs1_mirror = 0, |
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
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.walat = 1, /* Write additional latency */ |
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.ralat = 5, /* Read additional latency */ |
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.mif3_mode = 3, /* Command prediction working mode */ |
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.bi_on = 1, /* Bank interleaving enabled */ |
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
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}; |
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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/* setup AIPS and disable watchdog */ |
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arch_cpu_init(); |
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ccgr_init(); |
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gpr_init(); |
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/* iomux and setup of i2c */ |
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board_early_init_f(); |
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/* setup GP timer */ |
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timer_init(); |
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/* UART clocks enabled and gd valid - init serial console */ |
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preloader_console_init(); |
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/* DDR initialization */ |
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spl_dram_init(); |
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/* Clear the BSS. */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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/* load/boot image from boot device */ |
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board_init_r(NULL, 0); |
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} |
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#endif |
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@ -0,0 +1,6 @@ |
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CONFIG_SPL=y |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" |
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CONFIG_ARM=y |
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CONFIG_TARGET_MX6CUBOXI=y |
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CONFIG_DM=y |
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CONFIG_DM_THERMAL=y |
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@ -0,0 +1,205 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* Configuration settings for the SolidRun mx6 based boards |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __MX6CUBOXI_CONFIG_H |
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#define __MX6CUBOXI_CONFIG_H |
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#include <linux/sizes.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/imx-common/gpio.h> |
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#include "mx6_common.h" |
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#define CONFIG_MX6 |
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#define CONFIG_SPL_LIBCOMMON_SUPPORT |
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#define CONFIG_SPL_MMC_SUPPORT |
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#include "imx6_spl.h" |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_REVISION_TAG |
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#define CONFIG_IMX6_THERMAL |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_MXC_GPIO |
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#define CONFIG_MXC_UART |
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#define CONFIG_CMD_FUSE |
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#define CONFIG_MXC_OCOTP |
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/* MMC Configs */ |
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#define CONFIG_FSL_ESDHC |
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#define CONFIG_FSL_USDHC |
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
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#define CONFIG_MMC |
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#define CONFIG_CMD_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_BOUNCE_BUFFER |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_EXT4_WRITE |
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#define CONFIG_CMD_FAT |
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#define CONFIG_DOS_PARTITION |
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/* Ethernet Configuration */ |
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#define CONFIG_FEC_MXC |
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#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_ATHEROS |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/* Command definition */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#define CONFIG_BOOTDELAY 1 |
||||
|
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
#define CONFIG_CONSOLE_DEV "ttymxc0" |
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" |
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6q-hummingboard.dtb" |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"console=" CONFIG_CONSOLE_DEV "\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* Environment organization */ |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (8 * 64 * 1024) |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_CACHE |
||||
|
||||
#endif /* __MX6CUBOXI_CONFIG_H */ |
||||
Loading…
Reference in new issue