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@ -23,6 +23,7 @@ extern struct xilinx_fpga_op zynq_op; |
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#define XILINX_ZYNQ_7015 0x1b |
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#define XILINX_ZYNQ_7020 0x7 |
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#define XILINX_ZYNQ_7030 0xc |
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#define XILINX_ZYNQ_7035 0x12 |
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#define XILINX_ZYNQ_7045 0x11 |
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#define XILINX_ZYNQ_7100 0x16 |
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@ -31,6 +32,7 @@ extern struct xilinx_fpga_op zynq_op; |
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#define XILINX_XC7Z015_SIZE 28085344/8 |
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#define XILINX_XC7Z020_SIZE 32364512/8 |
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#define XILINX_XC7Z030_SIZE 47839328/8 |
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#define XILINX_XC7Z035_SIZE 106571232/8 |
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#define XILINX_XC7Z045_SIZE 106571232/8 |
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#define XILINX_XC7Z100_SIZE 139330784/8 |
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@ -51,6 +53,10 @@ extern struct xilinx_fpga_op zynq_op; |
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{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z030" } |
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#define XILINX_XC7Z035_DESC(cookie) \ |
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{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z035" } |
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#define XILINX_XC7Z045_DESC(cookie) \ |
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{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
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"7z045" } |
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