This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
Shengzhou Liu
8 years ago
committed by
York Sun
parent
93a6d3284c
commit
b9e745bbe2
@ -0,0 +1,156 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Generic driver for Freescale MMDC(Multi Mode DDR Controller). |
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*/ |
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#include <common.h> |
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#include <fsl_mmdc.h> |
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#include <asm/io.h> |
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) |
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{ |
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int timeout = 1000; |
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out_be32(ptr, value); |
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while (in_be32(ptr) & bits) { |
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udelay(100); |
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timeout--; |
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} |
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if (timeout <= 0) |
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printf("Error: %p wait for clear timeout.\n", ptr); |
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} |
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void mmdc_init(void) |
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{ |
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struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR; |
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unsigned int tmp; |
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/* 1. set configuration request */ |
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); |
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/* 2. configure the desired timing parameters */ |
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out_be32(&mmdc->mdotc, CONFIG_MMDC_MDOTC); |
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out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0); |
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out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1); |
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out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2); |
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/* 3. configure DDR type and other miscellaneous parameters */ |
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out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC); |
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out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR); |
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out_be32(&mmdc->mdrwd, CONFIG_MMDC_MDRWD); |
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out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL); |
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/* 4. configure the required delay while leaving reset */ |
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out_be32(&mmdc->mdor, CONFIG_MMDC_MDOR); |
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/* 5. configure DDR physical parameters */ |
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/* set row/column address width, burst length, data bus width */ |
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tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1); |
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out_be32(&mmdc->mdctl, tmp); |
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/* configure address space partition */ |
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out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP); |
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/* 6. perform a ZQ calibration - not needed here, doing in #8b */ |
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/* 7. enable MMDC with the desired chip select */ |
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#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1) |
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out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0); |
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#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2) |
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out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1); |
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#endif |
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/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */ |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2); |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); |
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) | |
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CMD_ADDR_LSB_MR_ADDR(0x30) | |
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MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0); |
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/* 8b. ZQ calibration */ |
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ | |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0); |
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl, CONFIG_MMDC_MPZQHWCTRL, |
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MPZQHWCTRL_ZQ_HW_FORCE); |
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/* 9a. calibrations now, wr lvl */ |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) | |
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MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); |
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN | |
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CMD_NORMAL); |
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set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN, |
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MPWLGCR_HW_WL_EN); |
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mdelay(1); |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); |
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); |
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mdelay(1); |
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/* 9b. read DQS gating calibration */ |
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0); |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); |
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out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN); |
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/* set absolute read delay offset */ |
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#if defined(CONFIG_MMDC_MPRDDLCTL) |
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out_be32(&mmdc->mprddlctl, CONFIG_MMDC_MPRDDLCTL); |
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#else |
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out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY); |
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#endif |
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set_wait_for_bits_clear(&mmdc->mpdgctrl0, |
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AUTO_RD_DQS_GATING_CALIBRATION_EN, |
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AUTO_RD_DQS_GATING_CALIBRATION_EN); |
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_3); |
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/* 9c. read calibration */ |
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0); |
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); |
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out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN); |
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set_wait_for_bits_clear(&mmdc->mprddlhwctl, |
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN, |
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN); |
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_3); |
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/* 10. configure power-down, self-refresh entry, exit parameters */ |
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out_be32(&mmdc->mdpdc, CONFIG_MMDC_MDPDC); |
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out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT); |
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/* 11. ZQ config again? do nothing here */ |
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/* 12. refresh scheme */ |
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set_wait_for_bits_clear(&mmdc->mdref, CONFIG_MMDC_MDREF, |
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MDREF_START_REFRESH); |
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/* 13. disable CON_REQ */ |
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out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ); |
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} |
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